itor, as shown in Figure 1. The function of thebias tee is to simultaneously allow a DC biasvoltage and an RF test signal to be applied tothe port of a transistor during measurement.For example, in an S-parameter measurementsystem, the DC bias is applied at the port la-beled DC, and the RF test signal from thevector network analyzer is applied to the portlabeled RF. At the RF + DC port, both theRF and DC voltages are applied to the device.

CHARLES BAYLISUniversity of South FloridaTampa, FLLAWRENCE DUNLEAVYUniversity of South Florida

and Modelithics Inc.Tampa, FLWILLIAM CLAUSENModelithics Inc.Tampa, FL

This article describes the design of a biastee for a pulsed-bias, pulsed-RF testsystem. The cut-off frequency of theDC path was raised to allow pulsing of thebias signal. The theory of bias tee design forpulsed measurements is first presented. Thesimulation results for the design without theuse of component models are presented, fol-lowed by simulation results obtained using ac-curate parasitic models for the inductor andcapacitor used. The simulation results arethen compared with S-parameter measure-ments obtained using a TRL calibration andfound to show good agreement. Finally, illus-trations of the accurate use of the bias tees inperforming both pulsed IV and pulsed S-

parameter measurements areprovided.

BIAS TEE DESIGNA typical bias tee circuit con-

sists of an inductor and a capac-

DESIGN OF BIAS TEESFOR A PULSED-BIAS,PULSED-RF TEST SYSTEMUSING ACCURATECOMPONENT MODELS

In this article, a design of custom bias tees to be used in a pulsed-bias, pulsed-RF measurement systemis described. The bias tee design is such that the DC path allows bias pulses to pass through to thedevice unchanged, while still allowing RF measurements at as low a frequency as possible. The use ofaccurate component models led to a successful simulation-based development of a bias tee with a(three-port) frequency response that allows accurate pulsed S-parameter and pulsed IV measurementresults to be achieved in the desired bandwidth.

DC + RF

DC

RF

t Fig. 1 Bias tee circuit.

Reprinted with permission of MICROWAVE JOURNAL from the October 2006 issue.2006 Horizon House Publications, Inc.

The purpose of the inductor is to pre-vent the RF signal from entering theDC path, and the purpose of the ca-pacitor is to keep the DC signal fromentering the RF path. The inductorand capacitor should be designedsuch that the upper cut-off frequencyof the low pass DC path is lower thanthe lower cut-off frequency of thehigh pass RF path. If this is true, thenthe lower cut-off frequency of the RFpath containing the capacitor (consid-ering the inductor to be an open cir-cuit) is given by

where R is the total resistance seen atthe capacitor terminals. In this case, thetermination at the RF port is 50 andthe termination at the RF + DC port islarge (either the input or output im-pedance of the device) in normal oper-ation but will be 50 in the bias tee

fRCc AC,

( )=1

21

pi

test setup. In opera-tion, however, thevalue of the input re-sistance will be fairlylarge, changing thecut-off frequency.However, in a 50 test system, 50 isthe impedance at alltest ports. This setupwill be used for thepurpose of bench-marking the behav-ior of the devicethrough measure-

ment and simulation. Thus, R = 50 + 50= 100 for this case.

The cut-off frequency of the DCpath, assuming that the capacitor ap-pears as an open circuit, is given by

In this case, R is equal to the sum ofthe impedance presented by the biasequipment and the input impedanceto the device under test. For a 50 test system, R = 50 + 50 = 100 .

The outstanding factor for apulsed bias tee design is that the cut-off frequency of the DC path must behigh enough to allow the pulsed biassignal to proceed unabated from theDC to the RF + DC ports. In thiscase, the smallest pulse length to beused for pulsing the bias is approxi-mately 100 ns. The frequency contentof this pulse is a (sin x)/x functioncentered at a frequency of 1/(100 109) = 10 MHz. Thus, the upper cut-off frequency of the bias networkshould be greater than 10 MHz, large

fRLc AC,

( )=2

2pi

enough that the entire frequencycontent of the pulse can pass throughthe DC path without distortion; thiswill allow the integrity of the pulseshape to be maintained.

Initial values for the inductor andcapacitor were chosen and simulationscontaining ideal elements were per-formed to ensure the selection ofcomponent values that will provide ad-equate cut-off frequencies for the DCand RF paths. The simulations wereperformed using Agilent TechnologiesAdvanced Design System (ADS). Thesimulation circuit and results for idealcomponent values of C = 100 pF andL = 27 nH are shown in Figures 2and 3, respectively. For these compo-nent values, the 3 dB cut-off frequen-cy of the RF path is shown to be 151MHz and the cut-off frequency of theDC path is shown to be 61 MHz.

SIMULATION RESULTSSimulations were performed for

the selected component values L = 27nH and C = 100 pF. The simulationwas performed at three different lev-els. At each level, both S-parametersand transient simulations were run.The purpose of the S-parameterssimulation is to ensure that the RFpath of the bias tee passes the signalwhile the DC path does not at RFfrequencies. The transient simulationis used to show that the pulse can ac-curately reach the RF + DC portwithout being significantly distortedin the time domain. Three levels ofsimulation were incorporated intothis effort: (1) ideal components andno transmission lines; (2) ideal com-

TECHNICAL FEATURE

Z=50Port 1

L1=27nH

Port 2

Z=50Port 3

Z=50

+

-

+

-

+

-

C1=100pF

s Fig. 2 Circuit with ideal components and without microstrip linesused in simulation.

S 31 (d

B)

RF to RF + DC PATH0

10

20

30

400 100 200

FREQUENCY (MHz)

300 400 500

S 32 (d

B)

0

10

20

30

400 100 200

FREQUENCY (MHz)

300 400 500

DC to RF + DC PATH

s Fig. 3 Simulated S-parameters for theideal circuit.

0

10

20

30

40

0

10

20

30

40

S 21 (d

B),

S 31 (d

B)

S 11 (d

B)

0 2 0FREQUENCY (GHz)

6 8 10

0 2 0FREQUENCY (GHz)

6 8 10

s Fig. 4 Simulated S-parameters for theideal circuit.

VO

UT

(V),

VIN

(V

) 6543210

1

0 1 2 3 4 5TIME (s)

1 s PULSE

0.1 s PULSE

6 7 8 9 10

VO

UT

(V),

VIN

(V

) 6543210

1

0 0.2 0.4TIME (s)

0.6 0.8 1.0

s Fig. 5 Simulated transient results.

TECHNICAL FEATURE

ponents with microstrip (FR-4 sub-strate) transmission lines; and (3)lumped component parasitic modelsdeveloped by Modelithics, combinedwith microstrip transmission linemodels built-in to Agilent ADS. Thefirst level was used to assess the opti-mum inductance and capacitance val-ues, as shown in the previous section;the second and third levels are usedto view non-idealities introduced bythe substrate (second level) and com-ponent parasitics (third level).

For the first-level schematic, thesimulation results are displayed inFigures 4 and 5. They show that theS-parameter results are as desired.From approximately 500 MHz andabove, S31 is high (which means thatmost of the input signal is getting to

Z=50

Port 1

TL 1MSub1

W=3.03mmL=5mm

C1=100pF TL2MSub1

W=3.03mmL=5mm

TL5MSub1

W=3.03mmL=5mm

TL4MSub1

W=3.03mmL=5mm

L=1L=27nH

TL3MSub1

W=3.03mmL=5mm

Port 2

H=1.58mmr=4.3Mur=1

Cond=1.0E+50Hu=3.9e+0.34mil

T=0.035mmTan=0.02

Rough=0mil

Tee1MSub1

W1=3.03mmW2= 3.03mmW3=3.03mm

Z=50

Port 3

+

Z=50MSub

-

+

-

+

-

s Fig. 6 Simulated circuit with microstrip lines and ideal components.

S 21 (

dB),

S 31 (

dB) 0

10

20

30

400 2 4

FREQUENCY (GHz)6 8 10

S 11 (

dB)

0

10

20

30

400 2 4

FREQUENCY (GHz)6 8 10

s Fig. 7 Simulated S-parameters for thecircuit with microstrip lines.

VO

UT

(V),

VIN

(V

) 6543210

10 1 2 3 4 5

TIME (s)

1 s PULSE

0.1 s PULSE

6 7 8 9 10

VO

UT

(V),

VIN

(V

) 6543210

10 0.2 0.4

TIME (s)0.6 0.8 1.0

s Fig. 8 Simulated transients from DC to RF+ DC ports for the circuit with microstrip lines.

Z=50

Port 1

TL1MSub1

W=3.03mmL=5mm

Step 2MSub1

W1=1.1mmW2=3.03mm

TL2MSub1

W=3.03mmL=5mm

TL5MSub1

W=3.03mmL=5mm

TL4MSub1

W=3.03mmL=5mm

L=27nHH=1.58mm

r=4.3T=0.035mmTan=0.02

Sim_mode=0Tolerance=1

Step3MSub1

W1=3.03mmW2=0.8mm

TL3MSub1

W=3.03mmL=5mm

Port 2

Step 4MSub1

W1=0.8mmW2=3.03mm

H=1.58mmr=4.3Mur=1

Cond=1.0E+50Hu=3.9e=0.34mil

T=0.035mmTan=0.02

Rough=0mil

C=100pfH=1.58mm

r=4.3Mur=1

T=0.035mmTan=0.02

Sim_mode=0Tolerance=1

Tee1MSub1

W1=3.03mmW2=3.03mmW3=3.03mm

Step 1MSub1

W1=3.03W2=1.1mm

Z=50

Port 3

Z=50MSub

+

-

+

-

+

-

s Fig. 9 Simulated circuit with parasitic models for lumped components and microstrip lines.

the RF + DC output) and S21 is low(very little signal is going from theRF port to the DC port). Also, S11 isbelow approximately 20 dB for allfrequencies greater than approxi-mately 1.7 GHz. These results showthat the choice of component valuesseems reasonable for a large RF pass-band. The transient simulation re-veals whether the bias tee will allowaccurate transmission of pulses fromthe DC port to the RF + DC port.The results show that a 1 s squarepulse sent from the DC port appearsvirtually undistorted at the RF + DCport, and a 0.1 s pulse also goesthrough the system with only minimalovershoot at the rising and fallingedges of the pulse. Since 0.1 s isshort enough for isodynamic mea-

surements, it appears that this biastee is designed correctly with regardto the DC path passband.

The next step was the incorpora-tion of microstrip lines into the simu-lation. Ideal components, however,were still used for the inductor andcapacitor, as shown in Figure 6. Thesubstrate parameters used in theMSUB element are those for theFR-4 substrate to be used in millingthe circuit. Figure 7 shows the S-pa-rameters simulation results for themicrostrip circuit. While the circuitbehavior is still close to ideal up toapproximately 5 GHz, there is a steepdrop in S31 at approximately 8 GHz.In addition, the input match becomesworse as the frequency increases,reaching a peak at the same locationas the notch in S31. However, thesesimulations indicate that the bias teeshould be useful in applications up to6 GHz. The transient simulations areshown in Figure 8. Excellent pulseintegrity is obtained at the RF + DCport.

Finally, the simulations were per-formed using detailed models for thecomponents to be used in the circuit: aTDK 27 nH size 0603 inductor and anATC 100 pF size 0603 capacitor. Themodels include the bond pads, so thesewere not included in the microstripcomponents. However, it is necessaryto include these bond pads in theschematic for the layout generation.

Figure 9 shows the schematic usedfor the simulation. Figure 10 displaysthe S-parameters simulation results.The plots show that the response con-cerning the RF to DC port and RF toRF + DC port transmissions is ade-quate at frequencies below 4 GHz.However, at 4.5 GHz, more transmis-sion is occurring from the RF port tothe DC port than from the RF port tothe RF + DC port. In addition, the in-put match at this frequency is relativelypoor, as evidenced in the S11 plot.These non-ideal effects are due to thecomponent parasitics, since the mi-crostrip line elements added in the sec-ond simulation stage did not cause sucheffects at these frequencies. They willlimit the frequency range for which thebias tee will be able to be accuratelyused in S-parameter measurements.Figure 11 shows the transient simula-tion results for the bias tee. It appearsthat the height of the pulse at the RF +DC port is slightly lower than at the in-

put. This is likely due to the non-idealresistance of the components that is in-cluded in the models but is not takeninto account in the ideal componentdefinitions used for the simulationswhose results were previously dis-played. The use of three levels of simu-lation has shown that both the trans-mission line elements and the parasiticeffects of the components have a sub-stantial impact on the S-parameterssimulation results. With the addition ofthe transmission line elements andcomponent models, it was seen thatsome non-ideal effects are expected tooccur above 4 GHz.

LAYOUT AND FABRICATIONThe bias tees were constructed by

mounting the components on a 59-milthick FR4 substrate. The circuit boardwas fabricated in the University ofSouth Florida (USF) Wireless and Mi-crowave Instructional (WAMI) Labora-tory. The layout for milling was gener-ated using a schematic in AdvancedDesign System with the componentsreplaced by bond pads and a small gap.The bond pads were not part of theprevious schematics used for simula-tion because the effects of the bondpads were included in the models forthe simulations. The schematic used togenerate the layout is shown in Figure12 and the layout generated by ADSfor milling is shown in Figure 13.

S-PARAMETER MEASUREMENTSOF BIAS TEES

To test the accuracy of the modelsin predicting the behavior of the biastees, S-parameter measurements wereperformed over a frequency range of40 MHz to 6 GHz using an Anritsu37397C Lightning vector networkanalyzer. A through-reflect-line (TRL)calibration was used for the measure-ment. The 59-mil FR4 standards usedfor this calibration have coaxial-to-mi-crostrip adapters at each port. Thelength of the standards was measuredin the USF laboratory. The throughstandard was measured to be 10.00mm, while the delay standard wasmeasured as 18.64 mm. The open wasoffset by half of the through standardline length. The calibration was per-formed using the Multical Softwarecreated by the National Institute ofStandards and Technology (NIST). Areference impedance of 50 and aneffective relative permittivity of 3.3

TECHNICAL FEATURES 21

(dB

), S 31

(dB

) 0102030405060

0 2 4FREQUENCY (GHz)

6 8 10

S 11 (

dB)

05

1015202530

0 2 4FREQUENCY (GHz)

6 8 10

s Fig. 10 Simulated S-parameters for thecircuit with parasitic models for lumpedcomponents and microstrip lines.

VO

UT

(V),

VIN

(V

)

1.0 s PULSE

TIME (s )

4

3

2

1

0

10 1 2 3 4 5 6 7 8 9 10

VO

UT

(V),

VIN

(V

)

0.1 s PULSE

TIME (s )

4

3

2

1

0

10 0.2 0.4 0.6 0.8 1.0

s Fig. 11 Simulated transients from DC toRF + DC ports for the circuit with microstriplines and parasitic lumped componentsmodels.

were used. The reference plane wasset to be 5 mm from the center of thethrough, placing it at the beginning ofthe microstrip line, just on the mi-crostrip side of the coaxial-to-mi-crostrip adapter at each port. Figure14 shows plots of S31, the RF to RF +DC transmission, in dB magnitude andphase. The largest difference betweenthe results in both magnitude andphase occurs between 5 and 6 GHz.

The measured versus simulated(without microstrip-to-coaxial adapters)

results for S21 (the RF to DC transmis-sion) are shown in Figure 15. Themagnitude of S21 should be low at allfrequencies. A very good agreement isobtained between the measured andsimulated data in both magnitude andphase. Measured and simulated resultsfor S32 (DC to RF + DC transmission)are shown in Figure 16. The magni-tude of this transmission is expected tobe low except at low frequencies. Themagnitude match is excellent between

TECHNICAL FEATURE

Z=50

Port 1

TL1MSub1

W=3.03mmL=5mm

TL6MSub1

W=1.1mmL=0.67mm

Gap1MSub1

W=1.1mmS=0.63mm

TL7MSub1

W=1.1mmL=0.67mm

Step 2MSub1

W1=1.1mmW2=0.67mm

TL2MSub1

W=3.03mmL=5mm

TL5MSub1

W=3.03mmL=5mm

TL4MSub1

W=3.03mmL=5mm

TL9MSub1

W=0.8mmL=0.63mm

TL8MSub1

W=0.8mmL=0.63mm

Step3MSub1

W1=3.03mmW2=0.8mm

TL3MSub1

W=3.03mmL=5mm

Port 2

Gap2MSub1

W=0.8mmS=0.63mm

Step 4MSub1

W1=0.8mmW2=Wmm

H=1.58mmr=4.3Mur=1

Cond=1.0E+50Hu=3.9e+0.34mil

T=0.035mmTan=0.02

Rough=0mil

Tee1MSub1

W1=3.03mmW2=3.03mmW3=3.03mm

Step 1MSub1

W1=3.03W2=1.1mm

Z=50

Port 3

Z=50

MSub

+

-

+

-

+

-

s Fig. 12 ADS schematic for layout generation.

S 31 (

dB)

0

5

10

150 1 2

FREQUENCY (GHz)

MEASUREDSIMULATED

3 4 5

S31

()

200

100

0

100

2000 1 2

FREQUENCY (GHz)3 4 5

s Fig. 14 Measured and simulated S31(RF to RF + DC transmission).

s Fig. 13 Bias tee layout for FR4 milling.

S 21 (

dB)

0102030405060

0 1 2FREQUENCY (GHz)

3 4 5

MEASUREDSIMULATED

S21

()

200

100

0

100

2000 1 2

FREQUENCY (GHz)3 4 5

s Fig. 15 Measured and simulated S21(RF to DC transmission).

S 32 (

dB)

MEASUREDSIMULATED

0102030405060

0 1 2

FREQUENCY (GHz)

3 4 5

S32

()

200

100

0

100

2000 1 2

FREQUENCY (GHz)

3 4 5

s Fig. 16 Measured and simulated S32(DC to RF + DC transmission).

measured and simulated results overthe entire measurement band for bothS21 and S32.

Figure 17 shows the measuredand simulated input reflection coeffi-cient results for all three ports. Thesimulation and measured reflectionparameters match well at lower fre-quencies; however, some differencesexist at higher frequencies. The simu-lated parameters have larger magni-tude in each case at the higher fre-

quencies, especially S33. This may bedue to the difficulty of obtaining agood reflection calibration using a 59-mil FR4 substrate with SMA-to-mi-crostrip adapters at higher frequen-cies. Figures 18, 19 and 20 displaythe reflection parameters as mag-nitude and phase versus frequency.

In general, the S-parameter resultsshow good agreement from 40 MHz to5 GHz. This data seems to indicate thatthe models have accurately predicted

the performance of the design on thefirst pass.

PULSED IV MEASUREMENTTHROUGH BIAS TEES

In addition to testing the RF perfor-mance of the bias tee, it is also impor-tant to ensure that the circuit allows apulsed bias to be correctly applied to adevice under test. A good test methodfor this is to attempt to perform pulsedIV measurements through the bias teesas attempted previously;1 if the biastees do not distort the IV curves, theyare adequate for applying a pulsed biasto an RF measurement system. In thisexperiment, pulsed IV measurementswith pulse lengths varying from 0.1 to1000 s were performed on a GaAsMESFET, using an Accent OpticalTechnologies Dynamic i(V) Analyzer(DiVA) model D225. The measure-ments were performed for three se-tups: (1) no bias tees; (2) a set of com-mercially available bias tees; and (3) aset of USF custom bias tees. In the biastee setups, the DiVA was connected tothe DC ports of the bias tees and theRF ports of the bias tees were termi-nated in 50 loads. The measurementsetup is shown in Figure 21. For thecommercially available bias tees, themeasurements were performed forpulse lengths varying from 1000 to 5 s.When attempting to measure at 2 s,the instrument reported that it couldnot complete the measurement due tothe large amount of gate current. Mea-surements were performed for the cus-tom USF bias tees from 1000 to 0.1 s.From simulation and initial transientmeasurement results, it was expectedthat the bias tee would function verywell for pulse lengths as low as 0.1 s.

TECHNICAL FEATURE

S11 S22 S33

MEASURED SIMULATED

s Fig. 17 Measured and simulated S11, S22 and S33 (F = 40 MHz to 5.0 GHz).

S 33(d

B)

0

10

20

30

40

500 1 2

FREQUENCY (GHz)

MEASUREDSIMULATED

3 4 5

S33

()

200

100

0

100

2000 1 2

FREQUENCY (GHz)3 4 5

s Fig. 20 Simulated and measured S33parameters.

x13

MEASURED SIMULATED

S 11 (

dB)

05

1015202530

0 1 2FREQUENCY (GHz)

3 4 5

S11

(

)

200

100

0

100

2000 1 2

FREQUENCY (GHz)3 4 5

s Fig. 18 Simulated and measured S11 parameters.

S 22 (

dB)

02468

1012

0 1 2FREQUENCY (GHz)

MEASUREDSIMULATED

3 4 5

S22

()

200

100

0

100

2000 1 2

FREQUENCY (GHz)3 4 5

s Fig. 19 Simulated and measured S22parameters.

In addition, it is desired to performpulsed IV measurements within thepulsed S-parameter system, so it is crit-ical that the IV characteristics be accu-rately measurable through the biastees. Figure 22 shows pulsed IVcurves taken with different pulselengths for the commercially availablebias tees and the custom USF designedbias tees. In each plot, the dashed setsof curves are the measurements with-

out bias tees. At 1000 s, there is ajog in the knee region characteristicof the curves without bias tees. Formeasurements made with the commer-cial bias tees, this jog is not measured;however, the USF bias tees correctlydepict this shift in the curves. Thephysical phenomenon behind this shiftmay be due to trapping effects. Thecommercial bias tees may lengthen theresetting time between pulses, so thiseffect is likely not due to the pulselength, but the pulse separation, asshown in Reference [3] for this device.If the pulse separation were length-ened, this result would likely to im-prove. However, even in this situation,it is interesting to note that the custombias tees more closely represent themeasurement environment where nobias tees are used.

The figure also shows that thecommercially available bias tees can-not allow accurate pulsed IV mea-surement for pulse lengths belowabout 20 s. Both bias tees allow ac-curate measurement of the 20 scurves. At 10 s, the IV curves mea-sured through the commercial biastees are too greatly sloped (gds is toolarge), while the custom bias tees al-low accurate measurement of thecurves. For a pulse length of 5 s, thecommercial bias tees are very clearlyin error. The 0.1 s pulse length mea-surement through the custom biastees is compared to a 0.1 s pulselength measurement without biastees in Figure 23.

In the custom bias tee measure-ments, the knee appears to occur at aslightly larger value of VDS than forthe measurements without bias tees.This is likely due to the fact that boththe inductor and the coaxial-to-mi-crostrip adapters, the FR4 substratemicrostrip transmission lines, the sol-

TECHNICAL FEATURE

(b) Pulse Length = 20 s

(c) Pulse Length = 10 s

(a) Pulse Length = 1000 s

(d) Pulse Length = 5 s

i D (

mA

)

vDS (V)

1000

800

600

400

200

00 2 4 6 8

i D (

mA

)

vDS (V)

1000

800

600

400

200

00 2 4 6 8

i D (

mA

)

vDS (V)

1000

800

600

400

200

00 2 4 6 8

i D (

mA

)

vDS (V)

1000

800

600

400

200

00 2 4 6 8

i D (

mA

)

vDS (V)

1000

800

600

400

200

00 2 4 6 8

i D (

mA

)

vDS (V)

1000

800

600

400

200

00 2 4 6 8

i D (

mA

)

vDS (V)

1000

800

600

400

200

00 2 4 6 8

i D (

mA

)

vDS (V)

1000

800

600

400

200

00 2 4 6 8

s Fig. 22 Pulsed IV curves measured with no bias tees, commercially available bias tees andcustom USF bias tees at different pulse lengths.

DiVA D225

Personal ComputerRunning

Windows withDiVA Software

CLY-5GaAs FET in

CoaxialFixture Surrounded

by Bias Tees

DataBus

s Fig. 21 Measurement set-up.

I ds (m

A)

Vds (V)

1000

800

600

400

200

00 1 2 3 4 5 6 7 8 9

-0.5v

-1.0v

-1.5v

-2.0v

-2.5v

Vgs = 0v

s Fig. 23 Pulsed IV measurements withpulse length = 0.1 s and without bias tee(dashed lines) or with custom USF bias tees(solid lines).

der joints and the inductors them-selves add resistance to the drain sideof the device, causing a lower voltageto be applied to the device than inthe case where no bias tees are used.This DC resistive effect can be easilycorrected using a Mathcad sheet ifthe resistance is measured. In addi-tion, the figure shows that the curvesmeasured through the bias tees areslightly higher than the curves mea-sured without bias tees.

PULSED S-PARAMETERSMEASUREMENT RESULTS

The pulsed bias tee has been usedsuccessfully in the design of a pulsed-RF, pulsed-bias S-parameter measure-ment system, as documented by a re-cent conference paper.4 Figure 24shows the S21 measurement results fora 5 W Si laterally diffused MOSFET(LDMOSFET) under both pulsed-and continuous-bias measurementconditions. The RF signal is pulsed in

TECHNICAL FEATURE

both situations; however, the bias sig-nal is pulsed in one case and is heldcontinuous in the other case. As docu-mented by Parker, et al., the differencein |S21| can be attributed to self-heatingin the device.5 This can be predictedfrom the IV curves of the device,which are shown in Figure 25. Thebias point A is the pulse-from bias,while the bias point B is the pulse-tobias, the bias at which the measure-ment is performed. For the gate-volt-age, drain-voltage combination givenby the bias point B, the differencebetween the current values is substan-tial. Notice also that the spacing be-tween the surrounding curves is vastlydifferent, which indicates a significantdifference in the small-signal value forgm at this bias point between thepulsed- and continuous-bias cases.This manifests itself in a lower gain forthe continuous-bias case, because thevalue of gm is lower. This is exactlywhat is observed in the previous figure.

CONCLUSIONA custom bias tee design has been

obtained with the assistance of accuratepassive component models to accom-modate pulsed-bias, pulsed-RF S-para-meters measurements with pulselengths on the order of 1 s and lower.The simulation results for the time andfrequency domains are found to com-pare remarkably well with the use ofthe models. An incremental design pro-cedure for this circuit has been demon-strated, followed by the results of mea-suring pulsed IV characteristicsthrough the bias tees. The pulsed IVresults for the custom bias tees are farmore accurate than those performedthrough commercially available biastees, which are not normally designedto allow pulses to pass through the biaspath. Finally, initial pulsed-bias, pulsed-RF S-parameter measurement resultsare shown and found to correlate withexpectations. The design of custom biastees for pulsed applications using accu-rate component models has providedfirst-pass success with the constructionof this pulsed measurement system. n

References1. C. Baylis and L. Dunleavy, Understanding

Pulsed IV Measurement Waveforms,2003 IEEE International Symposium onElectron Devices for Microwave and Opto-electronic Applications Digest, Orlando,FL.

2. C. Baylis, Improved Current-voltageMethods for RF Transistor Characteriza-tion, Masters Thesis, University of SouthFlorida, 2004.

3. C. Baylis, L. Dunleavy and A.D. Snider,The Normalized Difference Unit as aMetric for Comparing IV Curves, 64th Au-tomatic RF Techniques Group Conference,Orlando, FL, December 2004.

4. C. Baylis, L. Dunleavy and J. Martens,Constructing and Benchmarking aPulsed-RF, Pulsed-bias S-parameter Sys-tem, 66th Automatic RF TechniquesGroup Conference, Washington, DC, De-cember 2005.

5. A. Parker, J. Scott, J. Rathmell and M.Sayed, Determining Timing for Isother-mal Pulsed-bias S-parameter Measure-ments, 1996 IEEE MTT-S InternationalMicrowave Symposium Digest, Vol. III, pp. 17071710.

Charles Baylis receivedhis BS degree in electricalengineering and a minorin mathematics, summacum laude, from theUniversity of SouthFlorida in 2002 and hisMS degree in electricalengineering in 2004. He isnow pursuing his PhDdegree in the Center forWireless and MicrowaveInformation Systems at the

University of South Florida. He serves as an adjunctinstructor and a research assistant under the guidanceof Lawrence Dunleavy, where he is focusing on thedevelopment and applications of pulsed measurementand electrothermal transistor characterizationmethods.

Lawrence P. Dunleavyreceived his BSEE degreefrom the MichiganTechnological Institute in1982 and his MSEE andPhD degrees from theUniversity of Michigan in1984 and 1988,respectively. He hasworked in industry for E-Systems (19821983) andHughes Aircraft Co.(19841990), and was a

Howard Hughes doctoral fellow (19841988). In1990, he joined the electrical engineering departmentat the University of South Florida, where he is now aprofessor and co-founder of the Universitys Centerfor Wireless and Microwave Information Systems. In2001, he co-founded Modelithics Inc. to providepractical commercial modeling solutions andmicrowave measurement services for RF andmicrowave designers.

William Clausen receivedhis BSEE and MSEEdegrees from theUniversity of SouthFlorida in 2003. He hasbeen a member of thetechnical staff atModelithics Inc. since2002. His current interestsinclude microwavemeasurements, active andpassive componentmodeling, and amplifier

design.

S 21(d

B)

10

5

0

5

100 0.5 1.0 1.5

FREQUENCY (GHz)

PULSED VgsCONSTANT Vgs

2.0 2.5 3.0

S21

(

)

200

100

0

100

2000 0.5 1.0 1.5

FREQUENCY (GHz)2.0 2.5 3.0

s Fig. 24 S21 parameters of a SW SiLDMOSFET for pulsed Vgs (from 3.2 to 7 V)and Vds = 10 V constant and continuous bias(Vgs = 7 V, Vds = 10 V).

i D (

mA

)

vDS (V)

1400

1200

1000

800

600

400

200

00 2 4 6 8 10 12 14 16 18 20 22 24 26

A

B

Ggs=8V

7V

7V

6V

5V

4V

6V

Vgs=8V

s Fig. 25 Static and pulsed IV for the 5 WSi LDMOSFET; quiescent bias: Vgs = 3.5 V,Vbs = 0 V; pulsed bias: start A; end B.