Clemson UniversityTigerPrints

All Theses Theses

10-2008

DESIGN OF AN IC CONTROLLER FOR ALIGHT EMITTING DIODE STACKAndrew AllemanClemson University, aallema@clemson.edu

Follow this and additional works at: https://tigerprints.clemson.edu/all_theses

Part of the Electrical and Computer Engineering Commons

This Thesis is brought to you for free and open access by the Theses at TigerPrints. It has been accepted for inclusion in All Theses by an authorizedadministrator of TigerPrints. For more information, please contact kokeefe@clemson.edu.

Recommended CitationAlleman, Andrew, "DESIGN OF AN IC CONTROLLER FOR A LIGHT EMITTING DIODE STACK" (2008). All Theses. 476.https://tigerprints.clemson.edu/all_theses/476

DESIGN OF AN IC CONTROLLER FOR A LIGHT EMITTING DIODE STACK

A Thesis Presented to

the Graduate School of Clemson University

In Partial Fulfillment of the Requirements for the Degree

Master of Science Electrical Engineering

by Andrew Alleman December 2008

Accepted by: Dr. Kelvin Poole, Committee Chair

Dr. William Harrell Dr. Rajendra Singh

ii

ABSTRACT

An integrated circuit (IC) powering up to nine series connected high brightness

light emitting diodes (HBLED’s) was designed. The LED’s are split into three groups by

color (RGB), and the average current through each group is independently varied using a

separate microprocessor in conjunction with the IC controller. Integrated comparators

compare the voltage across each LED group with internally generated references to check

for open or short circuit diodes. In the event of an open circuit failure, the IC controller

switches in a SCR to bypass the open circuit device thus maintaining light output at

reduced intensity.

Silvaco CAD tools and SPICE simulations were used to design the LDD high

voltage MOSFET’s. A MOSFET width of 15,000µm was sufficient to meet the

specification. Simulations showed a VDSON of 100mV at 0.5A is possible.

Mentor Graphics CAD tools in conjunction with a standard TSMC 0.35µm

process was used to design the op-amp and comparators used in the fault detection circuit

and the PMOS current mirror used in the MOSFET gate control circuit. The gate control

circuit was found to have an average delay of 4µs.

By varying the intensity of the three primary colored LED’s, a spectrum of colors,

including white light, can be produced. Independent control of the average current

through each LED group is accomplished by connecting a MOSFET in parallel with each

group. The MOSFET provides an alternate current path and, by applying a Pulse Width

Modulated (PWM) signal to the gate of the MOSFET, the average current through each

iii

LED group can be varied from 25mA (lowest duty cycle) to 475mA (highest duty cycle).

The 3.3v digital signals supplied by the microprocessor are used to switch each MOSFET

transistor ON or OFF using three separate level shift circuits on the IC controller.

A hardware version of the intensity control circuit was constructed out of discrete

components to demonstrate PWM LED intensity control functionality. The duty cycle of

the hardware circuit’s LED current was measured to have an average percent error of 2%

and a maximum percent error of 12%.

iv

DEDICATION

I dedicate this thesis to my parents, Chuck and Debbie Alleman, who helped me

to realize the most important thing in life is faith in Jesus Christ; and to my sister, Missy

Dawson, and my brother, Michael Alleman.

v

ACKNOWLEDGMENTS

Many thanks to my advisor Dr. Poole for all his help throughout my thesis from

start to finish. Thanks also to Travis Summerlin for his help and support with Texas

Instruments. I would like to give credit to Roman Korsunsky for the concept of the PWM

LED operation and his project ideas from Texas Instruments.

vi

TABLE OF CONTENTS

Page

TITLE PAGE....................................................................................................................i ABSTRACT.....................................................................................................................ii DEDICATION................................................................................................................iv ACKNOWLEDGMENTS ...............................................................................................v LIST OF TABLES........................................................................................................viii LIST OF FIGURES ........................................................................................................ix CHAPTER I. INTRODUCTION .........................................................................................1 Application...............................................................................................1 Purpose.....................................................................................................2 II. SYSTEM CONSIDERATIONS ....................................................................6 Introduction..............................................................................................6 Specifications...........................................................................................6 Pulse Width Modulation Color Intensity Control....................................7 MOSFET Gate Control ............................................................................9 LED Fault Detection ..............................................................................10 Open Circuit Bypass ..............................................................................12 III. DEVICE DESIGN AND VERIFICATION.................................................14 Introduction............................................................................................14 MOSFET Design ...................................................................................14 IV. CIRCUIT DESIGN AND VERIFICATION ...............................................23 MOSFET Floating Gate Controller .......................................................23 LED Fault Detection ..............................................................................29 Open Circuit Bypass Design..................................................................33

vii

Table of Contents (Continued) Page

V. PHYSICAL DESIGN AND VERIFICATION............................................34 Introduction............................................................................................34 Hardware Intensity Control Circuit Results. .........................................42 VI. PERFORMANCE RESULTS AND CONCLUSION .................................48 Results....................................................................................................48 Conclusion .............................................................................................51 APPENDICES ...............................................................................................................53 A: LDDMOSFET Details .................................................................................54 B: Voltage Mode PWM BUCK Constant Current Supply ...............................55 C: Op Amp and Comparator Design ................................................................57 D: MOSFET VDSON Issues ............................................................................66 E: IC Controller Layout....................................................................................69 REFERENCES ..............................................................................................................74

viii

LIST OF TABLES

Table Page 1 Time Domain Simulation Results for MOSFET Gate Control Circuit........25 2 FD Threshold Levels Based On LED Selector Inputs A and B...................31 3 Parts List for Hardware Circuit....................................................................41 4 Green LED Input Test Conditions and Expected Output ............................46 5 Measured Results From Group 2 .................................................................46 6 Floating Gate Controller Post-Layout Nominal Results..............................49 7 Fault Detection Circuit Post-Layout Nominal Results ................................49 8 Floating Gate Controller Circuit Post-Layout Parametric Results ..............51 9 Fault Detect Circuit Post-Layout Parametric Results ..................................51 10 40Volt NMOS LDD MOSFET Parameters .................................................54 11 60Volt NMOS LDD MOSFET Parameters .................................................54 12 24Volt PMOS LDD MOSFET Parameters..................................................54 13 Fault Detection Op Amp Performance ........................................................61 14 Fault Detection Comparator Performance ...................................................64

ix

LIST OF FIGURES Figure Page 1 LED Controller Block Diagram.....................................................................2

2 PWM Intensity Simulation Showing Different Duty Cycles in Groups 1, 2, and 3 ....................................................................................8

3 Fault Detection Block Diagram ...................................................................12 4 Open Circuit Bypass Block Diagram...........................................................13 5 Breakdown Scenario for MOSFET T2 ........................................................17 6 Basic Punch-Through Breakdown Model....................................................17 7 0.30µm MOSFET with Punch-Through Breakdown...................................19 8 0.60µm MOSFET with no Breakdown........................................................20

9 Simulation Showing IDS Currents Under High VDS Voltages for L=0.35µm and L=0.60µm......................................................................21

10 VDSON Variation Verses NMOS Width, T=100C ........................................22 11 MOSFET Floating Gate Controller Circuit Schematic................................24

12 Simulation Showing the Floating Gate Controller Output Across R1 (T=27C, R1=30k) ................................................................26

13 Worst Case Simulation: Showing the Floating Gate Controller

Output Across R1 (T=100C, R1=24k) .................................................27

14 Simulation Showing the Maximum Operating Bias for the Gate Controller Circuit ...................................................................................28

15 Simulation Showing the Current Mirror Output Current Verses

Bias Voltage...........................................................................................29 16 Fault Detection Circuit Schematic ...............................................................30

17 Simulation of the Fault Detection Circuit Showing All Possible Operational Conditions ..........................................................................32

x

List of Figures (Continued) Figure

Page 18 Hardware Light Intensity Control Circuit Schematic ..................................35 19 Complete Hardware LED Intensity Control Setup Photo............................36 20 Hardware Light Intensity Control PCB .......................................................37 21 Hardware Current Mirror Circuit Schematic ...............................................39 22 Simulation of the Hardware's Current Mirror Circuit..................................40

23 Complete Hardware Switch Mode Power Supply Circuit Using the TPS40200.........................................................................................40

24 Scope Graph of 5% PWM ...........................................................................43 25 Scope Graph of 50% PWM .........................................................................43 26 Scope Graph of 95% PWM .........................................................................44 27 Multi Duty Cycle Graph, Red=95%, Green=50%, Blue=5%......................45 28 Voltage Mode Buck Converter and Type3 Compensation Loop.................55 29 Op Amp for Fault Detection Circuit ............................................................59 30 Closed Loop Op Amp Circuit ......................................................................60 31 Op Amp Open Loop Frequency Response at ID = 50µA............................61 32 Closed Loop Simulation of Differential Voltage (VCM=0) .........................62 33 Comparator for the Fault Detection Circuit .................................................63 34 Comparator Differential Input Simulation Showing Min VIN .....................65

35 Comparator Simulation Showing the Input Common Mode Range, VIN = -10mV .............................................................................65

36 Layout Plot of the IC Controller Design......................................................69

xi

List of Figures (Continued) Figure

Page 37 Layout Plot of the Floating Gate Controller Block......................................70 38 Layout Plot of the Fault Detection Block ....................................................71 39 Layout Plot of the Sense Op-Amp for the Fault Detection

Block ......................................................................................................72 40 Layout Plot of the Comparator for the Fault Detection Block.....................73

1

CHAPTER ONE

INTRODUCTION

Application

The motivation for this work came from industry’s requirement for higher

efficiency lighting. Due to new energy laws, most incandescent lighting will not meet the

new high efficiency standard. The new efficiency standard [1], passed by congress in

2007, requires an approximate 20% energy reduction by 2012 and a 65% reduction by

2020. LED lighting, while efficient, is more expensive than virtually all other lighting.

Incandescent light bulbs, which have been the cheapest until now, will not meet this

standard. Currently, compact fluorescent lighting is the cheapest alternative; but LED

lighting while expensive, has a greater capacity for efficiency. While the controller is

intended to meet this new efficiency specification, the primary focus is on designing a

circuit that controls the light intensity of LED’s separated into three separate groups by

color. While white LED’s could be used for general purpose lighting, even more

functionality and versatility as a light source can be achieved by utilizing separate red,

green, and blue LED’s. This allows for applications where the color needs to be varied

from any single primary color, to any mix of the three, including white light. The IC

controller is intended to provide all the controls needed for a multi-color light source for

applications such as wall washing and colored architectural lighting.

2

Purpose

The block diagram below shows the IC controller’s internal and external circuit

function blocks. The LED current produces a voltage across the sense resistor, which is

used by the buck power supply as a feedback signal to regulate the current. The closed

loop control ensures a constant current drive through the parallel combination of LED’s

and MOSFET’s. In this circuit, there is no in-between mode of operation; the pulsed

current will go either entirely through the LED group, or through the MOSFET transistor.

LED fault detection is performed internally by checking the voltages across each LED

group. Lastly, the external OC bypass circuit provides an alternate current path for each

LED in the case of an open circuit fault.

Figure 1. LED Controller Block Diagram

IC Controller Chip

3

In this circuit, PWM (Pulse Width Modulation) control refers to diverting current

from the LED group through the MOSFET transistors. The purpose of the IC design is to

create a controller that controls the intensity of the colored LED’s connected in series.

The three NMOS transistors, one for each color group, can be turned ON to divert all of

the current away from their parallel LED group, effectively short circuiting a LED group.

There are two popular approaches to varying the LED current. One is to change the

steady state DC current through the LED’s. For example, a reduction in current of 50%

corresponds to an LED intensity that is also 50%. The second method is to use pulsed DC

current at different rates to develop an average DC current through the LED’s [2, 3]. This

is the method used for this thesis and is referred to as PWM. The current through the

LED’s alternates from the maximum current to zero current. The average LED DC

current is directly controlled by the PWM duty cycle. A high duty cycle corresponds to a

higher average current because the current is at its peak value for a longer period of time

relative to the time at which it is zero. This approach to dimming LED’s enables very

high dimming ratios. The dimming ratio is the ratio of the maximum brightness divided

by the minimum brightness. So if the minimum duty cycle is 5%, then the dimming ratio

would be 20:1. The PWM current control is the easier of the two to be integrated on a

chip, as the MOSFET’s can have very low resistance values which corresponds to low

power dissipation, and conversely, higher efficiency. In addition, PWM intensity control

gives two improvements over DC current. One is that the PWM duty cycle corresponds

on a 1:1 scale with LED intensity, and the other is that the LED’s will produce a truer

color [2]. Color variations arise in InGaN LED’s (blue, green, and white) when they are

4

not operated at their intended current. When the LED’s are OFF, zero current flows, and

when ON the peak PWM current flows. The peak PWM current is then set to the

intended LED current for optimal LED light output. Of course there are always the rise

and fall times (approximately 130µs max) where the current will invariably lie

somewhere between zero and the peak, but this time is negligible. The drawbacks to

using bypass MOSFET’s is that while they are in parallel with their corresponding color

groups, they are also in series with each other. This means that the NMOS transistors are

always floating and have no constant reference level from which to drive the gate. A level

shift circuit or high side gate drive circuitry is therefore needed to control the

MOSFET’s.

For the PWM dimming approach, a constant current source is needed to ensure

current flows either through the LED group or through the NMOS bypass transistor

connected in parallel. The voltage across each color group will vary greatly depending on

whether the MOSFET is turned ON or OFF. A current source automatically adjusts the

output voltage to drive the current through the circuit at a constant value. Constant

current supply is accomplished through a voltage mode PWM buck converter. The buck

power supply works by driving its output so that the feedback input equals 700mV. A 1.4

ohm current sense resistor is used to provide a .5A regulated current.

The LED fault block checks the LED’s for a fault in any of the three LED groups.

The fault detection will detect both open and short circuit conditions, but will not

differentiate between the two fault modes. Since the LED’s are in series, any open circuit

failure will stop the operation of the entire circuit. Therefore, the external OC bypass

5

circuit is used to provide an alternate current path for any LED, which undergoes an OC

failure. This will enable the rest of the circuit to continue to operate, but with a reduction

in light output.

The thesis is organized topically starting with an overview of the LED controller

system followed by design and simulation of the different circuit blocks, and ending with

the performance of the proposed solution and conclusions. Chapter 2 covers the system

overview of the circuit blocks and the operation. Chapter 3 provides details of the design

and simulation of the bypass transistor devices. Chapter 4 deals with the circuit design

and simulation. Chapter 5 covers the design and performance of the constructed hardware

circuit. Lastly, the performance of the IC controller’s layout is covered in chapter 6.

6

CHAPTER TWO

SYSTEM CONSIDERATIONS

Introduction

The circuit specifications given below are met through the different circuit blocks

discussed in this chapter. The specific details of the block’s operation will be discussed,

but the simulation results will be presented in chapters four and six. The first block that

will be discussed is the light intensity control block, followed by the fault detection

block.

Specifications

The core design specifications are given below: System Specifications:

• LED current = 0.5A • Current Stability: +/- 10% • Max IC controller power dissipation = 300mW

Device Specifications:

• VF for Green and Blue = 3.4V • VF for Red = 2.4V • Bypass Transistor Forward Current = 0.5A (ON Condition) • VDSON = 150 mV Max • MOSFET Transistor Channel Width < 100mm • MOSFET Transistor Power Dissipation = <75mW (ON Condition) • MOSFET Transistor VGS ≤ 15V

Circuit Specifications:

• MOSFET gate control for up to 9 LED’s. • Min LED Switching Frequency = 120Hz • Min LED PWM intensity control range from 5% to 95%.

7

• The controller will detect LED failures and indicate the failure with a digital output signal.

• The external controller circuit will bypass any open circuit LED to maintain operation.

Pulse Width Modulation Color Intensity Control

At the heart of the intensity control circuit is the use of a variable pulse with

modulated wave. With any PWM wave, there are three main parameters. They are the

period, pulse width, and duty cycle. The period is the time it takes to complete one cycle

of the wave. The duty cycle is percentage of the pulse width to the period. 100% duty

cycle means the PWM wave is ON all the time, while a 50% duty cycle means the PWM

wave has equal high and low times.

PWM light control is accomplished by changing the time that the LED’s are

turned ON. For example, Figure 2 shows a simulation of the voltage across LED groups

1, 2, and 3 at 95%, 50%, and 5% duty cycles respectively. These intensities would

correspond to respective average currents of 475mA, 250mA, and 25mA. If the

frequency of the PWM pulses is greater than the spec (120Hz), then the LED’s will not

appear to flicker. Using a separate MOSFET transistor for each color allows for the

simultaneous and independent dimming of all three colors. Under microprocessor control

the light output from red, green, and blue LED’s can be mixed to produce any color as

well as any shade of white light.

8

Thesis_PWM-Transient-9-Graph Time (s)

0.0 1.0000m 2.0000m 3.0000m 4.0000m 5.0000m 6.0000m

-1.000 Group 1 -1.000 Group 2 -1.000 Group 3 -1.000 D(TIME) -1.000 D(Group 3) -1.000

Figure 2. PWM Intensity Simulation Showing Different Duty Cycles in Groups 1, 2, and 3

An alternative to using large and costly integrated MOSFET transistors, is to use a

separate PWM current driver for each color. This method would either cycle the VDD or

use some other method to turn the chip ON and off. The primary appeal for this method is

elimination of the need for integrated MOSFET gate control circuitry. The maximum

number of LED’s is set by the maximum output drive of the PWM converter and is not

limited by the integrated transistor breakdown voltage. More practically, a single external

MOSFET could be used to provide the intensity control. This approach has the

disadvantage that a minimum of three different buck converter circuits is required. For

larger applications of 20 LED’s or more, this would be the ideal approach. This thesis

will focus on designing a IC controller for a small lighting application of 9 LED’s or less.

LED Group 1: 95% Duty Cycle

LED Group 2: 50% Duty Cycle

LED Group 3: 5% Duty Cycle

GREEN: 250mA Average

RED: 475mA Average

BLUE: 25mA Average

f = 333Hz

Group1

Group2

Group3

9

MOSFET Gate Control

The MOSFET gate control is the primary circuit block used for LED intensity

control. The integrated MOSFET transistors are floating, the bottom transistor is the

closest to the ground potential, but the other two transistors float several volts above

ground. The MOSFET transistors are controlled by standard 3.3V digital signals via a

floating gate driver circuit. The floating gate driver used is a current mirror that drives a

current through a resistor wired between the gate and source. This current then produces

a VGS voltage that floats on the source of the transistor. The RDSON of an NMOS switch

controls the current, while the gate of the NMOS is used as the control to switch the

current ON or OFF in the current mirror. The advantage of this current mirror design is

simplicity and solid control of the bypass gate in both ON and OFF modes. When ON,

the current through the resistor produces a VGS, and when OFF, the resistor effectively

shorts the bypass gate and source together. This eliminates any circumstances in which

the VGS could exceed the maximum rating.

Alternatives to control the integrated MOSFET’s were also considered. One idea

was to use a charge pumping scheme. One major drawback in the charge pump approach

is the lack of equivalent voltage ratings for the PMOS transistors. The Drain Extended

PMOS transistors can go to 24V VDS, while their NMOS counterparts can go up to 60V.

Timing issues were also a drawback, as the charge pump circuit could impose limits on

the dimming ratios. Still, a properly designed charge pump circuit could raise the

maximum forward voltage that the chip is able to control, and the maximum number of

LED’s in the circuit. Another possible solution was to use a non-inverting summing op

10

amp with one summing input as the source of the bypass transistor and the other

summing input as the digital control signal. This circuit did not perform as well as the

current mirror and was more complex.

LED Fault Detection

The goal of the LED Fault Detection (FD) block is to scan each LED

group for a lower voltage drop than what is expected. It does this because, in either fault

mode (short or open) the voltage drop across the faulty LED will be much lower than

normal. A short circuit LED will have practically zero voltage drop, while an open circuit

LED, that has been bypassed, will have the reduced forward voltage of the SCR. The FD

circuit was designed so that the fault detection circuit outputs will indicate a fault in the

event of a LED fault or while the LED group is turned OFF. The circuit will only provide

one digital output signal per group, so the same signal can potentially indicate up to three

LED faults per group. Also, the FD circuit will not indicate which particular LED is

faulty, only the LED group that contains the faulty LED. Practically, it is much easier to

program the microcontroller to check for fault detection signals when the LED’s are ON

and ignore the fault signals when the LED’s are OFF. For proper fault detection then, the

microcontroller would turn the LED’s ON and wait a programmed amount of settling

time before checking for LED faults.

Since the IC controller drives between one and three LED’s, the FD block will

need to determine how many LED’s are in each group. To reduce the pin count, the

circuit will not have inputs for each LED, but only inputs for each group. Since the

LED’s cannot be checked individually, the SC block must be able to detect 4 possible

11

outcomes for each group, namely 0, 1, 2, or 3 LED’s. Therefore in order to set the correct

threshold level, two external pins were added to tell the fault detection circuit how many

LED’s are present. Since the LED levels are well above the digital CMOS levels, a

resistor divider ratio of fifteen was used to shift the LED voltages to CMOS levels.

Figure 3 below shows the methodology for checking the LED’s against short and

open failure modes. This circuit uses an op amp to read the differential voltage across

each LED group. The circuit measures the differential voltage by subtracting the bottom

LED group node voltage from the top LED group node. Furthermore, since the LED’s

forward voltage is predictable; then the circuit only has to consider multiples of the LED

forward voltage. The proper threshold level is determined by the digital LED selector

inputs. The proper input for one LED is (A=0, B=0), for two LED’s is (A=1, B=0), and

for three LED’s is (A=0, B=1). Lastly, the differential voltage is compared against the

selected threshold level.

12

Figure 3. Fault Detection Block Diagram

Open Circuit Bypass

The OC bypass circuit is an external circuit block to provide an alternate current

path for each LED that has an OC fault. This is necessary to keep the current flowing

after a LED has an OC fault. Figure 4 below shows the simple block diagram for the LED

bypass circuit. The circuit uses a parallel SCR to bypass the OC LED when the voltage

rises above the normal LED level.

13

Figure 4. Open Circuit Bypass Block Diagram

Another option is redundancy. Instead of an SCR, a second LED would perform a

similar function. This would give twice the light output while providing a backup for

every LED. This simple alternative would produce more light without having to resort to

a higher voltage power supply. The power supply would also have to provide more

current for the new parallel LED branch. For applications in which more than 9 LED’s

are needed, this is an attractive approach, but this thesis will focus on small applications

of 9 LED’s or less.

14

CHAPTER 3

DEVICE DESIGN AND VERIFICATION

Introduction

A standard CMOS TSMC 0.35µm process was available at Clemson University.

It soon became apparent that the application required a process supporting high voltage

LDD MOSFET’s. Nonetheless, the design procedure is unaffected by this fact, and the

design was continued using the standard TSMC process. The VGS and VDS voltages of the

MOSFET’s were monitored throughout the design to ensure functionality if

manufactured in a high voltage LDD process. Silvaco CAD tools were used to simulate

the physical properties along with SPICE simulations to verify that the MOSFET’s

functioned as designed, and all parameters such as gate, source, and drain voltages

remained within expected tolerances.

MOSFET Design

This chapter details the design of the MOSFET used for the intensity control

circuit. The quality of LED light produced is directly proportional to the quality and

stability of the intensity control MOSFET. The MOSFET controller circuit is essentially

a floating gate controller that takes a digital signal and shifts the DC level to control the

bypass transistor.

The intensity control MOSFET is a simple but important element in the intensity

control circuit. Functionally, it shorts the LED group that it is in parallel with.

15

Furthermore, it must have a much smaller VDSON, compared to the LED’s forward voltage

drop, so as to carry all the current when turned on. At 0.5 amps, this requires a large

integrated NMOS transistor. The primary goal in designing the MOSFET is to balance

the power dissipation and area consumption. The power consumption is the voltage drop

across the transistor multiplied by the current. In this case, the current is fixed at .5A, so a

minimum VDSON is directly proportional to minimum power dissipation.

These transistors are Lightly Doped Drain (LDD) MOSFET’s, which have a

longer drain to allow for higher VDS and VDSUB breakdowns. Since no high voltage

MOSFET’s were available in the standard TSMC process, a digital TSMC NMOS

transistor was used as if it were a LDDMOSFET. The LDDMOSFET details are covered

in Appendix A. As the IC power specification is 300mW, the transistors were sized so

that they consumed approximately 50mW each.

A reliability issue considered in the design was the breakdown of the substrate-

drain junction for the TSMC 0.35µm MOSFET transistors. The goal of the LED

controller is to control each intensity control transistor independently of the other two.

Punch-through breakdown occurred in the MOSFET transistors with a minimum gate

length parameter of 0.35µm. This ‘punch-through’ breakdown causes the transistor to

conduct some of the current even with no gate to source voltage applied. Punch-through

breakdown is a result of very large values of VDS on a short channel device less than

1µm. Large VDS values cannot be avoided for this project because each transistor is in

parallel with up to 3 LED’s. The maximum voltage drop across the LED’s is 7.2V for

16

three red LED’s and 10.2V for three green or blue LED’s. Therefore, the MOSFET and

floating gate controller circuit must be designed to handle large VDS voltages.

Another complication in using the standard TSMC 0.35µm process is the large

N+ diffusion sheet and contact resistance. The design presented here will meet the

specifications, provided the process model parameters fall within those specified. Details

are provided in Appendix D.

The effects of transistor breakdown were first noticed in T2 as shown in Figure 5.

When T1 was turned ON and T2 was turned OFF (VGS = 0), T2 continued to pass current

when VDS rose above 9.5V. Similarly, if T1 and T2 were turned ON, it was found that T3

would conduct current when turned OFF if its VDS also rose above 9.5V. Figure 6 below

shows a basic physical model for the punch-through breakdown in the MOSFET

transistors. If the bulk, source, and gate were held at or close to ground, then increasing

VDS above 9.5V, for a .35µm standard TSMC MOSFET, causes the drain depletion

region to contact the source depletion region.

17

Figure 5. Breakdown Scenario for MOSFET T2

Figure 6. Basic Punch-Through Breakdown Model

For a short channel MOSFET (0.35µm), VDS can only be raised so high before the

depletion regions touch. Silvaco was used to simulate the MOSFET current while the

T1 (MOSFET ON)

T2 (MOSFET OFF)

GND

T3 (MOSFET OFF) Blue LED x 3 (10.2V)

Green LED x 3 (10.2V)

Red LED x 3 (100mV)

Substrate

Source Drain

Gate VDS (9.5V)

GND

Large Punch-Through Current

Bottom Transistor T3

GND (0V)

Expanded Depletion region due to Large VDS

18

source, gate, and substrate were held fixed at ground and the drain was at 30V. The

voltage was raised to 30V to show the device more clearly in punch-through breakdown.

Figure 7 below shows the Silvaco simulation on a 0.30µm N-channel MOSFET. The

simulation shows a large current path under the channel. Figure 8 shows the same

simulation on a 0.60µm N-channel MOSFET. The second simulation, on the .60µm

channel, shows practically zero IDS current.

19

Figure 7. 0.30µm MOSFET with Punch-Through Breakdown

Punch-Through Breakdown

20

Figure 8. 0.60µm MOSFET with no Breakdown

To eliminate the punch-through breakdown, the channel length was increased to

0.60µm for each intensity control MOSFET. The following graphs show the process used

to select a new length to account for the punch-through condition. Figure 9 shows the

major difference between a length of 0.35µm and 0.60µm. At a VDS of ten volts, the

Channel OFF

21

current through the 0.60µm device is only 300nA or about 4% of the 0.35µm device.

There are two other concerns as well as the IDS breakdown current. One is the VDS across

the transistor when on; the other is temperature’s effect on both the breakdown IDS, and

VDSON. At 0.60µm, and a temperature of 100oC, the current is only in the hundreds of

micro amps. This is a good transistor length because it is small enough not to cause a

large increase in channel resistance; but also large enough to practically eliminate the

current in punch-through breakdown. Figure 10 shows VDSON as a function of width. A

width of 15,000µm was chosen as a balance between minimum area and minimum power

dissipation. The true power dissipation depends on the average current through the

MOSFET.

IDS Break Down Current for L=.2um and L=.4um V2

8.0000 8.5000 9.0000 9.5000 10.0000 10.5000 11.0000 11.5000 12.0000

(Amp)

0.0

5.000u

10.000u

15.000u

20.000u

25.000u

30.000u

35.000u

V2 -1.000 IDS - L=.2um -1.000 IDS - L=.4um -1.000 D(V2) -1.000 D(i(v2)) -1.000

Figure 9. Simulation Showing IDS Currents Under High VDS Voltages for L=0.35µm and L=0.60µm

Current (Amps)

L=.35um Current=7.5µA

VDS (Volts)

L=.60um Current=300nA

35.00u

30.00u

20.00u

10.00u

0.0

25.00u

15.00u

5.00u

8.00 9.00 10.00 11.00 12.00 8.50 9.50 10.50 11.50

22

VDS Verses NMOS Width at T=100C M1.w

7.0000m 8.0000m 9.0000m 10.0000m 11.0000m 12.0000m 13.0000m 14.0000m 15.0000m 16.0000m

(V)

60.000m

80.000m

100.000m

120.000m

140.000m

160.000m

180.000m

200.000m

220.000m

240.000m

260.000m

M1.w -1.000 VDS at VGS=7V -1.000 VDS at VGS=3V -1.000 D(M1.w) -1.000

D(VDS at VGS=3V) -1.000

Figure 10. VDSON Variation Verses NMOS Width, T=100C

Device Width (mm)

VDSON (mV)

Worst Case: T=100C, Minimum VGS

Normal: T=25C, Optimum VGS

L=.60um 260.00m

220.00m

240.00m

200.00m

180.00m

160.00m

140.00m

120.00m

100.00m

80.00m

60.00m

10.00m 11.00m 12.00m 13.00m 14.00m 15.00m 16.00m 9.00m 8.00m 7.00m

23

CHAPTER 4

CIRCUIT DESIGN AND VERIFICATION

In chapter 3, the intensity control MOSFET was sized for a balance between

minimum power dissipation and minimum area. Chapter 4 details the design and

simulation of each of the internal circuit blocks. Each of the circuit blocks were simulated

in B2Spice. In chapter 6, the circuit blocks were simulated at the post-layout stage using

Mentor Graphic’s Eldo simulator.

MOSFET Floating Gate Controller

The main design challenge for this thesis was the MOSFET gate controller circuit.

The MOSFET gate controller circuit provides the VGS for the MOSFET irrespective of

the source potential. The focus for this block was to provide a VGS gate drive that worked

independent of the other gate controller circuits while insuring the VGS never exceeded

the limits. The method chosen that met all requirements, was a resistor placed between

the gate and source. This method is effectively a floating voltage source controlled only

by the current through the resistor.

24

3.3

INPUT

M4

M3

30K

R1

m2

24

V2

VGS

M5

M1

0

BIAS

IREF

IOUT

Figure 11. MOSFET Floating Gate Controller Circuit Schematic

Figure 11 shows the current mirror used to control the current through a resistor

between the MOSFET’s source and gate. This design is simple, but solid, since when no

current is flowing, VGS will be zero. On the other hand, forcing a current through the

resistor will give a VGS that floats on the source node. To produce this current, a 24V

PMOS current mirror was used. 24V was chosen because it was the maximum allowable

VDS for the PMOS transistors. For this design, the PMOS transistors in the current mirror

are the limiting factor for the maximum voltage that the mirror can float to and still keep

the current at the correct level. Their max VDS is limited to 24V, so 24V minus -2 VDSON

is the maximum drive voltage. A NMOS transistor was used both to set the current and to

turn the current through the resistor ON and OFF. The gate of the NMOS was used to

switch the current ON and OFF, while the NMOS width and length were adjusted to set

25

the correct current through the current mirror. This type of floating gate drive circuit has

the advantage that it can switch much faster than the specified 120Hz, as well as remain

on indefinitely, as no capacitors are involved. Simulations show that the optimum gate

drive voltage for the TSMC035 model is seven volts. This can be achieved with this

circuit by selecting the proper resistor size and current.

The following results show the simulation and performance of the MOSFET gate

driver. Figure 12 shows the VGS of the MOSFET in response to the LED intensity control

PWM signal. Table 1 shows the delay times for the gate controller circuit while driving a

bypass transistor. The resulting delay time is due to the fact that the gate controller circuit

is driving a very large gate capacitance. If CGS equals approximately 2fF/µm, then a

width of 15,000µm gives a CGS of 30pF. While 4µs switching times allow for high

frequency PWM intensity control, applications switching at 120Hz would actually benefit

from slower switching times by increasing the power supply stability. These transient

times represent approximately 1% of the smallest duty cycle (5% of 120Hz), which

provides a large safety margin.

Table 1. Time Domain Simulation Results for MOSFET Gate Control Circuit

TPLH 1.114µs

TPHL 1.000µs

TRISE 3.223µs

TFALL 3.680µs

26

Current Mirror VGS Drive Time (s)

0.0 10.0000u 20.0000u 30.0000u 40.0000u 50.0000u 60.0000u

(Amp)

0.0

1.000

2.000

3.000

4.000

5.000

6.000

7.000

TIME -1.000 VIN -1.000 VGS -1.000 D(TIME) -1.000 D(i(vam2)) -1.000

Figure 12. Simulation Showing the Floating Gate Controller Output Across R1 (T=27C, R1=30k)

One can see that the worst case conditions have a significant effect on VGS from

Figure 13. This simulation was taken with the VGS Resistor R1 at -20% or 24k, and the

temperature at 100oC. A VGS of 4V is still more than enough to turn the MOSFET

transistor on, but the net outcome will be a higher VDSON, which will in turn cause the

MOSFET to dissipate more power. Figure 14 shows the simulation of VDSON and VGS of

the bypass transistor versus a bias voltage ramp from 5V to 24V. One can see the bias

limit is about 20V for the current mirror output (IOUT). The largest bias the current

mirror has to drive in the design is the source of the group 3 bypass transistor. The largest

PWM Signal

MOSFET VGS (7.75V)

TRISE = 3.2us

TFALL = 3.7us

Volts Volts

7.00

6.00

5.00

4.00

3.00

2.00

1.00

0.0

0.0

Time (s)

10.00u 20.00u 30.00u 40.00u 50.00u 60.00u

27

bias on the source will be when the LED’s in groups one and two are on, which is

approximately 17.4V for the OSRAM LED’s.

Current Mirror Worst Case VGS Drive Time (s)

0.0 10.0000u 20.0000u 30.0000u 40.0000u 50.0000u 60.0000u

(Amp)

0.0

500.000m

1.000

1.500

2.000

2.500

3.000

3.500

4.000

TIME -1.000 VIN -1.000 VGS -1.000 D(TIME) -1.000 D(i(vam2)) -1.000

Figure 13. Worst Case Simulation: Showing the Floating Gate Controller Output Across R1 (T=100C, R1=24k)

MOSFET VGS (4.75V)

Volts Volts

4.00

0.0

Time (s)

10.00u 20.00u 30.00u 40.00u 50.00u 60.00u

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.0

28

Thesis_Current Mirror_Example-DC Transfer-12-Graph V_BIAS

10.0000 12.0000 14.0000 16.0000 18.0000 20.0000 22.0000 24.0000

0.0

1.000

2.000

3.000

4.000

5.000

6.000

7.000

V_BIAS -1.000 VGS -1.000 VDSON -1.000 D(V_BIAS) -1.085 D(VDSON) -1.000

Figure 14. Simulation Showing the Maximum Operating Bias for the Gate Controller Circuit

Figure 15 shows the current IOUT versus the bias voltage. The current stays

relatively constant until 15V. This is expected since the bias is given by:

GateDriveVONVDDBIASMAX −−= 2

Therefore, a VDD of 24V, a gate drive of 7.5V, and a VON of 1.2V gives a predicted

maximum bias of 14V. The maximum operating point is actually higher however,

because VON for this circuit is a function of BIAS voltage. Therefore, since the VGS

voltage needed for operation is less than 7.5V, the circuit will operate up to 21.4V as

shown in Figure 14. Practically, the maximum bias could be increased by lowering the

gate drive, but this would also have the undesirable affect of decreasing the gate drive

safe operation region needed to insure reliable gate operation with process and supply

variations.

MOSFTET VGS

MOSFET VDSON

MAX BIAS for MOSFET Operation at 21.4V

BIAS Voltage Volts

7.00

6.00

5.00

4.00

3.00

2.00

1.00

0.0

10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00

29

Thesis_Current Mirror_Example-DC Transfer-13-Graph V_BIAS

10.0000 12.0000 14.0000 16.0000 18.0000 20.0000 22.0000 24.0000

(Amp)

0.0

50.000u

100.000u

150.000u

200.000u

250.000u

V_BIAS -1.000 IOUT -1.000 D(V_BIAS) -1.000 D(IOUT) -1.000

Figure 15. Simulation Showing the Current Mirror Output Current Verses Bias Voltage

LED Fault Detection

The intent of the LED Fault detection block is to check each LED group for a

short or open, and then report to the microcontroller which group had the fault. The

circuit functions by sensing the differential voltage across an LED group and comparing

that against the expected voltage level corresponding to the number of LED’s per group.

The LED selector pins are inputs used to tell how many LED’s per group are physically

present in the circuit. This circuit will allow the microcontroller to check for a fault after

the LED’s have reached a steady state ON condition.

Figure 16 below shows the Fault detection circuit schematic. This circuit is the

simplest solution to meet the specification for SC and OC fault detection. Comparing the

IOUT

BIAS Voltage

10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00

Amps

250.00u

200.00u

150.00u

100.00u

50.00u

0.0

30

differential voltage across each group is preferable to checking the nodal voltages ( for

example, from the top Red LED to ground), because the nodal voltages depend on the

state of the LED’s in series below. Because the maximum voltage at the top of the LED

series can be approximately 30V, a divide by 15 voltage divider was used to level shift

the voltages to 3.3V CMOS levels.

10K

R5

U4

V+

V-

U5

V+

V-

U6

V+

V-

10K

R1

10K

R2

10K

R3

10K

R4

10K

R6

10K

R7

10K

R8

10K

R9

10K

R10

10K

R11

10K

R12

U3

V+

V-

U1

V+

V-

U2

V+

V-

14K

R13

1K

R14

14K

R15

1K

R16

14K

R17

1K

R18

14K

R19

1K

R20

A1

2.88k

R21

160

R22

160

R23

100

R24

U7OU

TG

ND

VD

D

NPIN

U8OU

TG

ND

VD

D

NPIN

U9OU

TG

ND

VD

D

NPIN

2.75k

R25

220

R26

230

R27

100

R28

U10OU

TG

ND

VD

D

NPIN

U11OU

TG

ND

VD

D

NPIN

U12OU

TG

ND

VD

D

NPIN

A2

A3

A5

A4

A6

A7

A8

A9

A10

FD1FD2FD3

BLUE GREEN RED Sense

SEL_BSEL_A

VDD

Figure 16. Fault Detection Circuit Schematic

Table 2 below shows the expected differential voltages based on the Osram

‘Golden Dragon’ series. The table also shows the LED selector inputs used to internally

generate each of the required reference levels used internally by the comparator. The

approximate forward voltage of the Red and Green/Blue series is 2.4V and 3.4V

respectively. Since the SCR has a dropout of 1V, it is reasonable to assume that the total

voltage drop across both a SC LED and a SCR will be below 1.5V. The thresholds were

based on a 1.5V level to provide a safety margin in the event of an OC LED being

Sense Amp

Multiplexer RED

Voltage Levels

Green/Blue Voltage Levels

31

bypassed by an SCR. The maximum differential range needed is 10.2V / 15 or .68V. The

minimum common mode expected is approximately zero volts. The maximum common

mode expected is 1.2V, so the maximum operating range (common mode plus

differential) needed from the differential op amp is from approximately zero volts to

1.88V (1.2V + .68V). In addition, the minimum difference between the comparator

threshold and the LED differential voltage is 60mV. This necessitates that the op amp’s

offset voltage be much less than 60mV while the minimum Vin of the comparator be

10mV or less for a good error margin.

Table 2. FD Threshold Levels Based On LED Selector Inputs A and B B A # LED’s Differential

Voltage (V) /15 Comparator Threshold (V)

0 0 1 x 2.4V .160 .100

0 1 2 x 2.4V .320 .260

RED Voltage Levels

1 0 3 x 2.4V .480 .420

0 0 1 x 3.4V .227 .100

0 1 2 x 3.4V .453 .330

BLUE/GREEN Voltage Levels

1 0 3 x 3.4V .680 .550

Figure 17 below shows a simulation of the fault detection circuit. The fault

detection for the Green LED’s was shown as representative of all three detection groups.

In the simulation, both the LED selector inputs (A and B), as well as the number of

LED’s physically present (denoted by the 0, 1, 2, and 3 boxes) were simulated so as to

cover all the combinations of LED’s and LED selector inputs. The top graph shows the

32

digital FD2 signal response, corresponding to the green fault signal. The top-middle

graph shows the change in differential voltage across the green LED’s according to how

many are ‘ON’ in the circuit. The bottom two graphs show the digital LED selector input

settings. The first 250µs of the simulation shows that the circuit only indicates a short

when 0 LED’s are active in the circuit, because the current LED selector input setting is

set to 1 LED (A=0 and B=0). The next 250µs section shows the response with the 2 LED

setting, and the last 250µs time section shows the response with the 3 LED setting. As

can be seen from the graph, if the number of LED’s turned ON are less than the minimum

expected from the LED selector, the circuit indicates a fault.

Thesis_FD_Circuit_test-Transient-17-Graph Time (s)

0.0 100.0000u 200.0000u 300.0000u 400.0000u 500.0000u 600.0000u 700.0000u

v(Green Diff Voltage)

-1.000 v(FD2) -1.000 v(Green Diff Voltage) -1.000 v(b) -1.000

-1.000 D(TIME) -1.000 D(v(FD2)) -1.000

Figure 17. Simulation of the Fault Detection Circuit Showing All Possible Operational Conditions

A=0

A=0

Green Dif Voltage: # of LED’s in circuit

FD2 (Green Fault)

3 2

1 0

A=1

B=0

B=0 B=1 LED Selector Inputs

1 LED MIN

2 LED’s MIN

3 LED‘s MIN

Good LED Fault

Time (s)

0.0 100.00u 200.00u 300.00u 400.00u 500.00u 600.00u 700.00u

33

Open Circuit Bypass Design

The OC bypass circuit is the simplest circuit in the thesis. The circuit’s

purpose is to automatically engage a parallel bypass element when the voltage across an

LED element rises above normal values. The simplest solution is ADDtek’s AMC7169

500mA 2-terminal LED protector. It has a thyristor-like characteristics with a 5V trigger

voltage, 1V drop out, and 100nS response time. Essentially, it works by turning ON when

the voltage across its two terminals rises above 5V, and turns OFF when the voltage

across it is less that 1V. So in the bypass circuit, the thyristor will turn ON when the

power supply drives the voltage across an open circuit LED past the 5V trigger.

Conversely, the thyristor will turn OFF when the intensity control MOSFET turns ON

thereby decreasing the voltage across the open circuit LED to the MOSFET’s VDSON,

which is much less than the thyristor’s1V drop out.

34

CHAPTER FIVE

PHYSICAL DESIGN AND VERIFICATION

Introduction

The second aspect of the thesis was to implement the light intensity control circuit

in hardware with off-the-shelf discrete components as proof concept for the design.

Figure 18 shows the circuit built on a printed circuit board (PCB) for testing. Figure 19

and Figure 20 show pictures of the PCB boards made for the hardware circuit. Both the

light intensity control PCB and the LED PCB were manufactured at Clemson University.

The BUCK power supply PCB is a modified TI TPS40200 evaluation board.

35

Current Mirror

Buck PWM Power Supply

PIC16F84

Digital PWM Control Inputs

X18

X17X16X15

X14

2.6k

R12

X13

X12X11

2.6k

R11X8

X7 X6

X10

X5

X4

D9

D8

D7

D6

D5

D3

D4

SW5

SW6

SW4

SW3

SW2

SW1

1K

R91K

R81K

R7

1K

R61K

R51K

R4

beta= 300

Q3beta= 300

Q2beta= 300

Q1

X4 4MHz

1u

C2

1u

C1

5V

VDD

30V

VDDHU5

INVDD

GND

OUT

X9

1k

R3

1k

R2

X3

X2

1k

R1

2.6k

R10

X1

D1

D2

1.4

RSenseU4

Figure 18. Hardware Light Intensity Control Circuit Schematic

36

Figure 19. Complete Hardware LED Intensity Control Setup Photo

Light Intensity Controller PCB

BUCK Power Supply

OSRAM LED’s PCB

37

Figure 20. Hardware Light Intensity Control PCB

For a practical implementation, only the PWM buck controller and the LED

intensity control circuit were implemented. Using a PIC, the average LED current can be

varied in the lab from 25 to 475mA. The circuit was then tested for functionality and

performance in each of the modes of operation. Two PCBs were created for the project;

one for the intensity control circuit, and the other for the LED’s. The LED’s were laid out

on a separate PCB using the copper plane as a heat sink.

Figure 18 shows the general PWM controller schematic that was used for the lab

hardware circuit. The resistor RSense was used to provide the 700mV reference needed

for the PWM buck converter. The LED’s represent each color group where there can be

Microcontroller

PWM Control Switches

LM311 – 3.3V Supply

PMOS Current Mirror

Power N-Channel MOSFET’s

38

up to three LED’s per group. The current mirrors were implemented as shown in Figure

21. In the mirror circuit, R2 was added to set the proper current. A simulation of the

hardware current mirror circuit (Figure 22) shows similar operation to the IC controller’s

current mirror. The TPS40200 was used as the asynchronous voltage mode buck

converter. The internal feedback amplifier is referenced to a 1% 700mV reference. The

BJT’s were added to enhance the output drive of the PIC 16F84. The PIC was

programmed to use two inputs per channel; one to raise the duty cycle and the other to

lower the duty cycle on each channel individually. Each channel can be set to a duty

cycle of 0%, 100%, or a duty cycle between 5% and 95% as determined by the inputs

(SW1 through SW6). The LED dimming circuit was tested in the lab first on a

breadboard, and then on a simple PCB setup. Figure 23 shows the modified evaluation

board that was used for the PWM buck converter circuit. The output capacitors and the 2-

pole compensation network were removed from the module. A smaller capacitor was

added along with a 3-pole compensation network. Also, the clock frequency was changed

to 450kHz. These changes were necessary to insure stable power supply operation while

the LED’s were switching ON and OFF. Additional detail on the power supply changes is

provided in Appendix B.

39

IN1

X5

X3

X2X4

VDD

X1

2.6k

R2

Figure 21. Hardware Current Mirror Circuit Schemati c

MOSFET Gate Control Output

OUT

IN

VDD

40

Thesis_Lab Circuit-DC Transfer-7-Graph V_BIAS

10.0000 12.0000 14.0000 16.0000 18.0000 20.0000 22.0000 24.0000

0.0

1.000

2.000

3.000

4.000

5.000

6.000

7.000

V_BIAS 19.065 VDSON 202.515m VGS 4.919 D(V_BIAS) 0.0 D(VDSON) 0.0

Figure 22. Simulation of the Hardware's Current Mirror Circuit Showing Maximum Bias for Operation

TPS40200

U1

C1

R1

D1

X1

L1

C2

R2R3C3

C4R4

IN

VDDH

OUT

C5

R5

R6

C6

C7

R7

FB

Figure 23. Complete Hardware Switch Mode Power Supply Circuit Using the TPS40200

MOSFTET VGS

MOSFET VDSON

MAX BIAS for MOSFET Operation at 19.7V

BIAS Voltage

Volts

7.00

6.00

5.00

4.00

3.00

2.00

1.00

0.0

10.00 12.00 14.00 16.00 18.00 20.00 22.00 24.00

41

The PIC was programmed to generate a 50% duty cycle for each channel at

startup. For simplicity, the program turns each channel ON at the same time, and turns

each channel OFF based on that channel’s PWM setting. The program continually scans

the inputs to see if any input has been activated. When one of the signals is detected, the

program adjusts the corresponding channel’s pulse width setting. When turned ON, the

input will either increment or decrement the pulse width each time the program goes

through a loop. Once the pulse width goes below 5% or above 95%, the program sets the

pulse width to 0% or 100% respectively. The 16F84 PIC program produces a 320Hz

PWM signal that is more than fast enough to avoid flickering. Table 3 below list the parts

used for the hardware circuit found in Figure 18.

Table 3. Parts List for Hardware Circuit

Part Description Specification/Value

R1, R2, R3, R4, R5, R6, R7, R8, R9

Resistor 1k ohms 5% 1/4W

R10,R11, R12 Resistor 2.6k ohms 5% 1/4W RSense Resistor 1.4 ohms 5% 1/2W C1, C2 Ceramic Capacitor 1uF 10%

U4 Crystal 4MHz Q1, Q2, Q3 BJT Transistor 2N3904 D1, D2, D3 Osram Golden Dragon LED LR W5SM D4, D5, D6 Osram Golden Dragon LED LT W5SM D7, D8, D9 Osram Golden Dragon LED LB W5SM X1, X2, X3 N-Channel Power MOSFET IRF520

X5, X12, X17 N-Channel MOSFET ZVN4424a X4, X6, X7, X8, X9, X10, X11, X13, X14, X15, X16,

X18

P-Channel MOSFET ZVP4424a

Buck PWM Power Supply Voltage Mode Buck SMPS TI TPS40200 EVM

42

Hardware Intensity Control Circuit Results.

The following shows the performance of the hardware circuit in the different

modes of operation. These tests are done with the hardware circuit powered with 3 LED’s

per group. Figure 24, Figure 25, and Figure 26 below show the Green LED current at

5%, 50%, and 95% duty cycles respectively. The graphs show the LED current in

response to the digital PWM control pulse. As in the simulations, the hardware tests show

that the LED current rise time is much slower than the current fall time. Despite the slow

rise times, these graphs show the circuit operates correctly across the specified PWM

range.

5% Duty Cycle

43

Figure 24. Scope Graph of 5% PWM Showing Digital Input and Output Current

Figure 25. Scope Graph of 50% PWM Showing Digital Input and Output Current

50% Duty Cycle

44

Figure 26. Scope Graph of 95% PWM Showing Digital Input and Output Current

In addition to operating from 5% to 95% duty cycles, each LED group can

operate at a different duty cycle, independent from the two other LED groups. To show

this mode of operation, the duty cycles were set to 95% for the red group, 50% for the

green group, and 5% for the blue group. Figure 27 shows the oscilloscope’s graph of the

differential voltage across each LED group. Currently, the simple PWM program will

turn OFF the channels at different times if they are at different duty cycles, but will

always turn them ON at the same time. Therefore, a more advanced program could put

the channels on different phases to limit switching OFF or ON at the same time. The

Buck control loop would then benefit by increased stability and faster response to the

intensity control MOSFET switching transients. Also, the intensity control MOSFET

95% Duty Cycle

45

transistors can be made to switch slower, which in turn decreases the intensity of the

transient spikes from the power supply. The power supply then would be able to supply a

more stable current output.

Figure 27. Multi Duty Cycle Graph, Red=95%, Green=50%, Blue=5%

The data below shows the currents measured from the hardware circuit across the

entire PWM intensity control range. Table 4 below shows the input conditions used to

test the different PWM duty cycles. For this test, the microcontroller was removed, and a

function generator was used to produce a 120Hz pulse at the tested duty cycles. The

power supply’s peak current was measured and was used to scale the expected average

LED current.

Green Differential Voltage (50% Duty)

Red Differential Voltage (95% Duty)

Transient spikes from the intensity control MOSFET switching OFF

Blue Differential Voltage (5% Duty)

46

Table 5 shows the results as measured by an oscilloscope. The equation for the

oscilloscope’s average current measurement is shown below.

SamplesNumber_of_

II AVG

∑=

In addition to the average current measured, the percent error is also shown.

Table 4. Green LED Input Test Conditions and Expected Output Current

Input Duty Cycle (%) +/- .01%

Expected Average LED Current (mA)

1 4.9 5 24.5 10 49 20 98 30 147 40 196 50 245 60 294 70 343 80 392 90 441 95 465.5 99 485.1 100 490

Table 5. Measured Results From Group 2

Duty Cycle(%) +/- .05%

Average LED Current (mA) +/- 1mA

Average LED Current % Error

2.3 18.5 277.55 4.3 27.4 11.84 9.3 51.5 5.10 19.3 99.9 1.94 29.3 148.0 0.68 39.3 196.3 0.15 49.3 244.7 -0.12 59.3 293.1 -0.31 69.3 341.6 -0.41

47

Duty Cycle(%) +/- .05%

Average LED Current (mA) +/- 1mA

Average LED Current % Error

79.3 389.9 -0.54 89.3 438.4 -0.59 94.3 462.6 -0.62 98.5 482.1 -0.62 100 490.9 0.18

Table 5 shows that the measured duty cycle of the LED current was typically .7%

less than expected, and this results in a small error in the LED average current. The

combined effects of an approximately 133µs rise time and 60µs delay cause a slight error

in the LED average current. These results show that the hardware circuit prototype

produces less than 2% error, on average, in LED current across the entire PWM range.

The worst percent error measured was 12% at the 5% duty cycle setting. The 1 percent

and 99 percent duty cycles were included to show the circuit’s performance outside of the

specified duty cycle range.

48

CHAPTER 6

PERFORMANCE RESULTS AND CONCLUSION

This chapter covers the results and conclusion of the LED light intensity

controller circuit. The following results are classified under two categories, nominal and

parametric. The nominal tests cover the different circuit block’s functionality under

nominal conditions. The parametric tests were performed to show that the system works

under temperature, process, and power supply variations.

Results

Mentor Graphic’s Eldo simulator was used to verify the post-layout circuit

netlists. The process used was a TSMC 0.35µm 3.3V process. All the circuit blocks were

implemented in layout except for the external OC bypass circuit. Each block was

simulated to check for both correct functionally and reliability with parametric variations.

Previously, SPICE was used to check for correct functional operation of each of the

blocks. SPICE is a better analog simulator, but it lacks the ability to handle the large

netlists generated from the layout. A new simulator called ELDO is used for all the layout

simulations. The reason for the post-layout simulations is to include the stray

capacitances and resistances that adversely affect integrated circuit design. The main

parametric variations of concern are temperature, resistor variations, and power supply

variations. The parametric variations were chosen to simulate the robustness of the design

under approximately real world scenarios. The temperature range for an LED light source

can vary over extreme ranges due conditions like outside temperature, increased ambient

49

heat from the hot LED’s, and the enclosure that the light is in. The industrial temperature

range of -40oC to 85oC will be used. The absolute resistor values can vary from one chip

to the next by as much as +/- 20%. On the other hand, on the same chip, resistor to

resistor variation is typically considered very small. A resistor to resistor deviation of .1%

will be used. As this controller is not a digital chip, and is in fact more of an analog

power chip, power supply variations are very likely. The two main supplies of concern

are the 3.3V digital supply and the 24V floating gate control supply. The digital supply is

primarily for the fault detection circuit, while the gate control voltage source directly

affects the PWM intensity control operation.

The following tables show the nominal simulation results for the floating gate

controller circuit and the fault detection circuit. Each circuit was tested for the

characteristics that most affected the specifications and performance. The nominal and

parametric data for both the floating gate controller and fault detection circuit were taken

from the second (middle) group as representative of all three.

Table 6. Floating Gate Controller Post-Layout Nominal Results Nominal Layout Simulation Results Time Delay: (TPLH/TPHL) 1.089µs/.469µs Rise/Fall Time 1.531µs/1.438µs Gate Drive Voltage 7.954V VDSON .28V*

* The reason for the high VDSON is discussed in Chapter 3 and Appendix D

Table 7. Fault Detection Circuit Post-Layout Nominal Results

Nominal Layout Simulation Results

Expected Trigger Point

Time Delay 87ns N/A FD1 Trigger Point (1 LED) 86mV 100mV FD1 Trigger Point (2 LED’s) 259mV 268mV

50

Nominal Layout Simulation Results

Expected Trigger Point

FD1 Trigger Point (3 LED’s) 434mV 420mV FD2 Trigger Point (1 LED’s) 86mV 100mV FD2 Trigger Point (2 LED’s) 345mV 330mV FD2 Trigger Point (3 LED’s) 594mV 550mV FD3 Trigger Point (1 LED’s) 81mV 100mV FD3 Trigger Point (2 LED’s) 328mV 330mV FD3 Trigger Point (3 LED’s) 566mV 550mV

The following tables show the post-layout simulation results, verifying the

robustness of each internal circuit block. The temperature variation tests were done at -

40oC and 85oC. The resistor variation tests were done at + and – 20% for the floating gate

controller circuit and as a Monte Carlo type simulation for the fault detection circuit in

which 50 runs were performed with a +/- 20% lot variation and .1% deviation. This

means that all the resistors in the simulation had a +/- 20% tolerance (could vary from

their nominal value by as much as +/- 20%) and they could vary from each other up to +/-

.1%. The power supply variation tests were performed at + and - 6%. Finally, the worst-

case test was performed as a Monte Carlo of 50 runs with the following tolerances.

• Temperature: (-40 to 85)

• Resistance: ( +/- 20% lot, .1% deviation)

• Power Supply: (+/- 6% lot)

51

Table 8. Floating Gate Controller Circuit Post-Layout Parametric Results Gate Drive Voltage (V) Rise Time (µs)

T = -40C 11.21 1.52 Temperature Variation T = 85C 6.21 1.54

-20% 6.52 1.22 Resistor Variation +20% 9.38 1.79

-6% 6.68 1.57 Power Supply Variation +6% 9.31 1.53

Min 5.25 1.28 Worst-Case Max 13.60 1.73

Table 9. Fault Detect Circuit Post-Layout Parametric Results

FD2 Trigger Point (2 LED’s) (mV)

T = -40C 344 Temperature Variation T = 85C 347

Mon.Car. Min 339 Resistor Variation Mon.Car. Max 356

-6% 325 Power Supply Variation +6% 365

Mon.Car. Min 323 Worst-Case Mon.Car. Max 367

Conclusion

This IC controller design, as seen in Appendix E. successfully meets all the

functional requirements, namely to provide PWM light intensity control of three (red,

green, and blue) LED groups. It is valid to conclude that this design can function as an

architectural light or for wall washing. The design meets all the specifications with the

proviso that the manufacturing process used for the IC fabrication incorporates LDD

MOSFET’s and has the N+ diffusion sheet resistance specified in Appendix D. The

parasitic resistances have a significant effect on the VDSON when using the TSMC 0.35µm

52

process. An alternative would be to use discrete off-chip power MOSFET’s. In the end,

the cost of on-chip versus off-chip would be the deciding factor.

The hardware circuit was helpful in backing up the simulations with some real

measurements of the circuit operation. Because the simulations did not include the switch

mode power supply, the hardware circuit was useful in observing the power supply’s

response to the switching LED’s. The result was that the power supply design itself is

non-trivial, and has a direct impact on the performance of the IC controller’s stability.

The current mirror was a good approach to the floating gate controller. If more

LED’s were needed, then a charge pump circuit would be required. On the other hand, an

arguably cheaper solution would be to use three separate power supplies, one for each

LED color. Of each of the circuit blocks, the fault detection seemed to be the most

optimum solution. An improvement could be made, however, in the resistor divider to

level shift the LED voltage down to CMOS voltage levels. More advanced circuits are

certainly possible for the open circuit detection. The SCR approach was chosen as a low

cost solution. A circuit that individually controlled the gates of each thyristor would

potentially be more effective at bypassing open LED’s, at the expense of increased cost.

An Area for further work is some form of feedback to the IC controller. Currently,

the only feedback to the microcontroller is the LED fault status. Therefore, if an LED

fails, then there is no way for the microcontroller to accurately adjust for the loss. More

precise control of the color spectrum could be attained with light sensors used to provide

feedback to the microcontroller. Feedback would broaden the scope of applications that

this LED design could meet as well as provide a more attractive multi-color light source.

53

APPENDICES

54

Appendix A

LDDMOSFET Details

Minimum Required MOSFET Specifications for IC Controller Circuit.

Table 10. 40Volt NMOS LDD MOSFET Parameters

Allowed Operating Conditions

Lower Spec Limit

Upper Spec Limit

Units Comments

Vds 40.0 Volts Drain-source Vgs 16.5 Volts Gate-source Vgd -40.0 16.5 Volts Gate-drain Vdg 40.0 Volts Drain-gate Vd, sub 60.0 Volts Drain-substrate Vs, sub 60.0 Volts Source-substrate Temperature Range -40 150 C

Table 11. 60Volt NMOS LDD MOSFET Parameters

Allowed Operating Conditions

Lower Spec Limit

Upper Spec Limit

Units Comments

Vds 60.0 Volts Drain-source Vgs 16.5 Volts Gate-source Vgd -60.0 16.5 Volts Gate-drain Vdg 60.0 Volts Drain-gate Vd, sub 60.0 Volts Drain-substrate Vs, sub 15.0 Volts Source-substrate Temperature Range -40 150 C

Table 12. 24Volt PMOS LDD MOSFET Parameters

Allowed Operating Conditions

Lower Spec Limit

Upper Spec Limit

Units Comments

Vds -24 Volts Drain-source Vgs -20 Volts Gate-source Vgd -20 Volts Gate-drain Vdg -24 Volts Drain-gate Vd, sub -24 Volts Drain-substrate Vs, sub -20 Volts Source-substrate Temperature Range -40 150 C

55

Appendix B

Voltage Mode PWM BUCK Constant Current Supply

The PWM current supply works by the popular buck operation. The chip I will be

using is the TPS40200. It is rated up to a 52V input, and it uses a 700mV internal

reference, which is the level of the FB signal input. In general, the buck DC/DC converter

will try to drive its output so that the sense voltage input equals its 700mV reference.

Typically, the main components of a buck converter are a PMOS transistor, an inductor, a

diode, and a capacitor.

Figure 28. Voltage Mode Buck Converter and Type3 Compensation Loop [3]

56

Another aspect of my control design is the feedback loop of the buck PWM

converter. Due to the nature of the switching frequency of the converter, it will not work

to simply connect the output of my sense amplifier to the voltage sense input of the

converter. A second complication is that with the PWM dimming, there are a lot of

current transients due to the PWM switching of the bypass transistors. There are two

common well-used and documented methods of providing a stable feed back loop. They

are referred to as two pole and three pole compensation loops. A three pole compensation

system is required to give a better phase response to the switching transients of the

bypass transistors [3].

57

Appendix C

Op Amp and Comparator Design

This appendix details the design of the op amp and comparator used in the LED

fault detection block. Both the op amp and the comparator designs were based on the

classic two stage amplifier design [4, 5, 6, and 7]. The design specifications needed for

the op amp and comparator are as follows:

• OP AMP

o Minimum Common Mode Range = .15 – 1.2V

o Minimum Differential Range = 680mV

o VOS < 50mV

o Open Loop Gain >= 5000

o Stability Condition: Phase Margin >= 60o

• Comparator

o VIN < 10mV

o Minimum Differential Range: 600mV

o VOS < 100mV

o Time Delay <= 1µs

The design of the op amp and comparator were mostly straightforward. A PMOS

differential pair was chosen to provide an input common mode range that extended close

to zero volts. A minimum Input Common Mode Range (ICMRMIN) of 0.15V was chosen

because that is the minimum expected voltage for one RED LED and the 0.7V drop

58

across the sense resistor. The minimum ICMR was calculated by the following:

VICMRMIN 150.15

4.27. ≈+= .

The common mode and the overdrive voltage are related by the following

equation:

TPTNGSTPDS VVVVVICMR −+=−> 33 .

An overdrive voltage of 0.28V was chosen based on the ICMRMIN of 0.15V. The

overdrive of 0.28V was used for each of the MOS device size calculations. The W/L

calculations were made initially with an ID of 100µA as a starting point, and then the

current was adjusted through simulations to provide an optimum between VOS, output

current drive, and gain. The Voltage Offset (VOS) was minimized by the following

equation:

5MOS

7MOS

4MOS

6MOS

L

W

L

W

*2

L

W

L

W

=

This equation makes sense since M6 and M7 share the same current, while M5 is

carrying twice the current of M4. Therefore, the circuit will have the least offset, not

including device matching issues, when the devices are balanced correctly. Figure 29

below shows the op amp schematic and MOS sizes.

59

V+V-

W/L = 160

W/L = 60

W/L = 64

W/L = 32W/L = 32

W/L = 12W/L = 12

W/L = 64

W/L = 0.36

N P

M5

M2M1

M6

M7

M3 M4

M8

M9

0.6p

C1

GND

VDD

OUT

Figure 29. Op Amp for Fault Detection Circuit

Figure 30 below shows the closed loop circuit used to sense the differential

voltage across an LED group. Simulations of the op amp with a current of 100µA gave a

VOS of 62mV and an open loop gain of 4200. Since both measurements were outside of

the desired specifications, the current was reduced until the specifications were met.

Reducing the current improves the offset voltage because less current translates into a

smaller voltage drop across the transistor, and hence less offset. Secondly, current is

indirectly proportional to Voltage gain in the following equation:

)(5. LWK

I

V

V

VA

D

A

OV

AV

××

== .

ID = 50uA

60

Therefore, decreasing the current will increase the voltage gain. Through simulations it

was found that reducing the current to 50µA met the specifications. Also, simulations of

the circuit in Figure 30 showed that the minimum resistor value that still provided the

differential range needed was 5kΩ.

U1

V +

V -

5K

R1

5K

R2

5K

R3

5K

R4

A

B

VDD

A_minus_B

Figure 30. Closed Loop Op Amp Circuit

Figure 31 below shows the performance of the op amp over the frequency range

of 0.1Hz to 1GHz. The performance of the op amp was summarized in Table 13 below.

Each of the desired specifications were either met or exceeded. Figure 32 below shows a

typical simulation of the output verses the differential voltage (A-B) at a fixed common

mode of 0V. The simulation graph shows the range of differential voltage for which the

output stays linear within +/- 10mV of the expected output. The bottom non-linearity is

due to the fixed offset voltage, while the upper non-linearity is due to op amp output

61

current driving the two 5kΩ resistors. These simulations show that the op amp will be

more than suitable for the fault detection circuit.

Thes is_FD_Sense_olfr-Small Signal AC-5-Graph Frequency (Hz)

100.0000m 1.0000 10.0000 100.0000 1.0000k 10.0000k 100.0000k 1.0000Meg 10.0000Meg 100.0000Meg 1.0000G

-300.000

-250.000

-200.000

-150.000

-100.000

-50.000

0.0

50.000

FREQ -1.000 PH_DEG(v(n1)) -1.000 DB(v(n1)) -1.000 D(FREQ) -973.397m D(DB(v(n1))) -1.000

Figure 31. Op Amp Open Loop Frequency Response at ID = 50µA

Table 13. Fault Detection Op Amp Performance Specification SPICE Simulation

Performance Closed Loop Differential Range (VCM=0V)

680mV 1000mV

Closed Loop Common Mode Range (VDIFF=680mV)

1.2V 2.6V

Offset Voltage 50mV 34mV Open Loop Voltage Gain 5000 5300 Stability: Phase Margin 60 degrees 60 degrees

Phase Margin = 60o

Gain Bandwidth = 60MHz

Gain = 74.5dB = 5300 MAG

Frequency (Hz)

dB/ Degrees

50.00

0.0

-50.00

-100.00

-150.00

-200.00

-250.00

-300.00

0.1 1.0 10.0 100.0 1.0k 10.0k 100.0k 1.0M 10.0M 100.0M 1.0G

62

Thes is_FD_Sense-DC Transfer-24-Graph V5

0.0 200.0000m 400.0000m 600.0000m 800.0000m 1.0000 1.2000 1.4000

(V)

0.0

200.000m

400.000m

600.000m

800.000m

1.000

1.200

1.400

V5 -1.000 OUT -1.000 D(V5) -1.000 D(OUT) -1.000

Figure 32. Closed Loop Simulation of Differential Voltage (VCM=0)

The comparator specifications were even less demanding than the op amp

specifications. The only practical concern was the minimum input voltage required to

switch the output. The design specifications call for a 10mV minimum input voltage to

provide an error margin between the target threshold level and the voltage from the op

amp. To meet the design specifications, the same circuit topology was used as the op

amp, but without the miller capacitor. Furthermore, as only a low performance level was

required, the circuit was found to have nearly the same performance if the devices and

currents were scaled down by a factor of 10. Without the compensation capacitor, the op

amp circuit becomes unstable, and functions as a comparator. Essentially, anytime the

differential voltage between the two inputs increases above the minimum input voltage,

Start of linear section at 40mV (within 10mV)

A – B Output Voltage

Differential Input Voltage

End of linear section at 1.44V (within 10mV)

Volts

Volts

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.0

0.0 0.20 0.40 0.60 0.80 1.00 1.20 1.40

63

the output will swing to either the GND or VDD power supply rail. The circuit schematic

used for the comparator is shown in Figure 33 below.

V+V-

W/L=16

W/L=0.48

W/L=6

W/L=3.2W/L=3.2

W/L=1.2W/L=1.2

W/L=6.4W/L=6.4

M8

M4

OUT

VDD

GND

M3

M7

M6

M1 M2

M5

M9

N P

Figure 33. Comparator for the Fault Detection Circuit

The simulation performance results in Table 14 below, shows that the comparator

meets or exceeds the specifications. Figure 34 shows the simulation of a sweep of the

input differential voltage. The minimum input voltage required to change digital states

was measured from 10% to 90% of the maximum output voltage (VDD). This simulation

shows that the comparator exceeds the design specifications by a factor of 10. Figure 35

below shows the results of the simulation of the comparator’s common mode range and

offset voltage. Both specifications were easily meet with this comparator design. For this

simulation, a negative VIN was used so that the offset voltage would show up as well as

ID = 5uA

64

the available common mode range. A positive VIN was also simulated (not shown), with

the result that the output remained constant at 3.3V through the entire range of 0V to

3.3V. These simulations show that this simple adaptation of the op amp is more than

adequate for use as a comparator in the fault detection circuit.

Table 14. Fault Detection Comparator Performance Specifications SPICE Simulation

Performance Minimum Vin <10mV 1mV Minimum CM Range 100mV to 600mV 0V to 2.6V VOS (VCM = 0V) <100mV 50mV Time Delay (VIN = 10mV) <1µs 40nS

65

Thes is_FD_Comp-DC Transfer-18-Graph V2

-1.0000m -800.0000u -600.0000u -400.0000u -200.0000u 0.0 200.0000u 400.0000u 600.0000u 800.0000u 1.0000m

(V)

0.0

500.000m

1.000

1.500

2.000

2.500

3.000

V2 -1.000 v(n1) -1.000 D(V2) -1.000 D(v(n1)) -1.000

Figure 34. Comparator Differential Input Simulation Showing Min VIN

Thes is_FD_Comp-DC Transfer-13-Graph V6

0.0 500.0000m 1.0000 1.5000 2.0000 2.5000 3.0000

(V)

0.0

500.000m

1.000

1.500

2.000

2.500

3.000

V6 -1.000 v(n1) -1.000 D(V6) -1.000 D(v(n1)) -1.000

Figure 35. Comparator Simulation Showing the Input Common Mode Range, VIN = -10mV

VOS: 50mV Offset at VCM =0V

Comparator Output Voltage

Input CM Voltage

VIN = -10mV

Input CM Range = 0V to 2.6V

Comparator Output Voltage Differential

Input Voltage

Common Mode Fixed at 0V

VIN = 1mV (10% to 90%)

Volts

3.00

2.50

2.00

1.50

1.00

0.50

0.0

0.0 -200.00u -400.00u -600.00u -800.00u -1.00m 200.00u 400.00u 600.00u 800.00u 1.00m

Volts

Volts

3.00

2.50

2.00

1.50

1.00

0.50

0.0

0.0 0.50 1.50 1.00 2.00 2.50 3.00

Volts

66

Appendix D

MOSFET VDSON Issues

Differences were found in the MOSFET’s VDSON between the SPICE and post-

layout simulations. SPICE does not accurately reflect layout effects such as N+ diffusion

sheet and contact resistance unless the net list is extracted from the layout. Running

SPICE from the schematic and using approximate values (NRD = NRS = L/W)

introduces significant differences for large width devices. A VDSON of 85mV was found

using this approach.

Investigation showed that large sheet and contact resistances were dominating the

IDS curve of the MOSFET. A marginal improvement was made by adjusting the finger

width of the MOSFET. It was also found that increasing the width further did not help,

but using several devices in parallel did lower the VDSON. Using several MOSFET’s in

parallel was not used as a solution because of the increased area needed as well as

matching issues affecting unequal currents through the devices.

Below is the extracted drain resistance network from Caliber’s PEX netlist

extraction. This is the extracted resistances from one MOSFET finger at a finger width of

10µm. The total drain resistance from the sub-circuit is 2.438 ohms. This proved to be

close to the optimum resistance. By increasing the source and drain contact area to a

maximum and widening the finger width (see sketch below) to reduce the drain

resistance, the optimum values were obtained for this 0.35µm process. This resulted in a

VDSON value of 280mV.

67

.subckt PM_MOSTEST5$ Drain 24 25 R0 22 24 0.041125 R1 20 21 0.133622 R2 19 20 0.133622 R3 18 19 0.133622 R4 17 18 0.133622 R5 16 17 0.133622 R6 15 16 0.133622 R7 14 15 0.133622 R8 25 4 1.23672 R9 2 4 0.000751567 R10 2 14 0.133622 R11 1 22 0.0450476 R12 1 21 0.133622

The NSRCDRN (N+ diffusion resistance) extraction parameter is 81.1

(ohms/square) for the TSMC 0.35µm process while it was found to be 4.1 for the TSMC

0.25µm process. It is expected then that a process with half the sheet resistance or less

Drain

Source

MOSFET Length = .6um

MOSFET Gate Finger Length = 1705um

MOSFET Finger Width = 10um

Drain

Source

MOSFET Width = 15,000um with 44 Fingers

68

would be satisfactory and it would be possible to fabricate a MOSFET that could produce

the correct VDSON.

69

Appendix E

IC Controller Layout

Figure 36. Layout Plot of the IC Controller Design

70

Figure 37. Layout Plot of the Floating Gate Controller Block

71

Figure 38 Layout Plot of the Fault Detection Block

72

Figure 39 Layout Plot of the Sense Op-Amp for the Fault Detection Block

73

Figure 40 Layout Plot of the Comparator for the Fault Detection Block

74

REFERENCES

1. 2007 Federal Energy Legislation, American Council for an Energy-Efficient

Economy, December 14, 2007, www.aceee.org/energy/national/07nrgleg.htm. 2. Osram OPTO Semiconductors, Dimming InGaN LEDs: Application Note,

http://catalog.osram-os.com/catalogue/catalogue.do?favOid=000000030002122001bd00b7&act=showBookmark, January 8, 2003.

3. Richardson, Chris, “Driving High Brightness LED’s with Switching Regulators”,

Power Management: Design Line, March 21, 2006. 4. Razavi, Behzad, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill

2001. 5. Adel S. Sedra and Kenneth C. Smith, “Microelectronic Circuits”, 5th Ed. Oxford

University Press, 2004. 6. Gray, Paul R., Hurst, Paul J., Lewis, Stephen H., Meyer, Robert G., “Analysis and

Design of Analog Integrated Circuits”, 4th Ed. John Wiley & Sons, Inc. 2001. 7. Phillip E. Allen and Douglas R. Holberg, “CMOS Analog Circuit Design”, 2nd

Ed. Oxford University Press, 2002.