1

DESIGN OF A POWER HI-FI SYSTEM

2

CONTENTS

Preamplifier

Preamplifier architecture ……………………………………………………… 8

Balance control ………………………………………………………………... 9

Balance control working principle …………………………………………. 11

Noise ………………………………………………………………………... 12

Distortion …………………………………………………………………… 13

Treble control …………………………………………………………………. 14

Bootstrap ……………………………………………………………………. 14

Bootstrap on the treble control …………………………………………….... 15

Noise ……………………………………………………………………….... 16

Distortion ……………………………………………………………………. 17

Bass control ……………………………………………………………………. 18

Noise ……………………………………………………………………….... 20

Distortion ……………………………………………………………………. 21

Tone control sum stage ………………………………………………………… 21

Volume control ………………………………………………………………… 23

Noise ………………………………………………………………………… 24

Distortion ……………………………………………………………………. 25

Preamplifier performance ……………………………………………………… 26

Active crossover

Bandwidth definition filter ……………………………………………………... 30

High-pass section ……………………………………………………………. 30

Poles location and behavior ………………………………………………….. 32

3

Noise …………………………………………………………………………. 34

Distortion …………………………………………………………………….. 35

Low-pass section ………………………………………………………………... 36

Noise ………………………………………………………………………….. 38

Distortion ……………………………………………………………………... 38

Linkwitz-Riley crossover filters ………………………………………………… 39

Low-pass filter ………………………………………………………………... 40

Noise ……………………………………………………………………….. 41

Distortion …………………………………………………………………... 42

High-pass filter ……………………………………………………………….. 42

Noise ……………………………………………………………………….. 44

Distortion …………………………………………………………………... 44

Time delay ………………………………………………………………………. 45

Required delay ………………………………………………………………... 45

Filter calculations and response ………………………………………………. 46

Source code of the parallel resistor finder ………………………………………. 48

Power amplifiers

Input stage and VAS …………………………………………………………….. 53

Current source …………………………………………………………………... 55

Vbe multiplier …………………………………………………………………… 56

DC operating point ………………………………………………………………. 57

Differential input pair …………………………………………………………….. 57

Voltage amplifier stage VAS …………………………………………………….. 58

Output stage …………………………………………………………………….... 59

Slew rate considerations …………………………………………………………. 61

4

Gate and short circuit protections ………………………………………………. 62

Output Zobel network ………………………………………………….………... 63

Negative feedback ……………………………………………………………….. 64

Open loop gain …………………………………………………………………... 65

Stability ………………………………………………………………………….. 67

Miller compensation …………………………………………………………….. 68

Transitional Miller compensation ……………………………………………….. 68

DC servo ……………………………………………………………………….... 70

Amplifier simulations …………………………………………………………… 72

Frequency response ………………………………………………………….... 72

Distortion ……………………………………………………………………… 73

Square wave response ……………………………………………………….... 74

Signal to noise ratio SNR ……………………………………………………... 74

Damping factor and output impedance …………………………………………75

Open loop gain and phase margin …………………………………………….. 75

Output stage considerations ………………………………………………………. 76

Efficiency ………………………………………………………………………. 77

Thermal considerations ………………………………………………………… 77

Input filters ……………………………………………………………………….. 78

Power supply ………………………………………………………. 79

Power supply considerations …………………………………………………….. 79

IPS and VAS power supply filter ………………………………………………... 79

Microcontroller ........................................................................................................... 80

DC protection........................................................................................................... 80

5

Over-temperature protection ................................................................................... 80

Bar-graph meter ....................................................................................................... 81

PIC source code and flow chart ............................................................................... 83

SYSTEM SCHEMATICS AND PCBs ………………………………....................... 96

Preamplifier and crossover PCBs ………………………………………………... 96

Preamplifier and crossover schematics ………………………………………….. 97

Amplifier schematic …………………………………………………………….…. 98

Amplifier PCBs …………………………………………………………………... 99

Power supply schematic……………………………………………………………101

Power supply PCB …………………………………………………………………102

Relays schematic …………………………………………………………………..104

Relay PCB ………………………………………………………………………... 105

Microcontroller schematic ………………………………………………………...106

Microcontroller PCB ………………………………………………………………107

Final considerations …………………………………………………………………..108

6

ABOUT THE AUTHOR

My name is Davide Lucchi, I am eighteen years old and I am from Italy. I have never studied electronic at school but I have always been into because of my father. My father in the 1980s started buying electronic kits and books with a lot of projects inside so buying also a lot of different components like resistors, capacitors, transistors and ICs like the famous series 74xx and 40xx. I have been lucky because I found a lot of components but I did not know how to use them in the right way and especially how I could make something projected by me rather than coping something published on those books and see it working without knowing why. My father is not an engineer and he has never worked in the electronic field so he does not know a lot about theory, so I decided to find a good book to start from and the “Sedra/Smith Microelectronic circuits 6th edition” came into my hands. The book at first has been tough because basic things are not explained but it give me a vision of modern electronic, from basic devices like operational amplifiers, diodes and transistor to much more complex circuits like IC amplifiers most common configurations, filters, oscillators and feedback concepts. While studying the book I decided that a good project could have been an amplifier, so I looked out to find good books about the topic, I found “designing audio power amplifiers” written by Bob Cordell and “audio power amplifier design handbook” written by Douglas Self. What I learned from the Sedra/Smith give me the knowledge to understand what the other two books do not explain for example the method to determine the output resistance of a cascode amplifier and its transconductance. All this began on January 2012 and on August I had built the first amplifier, which fortunately worked at the first time. After that I decided to improve the project in particular I had a pair of woofers and tweeters so all the project started from there. I built the preamplifier and crossover using the books “small signal audio design” and “the design of active crossovers” both written by Douglas Self. The preamplifier as you can check is the same of the book I only changed some components while the crossover has been projected by me. Considering what I have been able to do in this past year I am very happy because I have built a system that sounds good and I did it without having any experience. I built the project using as much as possible the components my father bought just to make the project cheaper, so buying only what was needed.

To see the amplifier working watch this video on youtube:

The system is not completed yet, but only one channel so in the video there are the preamplifier with crossover inside the metal box, used to reduce noise, and two power amplifiers one connected to the tweeter and the other to the woofer and the loudspeaker enclosure.

I want to thank the authors of the books I named and the users of diyaudio.com forum especially the ones who helped me with the loudspeaker enclosure design. You can mail me at: davide.lucchi94@gmail.com

Lucchi Davide

03/03/2013 Italy

7

DESIGNING A COMPLETE HI-FI SYSTEM

This project deals with the design of a complete HI-FI system that includes for each channel a preamplifier, an active crossover and two power amplifiers in a bi-amping system. The preamplifiers cover functions like volume control, tone control and balance control, the active crossover is a Linkwitz-Riley type which splits the audio frequency spectrum into two bands which then are amplified and applied to the loudspeakers. The total power of the system is around 120 Wrms. Figure 1 shows the block diagram of the system.

Figure 1.

8

THE PREAMPLIFIER

Figure 3, preamplifier circuit.

C12

1µR

1247k

R16

470C

11

270n

Rp9

10k

Rp10

10k

R10

680

R111k

C6

4.7n

47KR

6R

72.2k

R8

1.8k

Rp8

10k

R17

470

R9

100k

C9

10µ

R5

100k

C5

470n

C7

10µ

C8

220µ

R15

4.7k

Rp14

10k

Rp13

10k

Rp11

10k

Rp12

10k

R14

4.7k

R18

560C

13

10n

C18

220µ

R2

470kR

31.8k

Rp1

10k

Rp2

10k

R4

1.8k

C3

220µ

C4

220µ

C1

470n

R1

100C

2

100p

V715V815

Rp7

10k

C10

10µ

U4

ne5532U

7

ne5532

U8

ne5532U

9

ne5532

U1

ne5532

U2

ne5532

U3

ne5532

R20

680

R21

4.7k

Rp16

1k

Rp15

18k

C14

22µ

C15

100p

R19

22k

C16

220µR

2222k R

23

100

U5

ne5532

U6

ne5532

R24

100k

C17

220µ

+15 -15

+15-15

+15-15

+15 -15

+15-15

+15-15

vin

+15 -15

+15-15

+15

+15

-15

-15

vout

Vin

9

The preamplifier is the first stage of the system and also the first stage the signal meets. The role of the preamplifier is, as the word says, to amplify the signal and it must cover functions like balance control between the two channels, tone control for treble and bass frequencies and volume control. All these things are covered in the preamplifier because it is simpler to implement these functions in a small signal stage, rather than making them when the signal has reached a considerable amplitude, in fact for this reason the volume control is the last stage of the preamplifier, and also it is economic because the power of the signal is low so it is possible to use normal components. Another important reason to work the signal at this stage is to keep distortion as small as possible which would be impossible with high amplitude signals. The preamplifier so must produce an output signal as much as possible distortion free and noise free. Figure 2 shows the block diagram of the preamplifier. This preamplifier is the one given by Douglas Self in his book “small signal audio design”, but I made some changes to adapt it to my design.

Figure 2.

THE BALANCE CONTROL

Figure 4, balance control circuit. The function of the balance control is to move the sound image from one channel to the other, which is useful to adapt the sound to the type of room. In order to move the sound image it is not necessary to attenuate extremely one channel while amplifying the other but is sufficient to leave one channel at 0dB while amplifying the other of 6 dB. The balance function in this preamplifier works in this way: When the potentiometer is left in its center position the signals of the two channels are not amplified (0 dB); When the potentiometer is turned full left or right it will move the sound

10

image from one channel to the other by amplifying one channel of 6 dB and leaving the other at its normal level ( 0 dB). To avoid noise when the potentiometer is turned it is important to do not allow DC to circulate through it, so coupling capacitors are used, these capacitors are also necessary to keep DC gain equal to unity. The input filter is where the input signal is connected so it must provide high input impedance, thus avoiding overloading of the source signal. Other functions of this filter are DC block, that is why it presents a high pass first order network, and attenuate high frequency signal to prevent the circuit from instability. The high pass network is made by C1, R1, R2 and the input impedance of the operational amplifier (op. amp.). The input impedance is very high so making a little change in the calculated frequency so it can be neglected . To calculate the -3dB frequency we need to know the effective resistance that C1 sees which is equal to the series combination of R1 and R2. This network is a first order filter so we have to find the transfer function T of the circuit. T can be calculated considering the resistors and capacitors as impedances in the domain of the complex variable s, so the impedance of a resistor equals the value of the resistor while that of a capacitor is equal to:

where s=jω and ω=2πf

The output voltage can be calculated applying the voltage divider rule so:

= 1 2

11 1 2

considering that R2>>R1

Thus = =

The general transfer function of a first order high pass network is:

0

where a is the high frequency gain and 0 is the corner frequency, that is the frequency at which the gain is 3dB below its high frequency value.

So 0 11 2 thus

With the values shown f = 0.72 Hz.

CR1 is also called the time constant of the network

The second filter in the input network is a first order low-pass filter whose function is to attenuate high frequency signals to avoid instability for example EMI interferences. This filter is formed by R1, R2, C2. As before we have to find the effective resistance that the capacitor sees which is equal to the parallel combinations of R1 and R2.

11

Applying the voltage divider rule we find that:

=

Considering that R1<<R2 the parallel combination is ≈ R1.

=

Thus = =

The general transfer function of a first order low pass network is:

10

Where a is the low frequency gain.

So 0 12 1 thus

With the values shown f = 15.9 MHz.

HOW THE BALANCE CONTROL WORKS

This circuit works by modifying the gain of the non-inverting stage, accordingly to the position of the potentiometer. In the normal non inverting configuration the gain is equal to 1+R2/R1. In this configuration the gain is modified varying the value of R2 and R1. Dividing the potentiometer into two resistors Rp1 and Rp2, R2 is equal to R3 in parallel with Rp1, while R1 is equal to R4 in series with Rp2. The two coupling capacitors can be neglected because their function is to block DC, their poles are at very low frequency, so the transfer function becomes:

= || 1 = +1

Now is possible to calculate the gain of the circuit considering the potentiometer at its center position or full turned in one direction:

Center position gain = 1.129 V/V = 20 * log 1.129 = 1.05 dB

Turned full left gain= 1.92 V/V = 5.67 dB

Turned full right gain= 1 V/V = 0 dB

12

NOISE

The noise is present in every circuit and it is caused by different devices, in this circuit the noise is contributed principally by resistors and the transistors inside the NE5532 op. amp. and it is called white noise. The noise contributed by capacitors is very low because they are ideally pure capacitances so they don’t have any resistance. To decrease the noise of the circuit is important to use low impedance circuits. Johnson’s noise, which is the noise produced by every resistor, is calculated with the formula:

√4

Where:

k is the Boltzmann’s constant 1.380662*10^-23;

T is temperature expressed in Kelvin;

R is the resistor value in ohms;

B is bandwidth in Hz over which the noise is calculated.

From this formula the lower the resistor is the lower the Johnson’s noise will be. The noise generated by the current is called shot noise, it is usually very low so it can be ignored. Noise in transistors is made up of Johnson’s noise generated by the base spreading resistance rbb and shot noise created by the collector current. All the noise plots have been simulated using LTspice, it is important to say that these simulation will not represent the effective noise of the circuit once it is built, because the noise simulation cannot consider power supply noise and EMI interferences.

Figure 5, noise plot.

Figure 5 shows the noise plot of the balance control simulated with LTspice, where the bandwidth is 20Hz- 20kHz, the line is the noise at the output of the balance control system, which is a total rms noise of 1.28μV.

13

DISTORTION

Distortion is another important parameter, because the signal must be as less as possible distorted by the circuit, it is usually calculated at 1kHz and at 20kHz. Distortion was simulated at 1 kHz on 10 harmonics, using a max time step of 0.48831106us, I did so because Bob Cordell in his book recommend for a FFT analysis in LTspice to use a max time step equal to the ratio of the transient time, here 8ms, and 16383. The total harmonic distortion at 1kHz is 0.000140%, figure 6 shows the FFT plot.

Figure 6, 1kHz FFT plot. The distortion at 20kHz was simulated considering a transient time of 400us and is 0.000570%. Figure 7 shows the FFT plot, done on the last 200us.

.

Figure 7, 20kHz FFT plot.

14

THE TREBLE CONTROL

Figure 8, treble circuit.

The function of the treble control is to attenuate or amplify high frequency signals, also allowing the user to change the cut-off frequency which is the frequency over which the treble control acts. The treble control is made by an input filter, which is a first order high pass, whose function is to block DC then there is a buffer used in order to do not affect the operation of the next stage of the circuit. The next stage is where the cut-off frequency is established, it is as before a high pass first order network but here the resistance that C6 sees is no longer equal to R6. The circuit after R6 makes use of the bootstrapping principle, thus varying the effective resistance Re, that the signal sees after R6, this resistance then is in parallel with R6 and this parallel combination is the resistance that C6 sees.

The -3dB frequency of the first filter is:

3.38

THE BOOTSTRAPPING PRINCIPLE

The bootstrapping principle is used in unity gain stages in order to increase the input impedance of the stage by using positive feedback. Consider a unity gain stage with a resistor connected between the non-inverting input and the output, the voltage drop on the resistor is ideally zero, so no current can flow from the resistor, thus if we consider the input impedance of the op-amp infinite, the input impedance of the system is also infinite. In the real world there are no ideal components so the output voltage is slightly less than the input one, thus there is a little voltage drop on the resistor. The smaller this voltage drop is, the higher the input impedance will be.

15

HOW BOOTSTRAP MODIFY THE EQUIVALENT RESISTANCE

Figure 9. When the potentiometer is turned full right R7 is directly connected to ground so the bootstrap is not acting, making the equivalent resistance in parallel with R6 equal to R7. The resistance that C6 sees is the parallel combination of these two resistors, so now is possible to calculate the cut-off frequency.

6|| 7 2101

16.1 When the potentiometer is not turned full right the bootstrap acts and varies the equivalent resistance in parallel with R6. Considering the gain of the op. amp. to be exactly unity, the voltage v1 is equal to vout, so vs can be calculated applying the voltage divider rule, considering that R7 is in parallel with the series combination of R8 and Rp1. The two electrolytic capacitors can be neglected because their poles are at low frequencies. Writing a node equation at v1 and calculating vs leads to:

12

27 8 17 8 1

1 616

17

0

Considering v1=vout and substituting for vs in the second equation leads to:

1

1

16

Whose magnitude is:

1

1

When the potentiometer is in the central position the -3dB point is at 3140Hz; when it is turned full left the cutoff frequency is 1466Hz. So the cutoff point can be varied from 1466Hz to 16.1 kHz From the values is clear that the variation is not linear but it is highly logarithmic especially when Rp2 tend to zero.

NOISE

Figure 10, noise plot. Figure 10 shows the noise plot which has a total rms value of 1.79μV.

17

DISTORTION Total harmonic distortion at 1kHz is 0.000029%, the FFT plot is shown in figure 11. Figure 11. At 20 kHz the total harmonic distortion is 0.000573%. Figure 12 FFT plot at 20kHz.

18

BASS CONTROL Figure 13, bass control circuit.

The function of this stage is the same as that of the treble control, with the difference that it acts on low frequencies. The principle used to modify the cut-off frequency is the bootstrap which vary the value of the combination Rp2, R10 and R11. The first part of the circuit is a high-pass filter, which places a pole at very low frequency to block DC. The corner frequency of this filter is:

0.159

The buffer after the filter is used in order to do not affect the operation of the other part of the circuit. The combination of Rp1, Rp2, R10 and R11 makes the resistance that works against C11, thus generating the cutoff point. After this circuit there is another high-pass filter to block DC current whose cut-off frequency is 3.38Hz.

19

TRANSFER FUNCTION OF THE CIRCUIT

Figure 14, bass cutoff frequency filter. The transfer function can be found by writing a node equation in V1 and Vout, considering the capacitor to be a short circuit and calling Rp the parallel combination of R10 with Rp2 gives :

10 210 2

1

11

0

1

111

11 0

Solving the two equations gives:

1111 11 11 11 1 11

Whose magnitude is:

11

11 11 11 11 1 11

20

The corner frequency is: 1.49 kHz with potentiometer turned full left; 90.8 Hz in the central position; 29.4 Hz when it is turned full right. It is worth say that when the potentiometer is turned full left Rp2 is a short circuit so the bootstrap doesn’t acts, making the resistance that C11 sees equal to Rp1 which is 20kΩ and from the values of the frequencies is possible to see the non-linear variation of the cutoff frequency.

NOISE The total rms noise is 1.079μV simulated in the bandwidth 20Hz-20kHz.

Figure 15, noise analysis.

21

DISTORTION Total harmonic distortion at 1kHz is 0.00079%.

Figure 16, FFT plot.

SUM STAGE OF TONE CONTROL

In figure 17 the sum stage is shown, it is a difference amplifier, which subtract or sum the input signal with the output of the treble and bass to amplify or attenuate those frequencies. Assuming that the circuits of the bass and treble control do not attenuate the band pass frequencies, then bass will be equal to bass.out, and also treble will be equal to treble.out, the voltage at the non-inverting input is given by the sum of the voltage divider made up by R17 and R18 for treble and R16 and R18 for bass. The gain of the circuit reaches a maximum of 11dB, and also does the attenuation. This circuit is symmetric because gain and attenuation are both 11dB. C13 with R18 make up a low-pass filter with cut-off frequency at 28.5kHz its function is to allow only audio frequencies to be amplified or attenuated. Figure 18 shows the frequency response of the circuit, where bass frequencies have been attenuated while high frequencies have been amplified. The gain and attenuation reach a maximum value of 11dB.

22

Figure 17, sum stage.

Figure 18, gain and attenuation of the circuit.

23

VOLUME CONTROL

The volume control is the last stage of the preamplifier, its function is to amplify the incoming signal, here by almost 17 dB, when is turned in one direction and to attenuate the signal when it is turned in the other direction. Figure 5 shows the volume control circuit. Figure 19 This circuit is an inverting amplifier with constant gain determined by the ratio –R21/R20, which is equal to 6.91 V/V or 16.79 dB. Here Rp2 acts by modifying the value of the voltage drop on R19 that is also the input voltage V1 of the inverting amplifier. Considering C14 to be a short circuit and neglecting C15 because its pole is at very high frequency, a node equation in V1 can be written and the output voltage is equal to:

12120

11

12

119

0

When the potentiometer is in its center position the overall gain is -2.64 dB. The maximum gain is 16.79 dB while the maximum attenuation is -87 dB. The volume variation is made logarithmic by the action of the circuit, approaching closely a 40dB variation. Figure 19 shows

24

a graph where the blue line is the transfer function of the circuit while the red line is the ideal 40dB variation. The two lines are very close. The x axis represents the position of the potentiometer.

Figure 20, ideal 40dB variation vs volume variation.

NOISE

Figure 21, noise plot. This circuit present a total rms noise of 10.21μV, simulated with the circuit giving the maximum gain of almost 17dB, which is a signal to noise ratio (SNR) of 99dBv considering a signal of 1Vrms. When the gain is unity the total noise is 4μV and with the maximum attenuation it is 1.30μV.

‐100

‐80

‐60

‐40

‐20

0

20

40

0 0,2 0,4 0,6 0,8 1

volume variation

ideal 40dB variation

25

DISTORTION The distortion analysis was performed with the volume control giving the full gain of almost 17dB, with an input signal of 300mV peak, thus giving an output signal of 2V peak. The total harmonic distortion is 0.000015%. Figure 22, FFT plot at 1kHz. Distortion at 20kHz is 0.00136%, the second harmonic is down of -111dB and the third of -94dB.

Figure 23, FFT plot at 20kHz.

26

PERFORMANCE OF THE PREAMPLIFIER

The overall noise of the circuit is 32.2μV which gives a signal to noise ratio of 93dB considering a signal of 1.5V rms. Figure 24, noise plot of the entire preamplifier Overall distortion at 1kHz is 0.000013%, figure 23 shows the FFT plot.

Figure 25, FFT plot at 1kHz.

27

Distortion at 20kHz has a total value of 0.000172%. Figure 24 shows the FFT plot, where the second harmonic is down of -140dB and the third of -113dB.

Figure 26, FFT plot at 20kHz.

The distortion of the preamplifier is very low reaching at 20kHz a total value of 0.00017%, this performance has been possible by the use of NE5532 which is a low noise and distortion operational amplifier. The overall noise is quite high but it has been measured with the volume control set at the maximum which is almost 17dB, anyway the SNR is always greater than 90dB.

28

ACTIVE CROSSOVER

The role of the active crossover is to split the audio frequencies into two or more bands, which then will be amplified and sent to the woofer or the tweeter. Another function of the active crossover is to delay the treble frequencies to make sure that both sound waves, treble and bass, come to the ear at the same time. Another function could be equalization to adjust the response of the loudspeakers. All these features make active filters much better than passive ones also considering that a passive realization of a time delay involves high power losses and expensive passive components. Active filters use op. amp. which join high performance to a relatively low cost. The slope of the filters is very important because if it is too flat, lower frequencies of the audio spectrum can be feed into the tweeter and brake it, usually a fourth order Linkwitz-Riley filter is used with a slope of -24 dB/octave but here I decided to use a second order Linkwitz-Riley filter with a slope of -12 dB/octave, which has a good performance. In second order filters and higher orders there is a parameter Q, that defines the flatness of the filter response. The flattest response is obtained when Q=0.707 which is 1/√2. Another important parameter is how the two filtered frequencies sum. In fact when the two separate bands are feed into the woofer and the tweeter then the sound waves produced by each loudspeaker will sum in air. The two signals in this type of filter are 180° phase shifted so if they are summed a deep notch will be obtained at the crossover frequency so to avoid it one of the two filters must be phase inverted, in this way the signals sum completely flat and the maximum phase of the output signal is -180°. Second order Linkwitz- Riley filters have Q=0.5. In this project the crossover must divide the audio spectrum into two bands where the crossover frequency is set at 2.5 kHz where the gain is down of 6 dB.

29

Crossover circuit.

C25

22nC

24

22n R32

82k

R29

82k

V315V415

C27

22n

C26

22n

R3482k

R353k

R2668k

R2568k

C20

170n

C19

170nC

23

1n

R28

2.2k

R27

2.2kC

22

1nU2 ne5532

U1 ne5532

U4ne5532

U3ne5532

C30

10n

C29

10n

R44

2.4kR42

9.1k

R46

1.5k

R48

4.7K

R47

4.7K

R37

1k

R38

1kewe

ne5532

wew

ne5532

U5ne5532

C32

10n

C31

10n

R52

10k

R50

910

R54

47k

R56

4.7K

R55

4.7K

U6ne5532

U9ne5532

C28

10nR402.2k

R3915k

R41

2k

R43

16kR45

330k

R49

62k

R51

4.3k

R53

4.3k

C21

1n

R30

3k

R31

3k

R3682k

R333k

R25568k

v+v-

v+v-

v+v-

V+ V-

V-V+

gvout

v+v-

V+V-

V+V-

v+v-

V+V-

Vout-treble

Vin

Vout-bass

30

THE BANDWIDTH DEFINITION FILTER

This filter sets the bandwidth of the crossover. It is made up of a high-pass filter which block DC and also very bass frequencies up to 20 Hz and a low-pass filter that blocks frequencies higher than 50 kHz. These two filters are second order Butterworth filters with a Q=0.707, thus obtaining the flattest response.

HIGH-PASS SECTION

Figure 27, 2nd order Butterworth high-pass filter. To analyze the high-pass filter is necessary to find its transfer function. Applying kirchhoff’s first law at node V1 and considering the op.amp. to be ideal, input impedance infinite and output impedance equal to 0, we can apply the voltage divider rule at Vs to obtain:

1 19 1 20 0

1

In these two equations we can consider Vs=Vout, actually they are not identical because the gain of the buffer is slightly less than unity but the error made is very little, substituting for V1 in the first equation lead to:

31

The general transfer function of a high-pass second order filter is:

Where a is the high frequency gain, in our case 1. Dividing the transfer function by 19, multiplying by s/s, summing the terms in s and considering the two capacitors to be equal leads to:

From this function:

0 0 2 √

0

With the components shown Q=0.707 and f=19.48 Hz. To plot the transfer function for physical frequencies, s must be substituted with jω, so the transfer function becomes:

Considering that = - 1:

Now is possible to find the magnitude of the transfer function which in a general function is defined as:

| | So:

| |

32

To have the gain expressed in decibel:

20 log

Figure 28 shows the Bode plot of the circuit simulated using LTspice, the marked line is the magnitude while the dotted line is the phase angle, the gain is -3 dB down at 19.55 Hz and the phase is 89.78°.

Figure 28, magnitude and phase plot.

This filter is a second order high-pass filter, which means that it has two zeroes and two poles. In an asymptotic Bode plot a zero produces an increase in the gain at a rate of 20dB/decade or 6 dB/octave, while a pole causes a decrease in gain at a rate of -20dB/decade or -6dB/octave. In the phase angle plot a zero at ω=0 causes a constant phase shift of +90° while a pole causes a phase shift of -90°. When a zero is not at the origin it will cause no effect on phase for frequencies much lower than the zero frequency, at the zero frequency the phase will be +45° and at much higher frequency it will reach +90°, for the poles the behavior is the same but the phases are negative. On the s plane the two zeroes are placed at ω=0, while the two poles are complex and conjugate and have negative real parts. The fact that the two zeroes are at the origins explains why this filter doesn’t allow DC to pass through it and also explains the phase angle, because each zero gives +90° so a total phase shift of +180°. As the frequency increases the phase shift caused by the two poles subtract from the initial 180° and at high frequency the phase tend to 0°. It is very important that the poles have negative real parts because it will tell if a circuit is stable or not. When the poles are in the left half of the s plane if a oscillation starts it will decay exponentially, if the poles are placed on the jω axis the oscillations will be sustained and finally if they are on the right half plane the oscillations will grow

exponentialshown belo

lly, the lattow.

er behaviorr is used inn oscillators to start oscillations. TThese relatiionships are

33

e

34

NOISE

Figure 29, noise plot.

Figure 29 shows the noise of the circuit, the black line is the noise at the output node, with a total rms value of 963.18nV, while the other two curves show the noise generated by each resistance and it can be seen that due to the high value of these resistors, the noise generated is principally Johnson’s noise and is the cause of the noise in the lower frequencies bandwidth. With the value of the total noise is possible to calculate the signal to noise ratio which is the ratio of the signal to the noise value. Considering that the maximum value of the signal that goes through the crossover is about 1-1.5V rms, the signal to noise ratio is:

.

. 1557341 which is 123dB below 1.5V rms

35

DISTORTION

Figure 30 shows the distortion which at 1kHz is 0.000014%, the second harmonic is down of -140dB.

Figure 30, FFT plot at 1kHz.

Figure 31 shows distortion at 20kHz which is 0.000223%, the second harmonic is down of -117dB.

Figure 31, FFT plot at 20kHz.

36

THE LOWPASS SECTION

Figure 32, 2nd order Butterworth low-pass filter.

To analyze the low pass filter the process is exactly the same as before so:

1 21 0

1

122

28122

Considering Vs equal to Vout, the two resistors equal, substituting in the first equation for V1 and rearranging the terms leads to:

The general transfer function of a low pass second order filter is:

Where the DC gain is in our case 1.

From this function we have:

0 0 2 √

37

0

With the components shown Q=0.707 and f=51.18 kHz, at 20 kHz the gain is down of about 100 mdB. Now to plot the transfer function the magnitude must be calculated, substituting s=jω and remembering that j^2=-1 gives:

20 log

Figure 33, magnitude and phase plot. From figure 33 which is the simulation of the circuit, the gain is down of 3dB at 51.15kHz and the phase is -90.47°. A low-pass filter has two zeroes and two poles but here the zeroes are at ω=∞ thus at the origin there will be no phase shift, as frequency increases the two poles will start cause phase shift both adding -90° thus giving a total phase shift of -180°. When low resistor values are used is important to verify the input impedance of the system in the worst case. Here the worst case is when ω tend to infinity so the two capacitors act as short circuit, thus the input impedance becomes equal to R1 which is 2200Ω.

38

NOISE

The noise of the circuit can be simulated with LTspice, setting the bandwidth from 20Hz to 20kHz gives a total rms noise of 1.649μV. The signal to noise ratio is:

.

. 909642 which is 119dB below 1.5V rms.

Figure 34, noise plot.

DISTORTION

The distortion at 1kHz is 0.000015%, figure 35 shows the FFT plot where the second harmonic is -139dB down.

Figure 35, FFT at 1kHz.

39

The distortion at 20kHz is 0.000556%, figure 36 shows the FFT analysis where the second harmonics is at -109 dB and the third at -145 dB.

Figure 36, FFT plot at 20kHz.

LINKWITZ-RILEY CROSSOVER FILTERS

The cut-off frequency of this filters are set at 2.5 kHz which is the recommended crossover frequency of the tweeter that will receive the amplified signal from the high-pass filter through an amplifier while the other signal will be sent to a woofer with a bandwidth up to 4 kHz. This filter is a Linkwitz-Riley type where Q = 0.5 and at the crossover frequency the gain is down of 6 dB. The two signals have opposite phases, in the low pass the phase goes from 0 to -180°, while in the high pass it goes from 0 to +180°. This characteristic means that if the two signals are directly summed the response will exhibit a deep notch at the crossover frequency. To make the response flat one of the two lines must be phase inverted giving a flat response and a maximum phase shift of -180°. The phase inversion is performed by the use of an inverting time delay circuit, which have also the task of delay high frequency signals to let bass and treble audio waves reach the ear at the same time.

40

LOWPASS FILTER

Figure 37, 2nd order Linkwitz-Riley low-pass filter.

The analysis of the circuit is the same as the low-pass filter analyzed before so:

√

With the components shown Q=0.5 and f= 2.49 kHz.

The magnitude is:

Figure 38 shows the magnitude and phase plot, as before this filter presents two zeroes at ω=∞ and two poles. The poles at frequencies much lower than that of the poles, don’t introduce any phase shift but as frequency increases each pole gives -90° of phase shift thus causing a total phase shift of -180°. Here the gain is down of 6dB at the crossover frequency which is 2.5kHz. The minimum value of the input impedance is when ω tend to ∞, and it reaches 3.1kΩ.

41

Figure 38, magnitude and phase plot.

NOISE

Figure 39, noise plot.

Total rms noise is 1.21μV, thus the signal to noise ratio is 121dB calculated considering a maximum signal level of 1.5Vrms. From the simulation is possible to see that around the crossover frequency the noise starts to decrease, this is so because the filter acts not only on the audio signal but also to all other signals that pass through it, thus it attenuates not only the audio frequencies but also the noise.

42

DISTORTION

The function of this filter is to preserve only frequencies lower than 2.5kHz and attenuate higher frequencies, so the distortion analysis can be done only on 1kHz. The distortion at 1kHz is 0.000019%, the second harmonic is down of -138dB and all the others are down of at least 180dB.

Figure 40, FFT at 1kHz.

HIGHPASS FILTER

This filter is a second order Linkwitz-Riley with cutoff frequency set at 2.5 kHz and Q=0.5, its function is to take the signal that come from the bandwidth definition filter and let only high frequencies reach the output.

Figure 41, 2nd order Linkwitz-Riley high-pass filter.

43

The analysis is the same as the high-pass filter analyzed before thus:

√

With the components shown Q=0.5 and f= 2.49 kHz. The magnitude is:

| |

Figure 42, magnitude and phase plot. Figure 42 shows the gain and the phase angle plots, where the gain is the marked line while the phase is the dotted line. At the cutoff frequency 2.5 kHz the gain is down by 6 dB and the phase is 90°. The two zeroes at the origin cause each a phase shift of 90° thus the initial phase shift is 180°, as frequencies increases, the phase shift caused by the poles subtract from the 180° reaching 0°. Minimum input impedance reaches 3.1kΩ at high frequency where the two capacitors act as short circuits.

44

NOISE

Figure 43, noise plot.

The noise in this filter is principally present in high frequencies because low frequencies are attenuated by the filter, it has a total rms value of 1.28μV. The signal to noise ratio is 121dB.

DISTORTION

This is a highpass filter so frequencies lower than 2.5kHz are attenuated, thus there is no need to see distortion at 1kHz. Distortion at 20 kHz is 0.000290%, from figure 44 is possible to see that the second harmonic is down of -115db and the third of -151dB.

Figure 44, FFT plot at 20kHz.

45

THE TIME DELAY CIRCUIT

The last part of the circuit is a 5th order all-pass filter, which is a filter that pass the whole band with a constant gain of 0dB but introducing a time delay. This filter is made up of two second order all-pass filters and a first order inverting all-pass filter. Before analyzing the circuits is important to calculate the required time delay. This delay is required because the two sound waves do not come from the same loudspeaker so they travel different path to reach the ear. To calculate the delay is necessary to know the dimension of the loudspeakers enclosure and to assume a listening point. Figure 45 shows the principal dimensions.

Figure 45, loudspeakers distances, where all dimensions are expressed in mm. From figure 45 is possible to see that I choose a listening point which is in line with the tweeter at a distance of 5 meters or about 16.5 feet. To calculate the delay is necessary to know the distance between the point where the air-wave is emitted, here I choose the point where the magnet behind the loudspeaker is joint to the cone and the distance between the centers. The distance x can be calculated applying the Pythagoras theorem to the triangle ABC thus:

181 5045 5048

Now is possible to calculate the difference between the bass path and the treble path which is:

5048 5000 48

Considering that the speed of sound in air is 343.2 m/s, the time delay is:

343.20.048343.2

140

46

The value calculated means that the bass sound wave reaches the ear 140μs after the tweeter wave, thus if the tweeter wave is delayed of this time, both waves will reach the ear at the same time. It is worth say that the time delay is not a perfect value because if the listening point changes also the delay does and also we have two ears not one so it is not possible to calculate a delay that will work with every listening point or room. The time delay function is realized using an all-pass filter, which is a filter that has a flat gain over its bandwidth and a phase that changes linearly with frequency, thus adding a delay to the signal. In an all-pass circuit, the delay is initially flat but as frequency rises, the delay tend to 0. It is important that the delay is present until a frequency where the bass wave is enough attenuated so the delay loss is not audible. The all-pass filters have been designed using a note released by Texas Instrument found on the Internet, where there were all the all-pass coefficients to make the filter works. This is the link of the note: http://www.ti.com/lit/an/slod006b/slod006b.pdf The first thing to do to design the filters is to choose a frequency and calculate the required order of the filter. With a frequency of 10kHz and a delay of 140μs Tgro is:

10000 140 10 1.4

The exact value of Tgro for a 5th order filter is 1.506 which gives a frequency of:

1.506140 10

10757

The all-pass coefficients for a 5th order filters are:

Number of filter a b / Tgro 1 1.2974 -------- -------- 1.506 2 2.2224 1.5685 3.1489 3 1.2116 1.2330 1.1905

Figure 46, all-pass filter.

47

Figure 46 shows the all-pass filters with the resistor value calculated and the capacitors assumed.

To have a flat summation of the Linkwitz-Riley filters outputs one of the two signals must be phase inverted. Here the treble filter is inverted using an inverting first order all-pass, then the 2nd order filters are also inverting thus the output is equal to the input because the gain is flat at 0dB but 180° phase shifted.

First order all-pass filter:

352 27

Second order filter:

364 28

3728

3840

Consider also that C28=C29 and R39=R40.

Figure 47, gain and delay plot of the overall all-pass filter. Figure 47 shows that the gain is flat, having a peak of about 50mdB but it also shows how the delay changes as frequency increases, in fact the required delay of 140μs lasts until 6 kHz, then it starts decreasing as frequency rises, reaching the 80% of its value at 9.7 kHz. Now because of the inversion of the first order all-pass filter, when the treble and bass waves sum in air there will be a flat summation. The resistor values calculated so far are not commercial thus it is needed to find a combination of commercial values that is the nearest to the values calculated. When designing is better to assume the

48

capacitors and then calculate the resistors rather than the opposite, because commercial capacitor values are less than resistors ones and also because they are more expensive than resistors. Precision values for resistors and capacitor are necessary to have the required response once the system is built, especially when talking about high order filters where a little change in one value can completely change the overall response. The note in fact says that the sensitivity of the 2nd order filters used here is on the order ±0.5%/% which is low if only one filter is used but with high order filters the sensitivity increases. To find the best parallel combination which gives the required resistance I made a DOS software write in C which can be compiled with any compiler for example DevC++. This software at first asks if you want to make it find the combination knowing only the required resistance or if you want to find a resistor that combined with the one known gives the required resistance. After selecting the modality it asks for the maximum percentage variation that the resulting resistance can have from the required one, finally it doesn’t take into account that real resistors have a tolerance thus the lower the tolerance the better the result. The best thing is to use 0.1% resistors and ceramic capacitors which are both expensive. This is the source code ready to be compiled: /* ******************************************************************************* * * * PARALLEL RESISTOR COMBINATION FINDER * * * ******************************************************************************* */ #include <stdio.h> #include <stdlib.h> int main(int argc, char *argv[]) // E12 RESISTORS SERIES float resistorsE12[]=1,10,100,1000,10000,100000,1000000,1.2,12,120,1200,12000,120000, 1200000,1.5,15,150,1500,15000,150000,1500000,1.8,18,180,1800,18000, 180000,1800000,2.2,22,220,2200,22000,220000,2200000,2.7,27,270,2700, 27000,270000,2700000,3.3,33,330,3300,33000,330000,3300000,3.9,39,390, 3900,39000,390000,3900000,4.7,47,470,4700,47000,470000,4700000,5.6,56, 560,5600,56000,560000,5600000,6.8,68,680,6800,68000,680000,6800000,8.2, 82,820,8200,82000,820000,8200000,10000000; // E24 RESISTORS SERIES float resistorsE24[]=1,1.1,1.2,1.3,1.5,1.6,1.8,2,2.2,2.4,2.7,3,3.3,3.6,3.9,4.3,4.7,5.1,5.6, 6.2,6.8,7.5,8.2,9.1,10,11,12,13,15,16,18,20,22,24,27,30,33,36,39,43,47,51,56,62,68,75,82,91,

49

100,110,120,130,150,160,180,200,220,240,270,300,330,360,390,430,470,510,560,620,680,750,820,910, 1000,1100,1200,1300,1500,1600,1800,2000,2200,2400,2700,3000,3300,3600,3900,4300,4700,5100,5600, 6200,6800,7500,8200,9100,10000,11000,12000,13000,15000,16000,18000,20000,22000,24000,27000,30000,33000, 36000,39000,43000,47000,51000,56000,62000,68000,75000,82000,91000,100000,110000,120000,130000, 150000,160000,180000,200000,220000,240000,270000,300000,330000,360000,390000,430000,470000,510000, 560000,620000,680000,750000,820000,910000,1000000,1100000,1200000,1300000,1500000,1600000,1800000, 2000000,2200000,2400000,2700000,3000000,3300000,3600000,3900000,4300000,4700000,5100000,5600000, 6200000,6800000,7500000,8200000,9100000,10000000,11000000,12000000,13000000,15000000,16000000, 18000000,20000000,22000000,24000000,27000000,30000000,33000000,36000000,39000000,43000000, 47000000,51000000,56000000,62000000,68000000,75000000,82000000,91000000; float Rout,R1,R2,delta,p,R2min,R2max,E12value,E24value, RoutfinalE24,RoutfinalE12,deltaRoutE12,deltaRoutE24,Routfinal,deltaRout; int arrayE12=0,arrayE24=0; char dec,rout; printf("PARALLEL RESISTOR COMBINATION FINDER\n"); printf("\n"); printf("TYPE B TO FIND THE BEST COMBINATION OF BOTH R1 AND R2 OR R TO TYPE THE VALUE OF R1\n"); printf("\n"); scanf("%c",&dec); if (dec=='R')

50

printf("\n"); printf("percentage variation from nominal\n"); printf("\n"); scanf("%f",&p); printf("\n"); printf("type the value of Rout\n"); // ASK FOR ROUT printf("\n"); scanf("%f",&Rout); // SCAN ROUT AND ADRESS THE VALUE TO ROUT printf("\n"); printf("type the value of R1\n"); printf("\n"); scanf("%f",&R1); printf("\n"); R2=(Rout*R1)/(R1-Rout); // CALCULATE TEORETICAL R2 printf("R2 calculated=%f\n",R2); // SHOW CALCULATED R2 printf("\n"); // EXTREME VALUES FOR R2 delta=0.2; R2min=(R2-(R2*delta)); R2max=(R2+(R2*delta)); printf("delta=%f\n",delta); printf("\n"); printf("R2min=%f\n",R2min); printf("\n"); printf("R2max=%f\n",R2max); printf("\n"); printf("\n"); // E12 values for (arrayE12=0;arrayE12<=85;arrayE12++) E12value=resistorsE12[arrayE12]; if(E12value>=R2min && E12value<=R2max) RoutfinalE12=(E12value*R1)/(E12value+R1); deltaRoutE12=((RoutfinalE12/Rout)-1)*100; if(deltaRoutE12>=-p && deltaRoutE12<=p)

51

printf("R2E12commercial=%f\n",E12value); printf("\n"); printf("RoutfinalE12=%f\n",RoutfinalE12); printf("\n"); printf("deltaRoutE12=%f\n",deltaRoutE12); printf("\n"); // E24 values for (arrayE24=0;arrayE24<=193;arrayE24++) E24value=resistorsE24[arrayE24]; if(E24value>=R2min && E24value<=R2max) RoutfinalE24=(E24value*R1)/(E24value+R1); deltaRoutE24=((RoutfinalE24/Rout)-1)*100; if(deltaRoutE24>=-p && deltaRoutE24<=p) printf("R2E24commercial=%f\n",E24value); printf("\n"); printf("RoutfinalE24=%f\n",RoutfinalE24); printf("\n"); printf("deltaRoutE24=%f\n",deltaRoutE24); printf("\n"); if (dec=='B') printf("\n"); printf("percentage variation from nominal\n"); printf("\n"); scanf("%f",&p); printf("\n"); printf("type the value of Rout\n"); // ASK FOR ROUT printf("\n"); scanf("%f",&Rout); // SCAN ROUT AND ADRESS THE VALUE TO ROUT printf("\n");

52

for (arrayE12=0;arrayE12<=85;arrayE12++) E12value=resistorsE12[arrayE12]; for (arrayE24=0;arrayE24<=193;arrayE24++) E24value=resistorsE24[arrayE24]; Routfinal=(E12value*E24value)/(E12value+E24value); deltaRout=((Routfinal/Rout)-1)*100; if(deltaRout>=-p && deltaRout<=p) printf("R2commercial=%f\n",E12value); printf("\n"); printf("R1commercial=%f\n",E24value); printf("\n"); printf("Routfinal=%f\n",Routfinal); printf("\n"); printf("deltaRout=%f\n",deltaRout); printf("\n"); system("PAUSE"); return 0; The resulting schematic is shown at page 29.

53

POWER AMPLIFIERS

The power amplifier is the circuit that drives the loudspeakers, its purpose is to amplify the signal not only increasing its amplitude but also giving it more power. In this project four power amplifiers are used, each driving its own loudspeaker, all amplifiers must be capable of driving with safe margins 4Ω loads. The power amplifiers used are made using discrete circuits and they are DC coupled amplifiers, which means that they do not only amplify time varying signal but also direct currents. The difficulties with DC amplifiers is to make sure that no DC voltage is present at the output, usually +/- 50mV is considered the maximum DC voltage allowed. DC coupled amplifiers differs from AC coupled ones by some aspects: AC coupled amplifiers use a single supply rail thus the output is biased at half supply voltage to have the maximum symmetrical signal swing therefore a capacitor is needed to avoid DC on the loudspeaker; DC coupled amplifiers use positive and negative supply rails so the output is biased at 0V, thus the capacitor is not needed. Output capacitor also increases the total distortion of the amplifiers not only at low frequency, where the capacitor presents high impedance, but on the whole audio bandwidth. Removing this capacitor will also remove DC protection of loudspeakers, thus a protection circuit must be used to give some DC protection.

THE POWER AMPLIFIER The power amplifier is shown in figure 48. It is made up of three stages where the first stage is a transconductance amplifier which converts the input voltage into a current signal, the second stage also called voltage amplifier stage, VAS, is a transimpedance stage which converts a current signal into a voltage signal and the last stage is a unity gain stage which increases the power of the signal. The circuit is perfectly symmetrical because the top half is equal to the bottom one, this feature reduces second order harmonics. The first two stages are inverting while the third is not so absolute phase between input and output is preserved.

THE INPUT STAGE AND THE VAS

The first two stages have to be considered together in order to calculate the operating point at which the circuit is biased. The analysis can be performed only on one half of the circuit because of its symmetry. The first stage is a differential amplifier loaded with current mirrors, in this way the noise performance and the common mode rejection ratio (CMRR) are improved. This is so because this circuit responds only to the difference between its two inputs and rejects all other common signals. If a differential amplifier is loaded with a current mirror then the current mirror acts by making the current of the two parallel halves of the circuit equal and it also increases the gain of the stage by a factor of two. Q9 is called a helper transistor and its function is to make possible the setting of the operating point of the first two stages, otherwise it will not be possible. R68 works for making the currents of the two halves of the differential pair equal, in fact when the two currents are equal no current flows through R68, but if there is a difference then some current flows through it, loading

54

Q5

2N5550

Q2

2N5401

Q6

2N5550

Q10

2N5550

Q9

2N5550

Q11

2N5550

Q13

2N5550

Q14

2N5550

Q21

2N5550

Q22

2N5550

Q19

2N5550

Q20

2N5550

Q7

2N5401

Q8

2N5401

Q3

2N5401

Q4

2N5401

Q15

2N5401

Q16

2N5401

Q17

2N5401

Q18

2N5401

R65

150

R67

150R

66680

R77

150R

79150

R78

680

R72

470

R73

470

R69

470

R70

470

R76

33kR68

33k

R83

100

R82

20k

R81

100

R80

20k

R93

60R

921k

R87

60R

861k

R90

6.8k

R89

1050

C43

47pC41

47p

R75

10k

R74

470

Q26

BD

140

M1

IRFP140

M2

IRFP9140

Q24

2N5550

Q25

BD

139

Q23

2N5401

R96

220R

952k

R102

0.68

R103

0.68

R97

100

R98

100

V130V230

C42

100p

R88

4.7k

C44

100pR

914.7k

D5

1N4002

D6

1N4002

C45

100p

R101

47

C46

100p

R99

47

R57

0.2R

58330

R59

16k

R60

10

D1

1N4002

D2

1N4002

1µ C35

C34

100µ

C33

470µQ

12N

5550

R61

0.2

R62

330

R63

16kR

64

10

C38

1µ

C36

100µ

C37

470µ

D3

1N4002

D4

1N4002

Q12

2N5401

R71

10k

U1

LT1001C

40

2.2µ

R85

330kR

84330k

C39

2.2µV312V412

R110

10k

U2

Q5006L4

R94

10k

U3

4N25

R100

1k

vout

Vin

55

differentially the circuit and reducing the gain. Real components have tolerances that make them not all equal thus the two parts of the circuit will tend to set different currents but it cannot be so a small offset voltage will be created at the input of the amplifier. The more equal the components are, principally the transistors, the smaller the input offset voltage will be. In order to make the distortion of the amplifier as low as possible, the transistors must be operated in their linear region, which is usually a very narrow region, to extend it degenerating resistors are used, like R69 and R70, the price paid for the linearization is a reduction in the gain of the stage. The current at the operating point is set by a circuit that acts as a constant current generator, so it must be capable of delivering to the load the set current regardless of the load resistance. The circuit is shown in figure 50. The current that flows through the load resistance is set by the value of R81, which can be calculated at first considering a base to emitter voltage drop (Vbe) equal to 0.7V, then the exact value is found with the simulator. Thus I=0.7/100= 7 mA, the final value from simulation is 6.5mA. The function of R80 is to give base current to Q16 about 2mA, to turn it on. This circuit has feedback because, if for some reasons the load current tend to change the circuit will attempt to keep it constant at the set value. To demonstrate it let’s assume that the current through Rload tend to increase, then the voltage drop on R81 will increase too thus making Q15 conduct more current, which in turn increases the voltage at the base of Q16 therefore tending to turn it off. A good current generator to be so should have a very high output impedance, in this way the load current will remain constant regardless of the load resistance and the voltage across it. The output resistance can be simulated using LTspice considering that Ro=ΔVo/ΔIo which leads to 3.5M.

Figure 50, current generator.

56

THE Vbe MULTIPLIER

Figure 51 Vbe multiplier.

The Vbe multiplier is a circuit that presents a voltage drop on it that is controlled by the ratio R90/R89 and is needed in order to turn on the output stage transistors. Considering that the final transistors in this project are MOSFETs a high voltage is needed, in fact to turn on a MOSFET a voltage of at least 3.5 - 4V is needed. Because of the tolerances on the gate-source turn on voltages, in the complete project instead of using only R89, I used a resistor in series with a potentiometer, in this way is possible to perfectly set all the currents of the output stage. The current that flows through the collectors of Q19 and Q20 is the same of the VAS which is about 8 mA, more on this later. For the Vbe multiplier in figure the voltage drop on it is equal to:

2 19089

Considering a Vbe of 0.7V gives V= 10.46V. The value found here is just a value that works with the simulator and sets the right current values, thus with real components this voltage could be either too high or too low so here comes the need for a potentiometer. Anyway once all the four amplifiers are built the voltage on each Vbe multiplier can be measured and they should be all similar, so a combination of R90 and R89 can be calculated thus saving four potentiometers. The formula comes out considering on R89 a voltage drop of 2 Vbe, then the current through it can be calculated and it can be considered equal to the current through R90, neglecting the base current of Q19, thus the voltage drop on R90 can be calculated and summed to the voltage drop on R89 to find the overall voltage drop. This circuit is also used for temperature compensation on the operating point of the output stage. The temperature coefficient of MOSFETs at low currents is positive thus as temperature rises also current does, but around 6 V the coefficient becomes negative. This

57

characteristic makes MOSFETs less prone to thermal runaway but the fact that at low currents the coefficient is negative implies the need for some protections for the devices. On the MOSFETs there will be a lot of power dissipation so increasing the junction temperature which will tend to change the current that the MOSFETs conduct, so a system that tracks the temperature change is necessary to avoid any change in the operating point. Vbe multipliers made up of only one transistor cannot be used because the temperature coefficient of Vgs of MOSFETs is -6mV/°C while that of a BJT is -2.2mV/°C, thus with a single Vbe the compensation will be too high about -14.23mV/°C. In the schematic above two transistors are used but only one will track the temperature so the compensation will be about -7mV/°C. Q20 is connected as a diode-connected-transistor, any NPN type transistor can be used but it should be in a package with the screw hole to be easily connected to the heat sink near the MOSFETs. To see how feedback works consider that when the junction temperature of a MOSFET increases also the current does, thus to maintain everything steady the voltage on the Vbe multiplier must decrease. Q20 works like a diode so an increase in temperature decreases the voltage drop on it of about 2.2 mV/°C, so the voltage drop on R89 will also decrease, decreasing the current through it and through R90 thus decreasing the overall voltage drop. This is an economic and simple way to have a thermal feedback Vbe multiplier.

THE DC OPERATING POINT

In an amplifier even when there is no signal applied the transistors must be on and they must never turn off and never enter into saturation because such things would highly increase the distortion of the amplifier. The current source of figure 50 biases the differential pair with a current of 3.25mA in each half of the circuit so making possible the calculation of the current at which the second stage is biased. Looking the circuit reveals that the voltage drop on R87 is equal to that on R67 that is

67 67 0.487 thus the current on the second stage is equal to VR67/R87 = 8.1 mA. The Vbe multiplier sets the voltage that turn on all the output stage transistor and as calculated before is equal to about 10.5V, considering a constant base to emitter voltage drop of 0.7 the voltage drop on R95 is equal to about 9.1V so the current through it is 4.55 mA, the voltage drop on R96 is 7.7V and the current is 35 mA, finally the current through the MOSFETs is around 130 mA.

THE DIFFERENTIAL PAIR

The differential pair input circuit as said before is a circuit that responds only to the difference between its two inputs and rejects all common signals. The role of the first stage is to compare the output signal with the input one, then the difference between these signals which is called error signal is the quantity amplified by the amplifier to create the output signal. The current through R69, Q7, Q10 and R65 is set by the current source and is equal to half of it thus about 3.25mA. Q10, R65, R67 and Q11 make up a current mirror which function is to increase the balance between the currents of the two vertical halves of the circuit and also it highly increases the gain of the stage. To understand what great advantages current mirrors provide consider that when using a differential pair there are two ways to take the output signal, single ended or differentially. Taking the signal single ended means that the load is connected between the output (one of the two collectors) and ground while differentially means that the load is connected between the collectors of Q7 and Q8. In the amplifier, as shown in figure 52, the output is taken single ended, which in a differential pair without current mirrors will create a loss of gain of 2 (6dB), because when a difference signal is present at

58

the inputs, Q7 will conduct a current I, while Q8 will conduct an equal but opposite current I, thus the current through the load will be equal to I. When a current mirror is used, it takes the current of Q8 and provides a replica of this current at the collector of Q10 which sum with the collector current of Q7 thus the current through the load is equal to 2I thus not creating a signal loss.

Figure 52 differential input circuit.

THE VOLTAGE AMPLIFIER STAGE

The voltage amplifier stage (VAS) figure 53, is made up of two transistors connected in a manner similar to the Darlington configuration but with the difference that the collectors of the two transistors are not joint together. The role of Q21 is to buffer the input of the VAS thus increasing the load resistance that the first stage sees. The increase in the input resistance is very important because it determines the gain of the first stage, particularly the higher it is the higher the gain of the input stage will be (see open loop gain calculation).

59

Figure 53 the VAS.

THE OUTPUT STAGE

Figure 54 shows the output stage of the amplifier, it is composed of pre-drivers Q24 - Q23, drivers Q25 - Q26 which are all connected as common collector transistors and finally the output MOSFETs. This output stage works in the AB class, thus it joints the advantages of the A class with those of the B class. An A class output stage gives the lowest distortion at the expense of high power dissipation and very low efficiency, it works by never turning off the transistors so the conduction angle is 360°. The class B highly increases efficiency but also distortion because the transistors conduct only for half cycle thus 180°, but when the signal has a small amplitude both transistors are off thus giving rise to distortion in the so called crossover region. The class AB biases the transistors so that at small voltages both transistors are on and as signal increases one of the two transistors turn-off. The configuration of output stage used biases the pre-drivers and the drivers transistors in the class A while the MOSFETs are biased in class AB, in this way there is a good deal between distortion and power dissipation. Usually in power amplifiers the output transistors are BJTs but MOSFETs have become an alternative. A big advantage is the ease of driving because MOSFETs do not have a gate current so they have infinite DC input resistance, to be turned on they only require an input current to charge and discharge the input capacitance. The fact that they do not have a beta means that they do not suffer of beta drop at high currents which makes BJTs difficult to drive at high power levels. The fT of MOSFETs is higher and it does not drop at high current so MOSFETs are faster than BJTs.

Other advantages are the absence of secondary breakdown and at high current levels a negative temperature coefficient. MOSFETs have also some disadvantages for example they require a higher

60

driving voltage to turn on, they tend to be prone to high frequency oscillations, higher price and the thin gate oxide that makes the gate has a low breakdown voltage of about 20V which can be easily exceeded therefore some protection circuits must be used. The biggest difference is about the transconductance, one of the parameters that determine the gain, which in a MOSFET is much smaller than that of a BJT, from a factor of 1/5 to 1/20 at equal currents, so making the gain of the MOSFETs less than that of the BJTs.

Figure 54 output stage.

MOSFET output pairs do not need to be biased at a precise current and usually the higher the current is the better the performance, so I chose 130mA to maintain a reasonable power dissipation when no signal is applied. The crossover distortion is present also with MOSFETs and it is a result of the change of the output impedance as the current goes through zero; the output impedance forms a voltage divider with the load resistance so determining the gain of the stage, thus if the output impedance tend to zero, the gain of the output stage tend to unity. The output impedance is the inverse of the transconductance (gm), so considering that in the crossover region both transistors are

61

in conduction, the output impedance is the inverse of the sum of the transconductances. At low currents gm is low so output impedance rises and the gain of the stage decreases. Gm doubling is a problem of BJT output stages which is controlled with emitter resistors, though MOSFETs do not suffer of this phenomenon so source resistors are not needed, here I decided to employ them because they are used to trigger the short circuit protection, more on this later. The output MOSFETs are driven by two BJT emitter followers which are then driven by other two emitter followers, this is so because the input impedance of a MOSFET is almost infinite but the input capacitance must be charged to turn on the device and to maintain a high slew rate the current needed is pretty high. Slew rate means how fast the output voltage can change in a large signal condition, the unit of measure is V/μs. For a sinusoidal waveform the slew rate is:

210

Where f is the frequency and Vpk the peak voltage of the sinusoid. The maximum power of these amplifiers will be around 50Wrms, the point of clipping, so the peak voltage is 20Vpk, thus the minimum slew rate that the amplifier must have to produce a 20kHz sine wave of 20Vpk is 2.51V/μs, which is a low value but the higher the SR of the amplifier the lower the distortion will be with high frequency signals, high quality amplifiers usually have a SR>100. The input capacitance of the MOSFET and the required slew rate will define the value of the bias current of the emitter followers that drive the output transistors as will be seen now. The input capacitances of a MOSFET are two: the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd). Cgs is bootstrapped by the output signal so its value becomes much smaller and is equal to:

The formula is found for example considering an op.amp connected as a voltage follower with a capacitor C connected between the non-inverting input and the output, which can be substituted with a capacitance that sinks an equal current of that of C, connected between input and ground. Zout is the output impedance of the amplifier while Zload is the loudspeaker impedance which is 4Ω. At the crossover point Zout is equal to the sum of the inverse of gm and the source resistors all divided by two because both transistors are conducting, thus assuming a gm of 2S, Zout becomes 0.59. From the datasheet of IRFP140N at Vds=1V i.e. near clipping, Cgs is about 1200pF which bootstrapped becomes about 155pF. The Cgd capacitance is of greater concern because it varies as the voltage between drain and gate varies and when this voltage is small it becomes high reaching even more than 1000pF, but this happens when the amplifier is near clipping. In program material the maximum voltage rate of change is not at the maximum near clipping so the slew rate performance is not very compromised. The value of this capacitance with Vgs=10V is 200pF so the input capacitance is 355pF. The bias current of the driver transistors were found to be 35mA, this is the current that charges and discharges the input capacitance so the slew rate is:

98.6

This value reveals how high the driver bias current must be to maintain a high slew rate value.

62

THE GATE PROTECTION AND SHORT CIRCUIT PROTECTION

Figure 55 shows the output stage completed with its protection circuits. The gate protection is done by diodes D5 and D6 which are called flying catch diodes, normally they are reversed biased so the circuit operates in the normal manner but if the gate voltage of one MOSFET tend to go higher than the Vbe multiplier voltage, the diodes become forward biased, limiting the gate voltage to about the Vbe multiplier voltage. The fact that they put a limit on the maximum gate to source voltage means that they also put a limit on the maximum drain current, but to avoid high currents in the case of a short circuit it is better to use a short circuit protection. The short circuit protection is made up of an opto-coupler and a TRIAC. The opto-coupler is trigged by the voltage drop on the source resistors that turn on the diode inside it which then turn on the TRIAC that short circuits the Vbe multiplier thus turning off the entire output stage. The TRIAC then will stay on until power is cycled. With the values shown the trigger current is about 10A.

Figure 55 , output stage with its protection.

63

THE ZOBEL NETWORK

Because of the high fT MOSFETs are prone to high frequency oscillations that must be controlled;

one way is to use gate stopper resistors like R97 in figure 55 which must be placed as close as possible to the gate terminal to minimize inductances but the disadvantage here is that these resistors work against the input capacitance of the MOSFET thus reducing the speed of it, creating a pole at only few megahertz. Another network used to damp oscillations is the Zobel network which is shown in figure 56 , its function is to present a minimum resistive load on the amplifier up to very high frequency. The power of resistor R104 have to be chosen carefully because in normal conditions its power dissipation will be very small, for example at 20kHz with an output signal of 18Vpk it is about 0.4W but in case of high frequency oscillations it will be much higher so this resistor is usually oversized, I used power resistors rated at 10W. From figure 56 is also possible to see that at the output there is another network formed by a resistor in parallel with an inductor, the function of the inductor is to isolate the amplifier from a capacitive load that at high frequency acts like a short-circuit while the function of the resistor is to damp out resonances of the inductor with load capacitances. Here a 2Ω resistors has been used so the amplifier will never seen a load less than 2Ω. For best sound quality the inductance should be an air coil, ferrites must be avoided because they present nonlinearities. The coil of the amplifier has a diameter of 10mm and a length of 25mm with 25 turns, so the inductance is about 2μH. The last networks are gate Zobel networks to damp out high frequency oscillations on the gate, typical values are 47Ω in series with 100pF.

Figure 56 Zobel network and output inductor.

64

NEGATIVE FEEDBACK Modern power amplifiers made use of negative feedback, which means that a part of the output signal is fed-back to the input of the amplifier and compared with the input signal, then if these signals are different the circuit acts by trying to make the output equal to the input. Amplifiers with negative feedback have an open loop gain Ao and a closed loop gain Acl. The open loop gain is the gain of the amplifier without the feedback applied and it must be as high as possible. Closed loop gain is the overall gain when the feedback is connected, the difference between open loop gain and closed loop gain is the negative feedback factor which acts to reduce distortion, reducing output impedance and increasing supply-rail rejection. Figure 57 shows a block diagram of negative feedback, where Ao is the open loop gain and β is the gain of the feedback network which is the inverse of the closed loop gain so it is less than 1. Figure 57 negative feedback blocks. The transfer function of the circuit is:

1

From the formula above if Ao is very high, then 1 can be neglected and the formula becomes:

1

The closed loop gain therefore becomes equal to the inverse of the feedback network gain which is set by some resistors allowing a precise setting of it. Besides Ao is not a known and precise value because it depends by many factors like gm which varies with collector current, output resistance of each transistor that is determined by the Early’s effect and depends on the voltage drop between collector and emitter thus varying with signal. Fortunately knowing the precise value of Ao is not necessary but the designer has to make sure that its value is very high. The value of Ao can be depicted making some approximations: _ Low power BJT hfe = 100; _ Medium power BJT hfe = 50;

65

_ Gain of a stage total collector resistancetotal emitter resistance

_ input resistance Rin total emitter resistance hfe

_ output resistance Rout ro degenerating factor

_ roVA Vce

Ic

_ degenerating factortotal emitter resistance

dynamic emitter resistance re′

_ re′VTIc

The open loop gain then is equal to the product of the gains of each of the three stages.

DETERMINE THE OPEN LOOP GAIN

For the differential input the total emitter resistance is equal to:

3.25 0.0260.00325

8 72 73 470

2 956

The total collector resistance is equal to the parallel combination of R76 and the input resistance of the VAS. The input resistance of the VAS is the total emitter resistance of Q17 times its hfe, but the total emitter resistance is the parallel combination of R92 and Q18 input resistance. Q18 input resistance is given by:

8.1 18 93 6320

17 92 || 18 863

17 88.5

Total collector resistance is equal to.

|| 76 24

First stage gain is:

2 50

The gain is doubled because of the current mirror action, that as explained before makes possible to have a single ended output without gain loss.

66

VAS gain:

First calculate ro where VA for the 2N5550 and 2N5401 is 100V, Vce is equal to Vrail= 30V and Ic=8.1mA.

16

93

19.75

316

This resistance is in parallel with Q22’s Rout which has the same value. The parallel combination then is in parallel with the input resistance of the output stage which can be calculated as follows:

25 96 11 50

24 25 || 95 1692

24 24 170

Total collector resistance is:

24 || || 82

Total emitter resistance is:

93 63.2

VAS gain is:

1297

The output stage gain is calculated as:

0.87

Zout is the output resistance that was calculated before and it is equal to 0.59 Ω, Zload is the loudspeaker impedance 4 Ω.

Open loop gain finally is the product of all gain thus:

56419 95

67

STABILITY

The transfer function of the amplifier when negative feedback is applied is:

1

The transfer function has a value that varies with frequency because of the presence of the complex variable s, looking at the denominator it is important to notice that if for some reasons the quantity Aoβ becomes negative, then negative feedback becomes positive feedback, leading to oscillations when Aoβ=-1. To see it let’s assume that Ao=1000, β=0.05 and input signal Vin=1V, so the signal, also called error signal, required by the amplifier to produce the output is Vin/Ao=0.001V therefore the input must supply 0.051V because of the signal fed back, making a gain of 1/0.051=19.60V/V. Now let’s consider β = -0.0005, the required error signal will still be 0.001V but now the input has to supply 0.5mV making a gain of 1/0.0005=2000V/V . Negative feedback has a phase of 180° while positive feedback has a phase of 0° or 360°. Negative feedback thus need a phase inversion of 180° somewhere in the loop, but in an amplifier there are multiple poles which give a phase shift of 45° at the pole frequency and 90° at much higher frequency making very simple to reach 360°, therefore if the gain is still positive sustained oscillations will occur. The concepts that define how free of instability an amplifier is are phase margin and gain margin. Phase margin defines how small is the phase around the loop than 180° when the gain becomes unity, while gain margin defines how negative is the value of the gain when the phase reaches 180°, the minimum phase margin is 45° while the gain margin is usually -6dB, these concepts are shown in figure 58 where the phase is that contributed by the poles.

Figure 58 phase and gain margin.

To make the amplifier stable negative feedback must remain negative and the only way to do it is to use a feedback compensation network. The role of this network is to create a dominant pole at a low

68

frequency that dominates the gain roll-off of the amplifier in order to guarantee stability. The simplest way to do it is by using a Miller capacitor. This capacitor is placed across the VAS as illustrated in figure 59, at low frequency it acts as an open circuit thus no current flows through it, but as frequency increases all of the signal current tend to go through the capacitor, this means that the open loop gain of the amplifier is no longer controlled by the VAS input resistance and VAS emitter resistance but by the capacitor.

Figure 59 simple Miller compensating capacitor.

The impedance of a capacitor is inversely proportional to frequency thus it decreases as frequency rises, decreasing the open loop gain at a rate of -20dB/decade. The frequency at which the open loop gain starts to roll-off is the point where the open loop gain starts to be determined only by the capacitor impedance.

The roll-off frequency can be calculated as follow:

56419

12

156419 2 32 10 956

92

The resulting plot is shown in figure 60. In the amplifier described here the compensating network is not a simple capacitor connected across the VAS but it is a more complex scheme, that was proposed by Baxandall and it is called transitional Miller compensation (TMC), it is shown in figure 61. The purpose of this network is to include the output stage in the compensating network, reducing output stage distortion. The output stage of an amplifier is the main source of distortion but also the main cause of phase shifts therefore at high frequency the inclusion of it could run the amplifier into oscillations. This compensating network solve the problem by excluding the output stage at high frequency, in fact at low frequency the impedance of R91 is much lower than that of C44 and the output stage is effectively enclosed in the network but as frequency increases the signal tend to go through C44 rather than R91 so excluding the output stage. The behavior is the same of the simple Miller capacitor where at high frequencies the value of Cm is about the value of the series combination of the two capacitors, which is 32pF that was used to calculate the roll-off frequency

69

and the gain roll-off is still -20dB/decade. The values of C43, C44 and R91 have been found using LTspice simulations with the scope of giving enough phase and gain margins to the amplifier. Figure 61 shows also R75 and R74, these resistors are the ones that set the closed loop gain of the amplifier which is equal to:

17574

22.27 26.9

Figure 60 open loop gain and closed loop gain plot.

Figure 61 TMC applied to the amplifier.

70

DC SERVO

This amplifier as all modern amplifiers is DC coupled which means that there is no capacitor between the output of the amplifier and the load so any output DC voltage will be present also on the load. Direct currents are dangerous for loudspeaker especially for tweeters which can be destroyed in less than a second under high DC voltages like the rail ones. The absence of the capacitor and the risks involved make necessary the use of a DC servo and loudspeaker protection. A DC servo is a circuit connected between the output of the amplifier and the inverting input, its function is to sense the DC voltage at the output of the amplifier and to produce a voltage that can be applied to the input of the amplifier to correct the output DC voltage and force it to be 0 Volts. This circuit can correct only little output DC voltages because, as it will be seen, its headroom is limited. To protect the loudspeakers a relay is usually used even though relays turn on time is high it is better to have one rather than hoping that the fuses will blow in a enough short time to save tweeters. Loudspeakers protections in my project are controlled by an EEPROM, a PIC which will be explained later. The closed loop gain of the amplifier as said before was set by two resistors thus the amplifier amplifies AC signals but also DC signals as well, thus a little offset at the input could become a large offset at the output. The main cause of input offset voltage are the bases currents of the BJT and here comes another advantage of the schematics used. NPN BJTs are said to sink base current while PNPs source current thus their currents have opposite sign. The input signal in this amplifier is applied to two differential pair one being NPN and the other PNP which are biased at equal collector currents thus assuming equal betas the two base currents will tend to cancel out thus reducing input offset voltage. In the real world the betas will never be equal so a little input voltage will always be present but the lower it is the less the DC servo has to work. From figure 49 the input bases are biased at 0V by resistor R71 whose value is equal to feedback resistor R75. This is not a coincidence because the difference of the currents of NPN and PNP bases will flow through this resistor developing the input offset voltage, the same will happen on the feedback side, so the same voltage drop will be present also on R75 thus reducing bases currents effects. The DC servo usually is an integrator which is connected to the output of the amplifier through a low pass filter with very low cut-off frequency, in order to sense only DC and reject all AC signals. The circuit is shown in figure 62, it is a non inverting integrator where C40 and R85 made up a low pass filter with cut-off frequency of 0.2Hz. When at the output there is a DC voltage then C39 starts to charge driving the output of the servo at a positive voltage which will be applied to the inverting input of the amplifier through R46, the amplifier then will decrease the DC output voltage. The gain of the integrator at DC is very high so it will force the output to ideally zero volt, in reality the output voltage will be forced to be equal to the input offset voltage of the op. amp. The choice of the op.amp is very important for two reasons: The servo should have a small input offset voltage; The servo is in the feedback path. The problem of small input offset is solved using JFET operational amplifier that have a very small input current. The problem of adding other circuits into the feedback path is that noise and distortion at low frequency can be fed in into the amplifier so high quality op. amp must be used. Here I used the OPA134 which is a high quality low distortion and noise audio amplifier, its input offset is about 3mV which is very good, this op.amp is a good deal between performance and cost.

71

Figure 62 DC servo.

The fact that the amplifier has a DC servo does not mean that the input offset voltage can be allowed to be of whatever value, because the servo has a clipping point, around ±14V when using ±15V rails, over which the servo is no longer able to decrease the output DC voltage. R46 is the injection resistor which injects the output voltage of the integrator into the inverting input of the amplifier. R46 works with feedback resistor R74 making an attenuation of about 22:1, thus if clipping occurs at ±14V the maximum input offset voltage that can be corrected is 0.640V. This voltage is not very high but with the input stage used here it works well because of the tendency of bases currents to cancel out. Amplifier output offset voltage was simulated with LTspice without the DC servo and it was 55mV, which is an input voltage of about 2.4mV. The DC servo thus in normal condition is not pushed to work hard. The DC servo to work properly must be insensitive to high amplitude low frequency signals, for example a 20Vpk signal at 2Hz at the output of the amplifier will produce 2Vpk a the output of the servo. High amplitude signals at frequency lower than 20Hz are always blocked by an input filter to avoid loudspeaker damage so the DC servo should work right. Figure 63 shows the frequency response of the servo where the unity gain is at 0.2Hz, lower frequency signals are amplified by the servo while others are attenuated. The slope of the frequency response is -20dB/decade. Resistor R46 is effectively in parallel with feedback resistor R74 because the output of the integrator is at 0V thus the gain of the amplifier increases.

The amplifier connected to the tweeter will process only frequencies higher than 2.5kHz thus lower frequencies are attenuated, to increase tweeter safety the corner frequency of the filter made up by R85 and C40 can be increased to 700Hz, in this way the response time of the DC servo will be decreased. Possible values are C40=22nF and R85= 10kΩ which leads to a corner frequency of 723Hz.

72

Figure 63, frequency response.

LTSPICE ANALISYS OF THE AMPLIFIER

In this part all simulations of the amplifier will be presented starting from the frequency response, distortion, noise, stability and so on.

FREQUENCY RESPONSE

Figure 54 shows the frequency response, which shows the closed loop gain of the amplifier to be about 27.3dB, the increase in gain is due to R46 which is in parallel with R74, the bandwidth of the amplifier is also shown and it is 0Hz- 337kHz. The phase increases as frequency rises reaching at 20kHz -3.8°, thus absolute phase is preserved.

Figure 64 frequency response.

73

DISTORTION

The distortion has been simulated at 1kHz and at 20kHz. 1kHz simulation was done on the first 10 harmonics while the FFT is based on the last 8 cycle of the waveform.

Figure 65 FFT plot at 1kHz.

The total harmonic distortion at 1kHz turned out to be 0.00029%, the FFT plot is shown in figure 65, where is possible to see that the second harmonic is down of -100dB, the third is at -95dB.

Distortion at 20kHz on the first 10 harmonics is 0.00073%, second harmonic is down of -82dB, third is down of -85dB while the others are all below.

Figure 66 FFT plot at 20kHz.

1 kHz distortion was simulated with an output voltage of 18Vpk with 4Ω load connected, while distortion at 20kHz was simulated without the load resistance.

74

SQUARE WAVE RESPONSE

Square wave response is useful to see the response of a system particularly if there is any ringing at the edge of the wave. From it is also possible to see if the amplifier enters into slew rate limitation.

Figure 67 square wave response.

The square wave response was simulated with a square wave of 50kHz, where the rise and fall time were set at 10ns, the on time 10μs and the period equal to 20μs. The rounded edges of the waveform are due to the finite bandwidth of the amplifier, from the figure is also possible to see that there is no appreciable trace of ringing.

SIGNAL TO NOISE RATIO

The signal to noise ratio (SNR), can be simulated using LTspice but it tend to be optimistic about the real SNR of the amplifier, this because power supply ripple and EMI are not simulated. Noise was simulated in the 20Hz- 20kHz bandwidth and it has a total rms value of 23.75μV, signal to noise ratio considering an output voltage of 20Vpeak, which is 14.14Vrms, is -115.5 dB. Figure 68 shows the noise plot.

Figure 68 noise plot.

75

DAMPING FACTOR AND OUTPUT IMPEDANCE

The damping factor of an amplifier is the ratio between the load impedance, 4Ω, and the output impedance of the amplifier, the lower the output impedance the higher the damping factor. The output impedance of an amplifier varies with frequency so the best way to simulate it, is by connecting the input of the amplifier to ground and then connecting a voltage source at the output with a resistor R much higher than the output impedance of the amplifier, for example 1kΩ. Output impedance is then calculated as:

The damping factor than is:

Figure 69 shows how the output impedance of the amplifier varies with frequency.

Figure 69 output impedance, where the y values are expressed in mΩ.

The raise of impedance with frequency is explained by the fact that as frequency rises, negative feedback decreases, a function of negative feedback is to reduce output impedance thus if it decreases output impedance increases. From the output impedance plot, the damping factor below 20kHz is always above 100.

OPEN LOOP GAIN AND PHASE MARGIN

The open loop gain of the amplifier can be exposed increasing the value of feedback resistor R75, if its value is increased to 1MΩ the plot figure 70 is obtained. This plot shows the open loop gain of the amplifier for frequencies higher than about 3kHz, showing that it decreases at a rate of -20dB/decade. The frequency at which the open loop gain has the same value of the closed loop gain, which is 27.3dB, is the crossover frequency, here 337 kHz. The phase at this point can be used to calculate the phase margin of the amplifier, considering that the phase is -97°, phase margin is 83°.

76

Figure 70 open loop gain plot.

CONSIDERATIONS ABOUT THE OUTPUT STAGE

The output stage is the point with the higher power dissipation and therefore high temperatures are present. The efficiency of a class AB amplifier is function of the difference between voltage peak of the output signal and rail voltage. The efficiency is given by:

4

This function can be plotted with excel to see how efficiency varies with output power and power dissipation with output power. The graphs obtained are these:

Figure 71, power dissipation vs output power.

05101520253035404550

0 10 20 30 40 50 60

POWER

DISSIPATED

OUTPUT POWER

power dissipation vs output power

77

Figure 72, efficiency vs output power.

The graphs have been drawn using the values of the amplifier which are: load impedance equal to 4Ω, Vcc=30V and for the clipping point 20V, probably too optimistic, all the powers are expressed in Watts. From the graphs is possible to see that as the output power increases also the efficiency does because as output power increases the power dissipated decreases. The power delivered by the amplifier to the load depends on the square of the output voltage and it is:

12

While the input power is equal to:

2

Where Vrail is the rail voltage here 30V and Iav is the average current through the load, which is:

2 1,6

The difference between these two powers is the power dissipated.

These values are important to verify that the MOSFETs being used can withstand the power that they are called to dissipate. The maximum power dissipation of the MOSFETs is 120W at room temperature, figure 73 shows the instantaneous power dissipation of the MOSFETs when the amplifier is delivering about 37Wrms on 4Ω loads which is near clipping with 30Vrails. Maximum power dissipated is less than 50W so the transistor can withstand this power. Now is necessary to define a maximum temperature for the heat sink, 70° is a good value because when touching an object at that temperature there is enough time to remove the hand before burning it. The maximum power that the transistor can dissipate at 70° must be checked; the maximum junction temperature of these MOSFETs is 175°, the thermal resistance between junction and heat sink is 1.49°C/W

0

0,1

0,2

0,3

0,4

0,5

0,6

0 10 20 30 40 50 60

EFFICIENCY

OUTPUT POWER

Efficiency vs power dissipation

78

considering θjc=1.25°C/W and θinsulator=0.24°C/W so maximum power that can be dissipated on average is (175-70)/1.49=70W.

Figure 73, MOSFETs instantaneous power dissipation.

INPUT FILTERS

The input filters of the power amplifiers are shown in figure 74. The first filter is made up by R106 and C48 with corner frequency of 9.65MHz, its function is to avoid EMI interferences such as that caused by cell-phone to reach the input of the amplifier. R107 defines the DC input impedance of the amplifier, it is followed by a low-pass filter with center frequency of 268KHz which reduces the bandwidth of the amplifier. The last filter blocks any DC that could come from the source so it is a high-pass filter with corner frequency of 3.4 Hz. It is worth say that because all of this capacitors are in the signal path they need to be of high quality in order to do not affect the distortion performance, this is especially valid for C50 which is an electrolytic capacitor that are usually not very linear so it should be of very high quality.

Figure 74, power amplifier input filter.

79

The function of R109 is to avoid ground loops. Usually an amplifier is inserted into a metal box so for safe reasons the box must be connected to ground earth, thus all the ground currents of the amplifier should flow into ground earth, but in an amplifier could happen that some currents starts to re-circulate locally rather than through ground earth. R109 reduces ground loops by increasing the loop resistance. The problem with current loops is that they are likely to introduce high quantity of distortion into the signal, for this reasons the amplifier ground architecture is very important and it will be discussed on the power supply PCB design.

POWER SUPPLY

The power supply of an amplifier must be as quite as possible especially it should have a negligible ripple. This characteristic is very important especially for the first two stages of the amplifier. The power rails of the first two stages are usually filtered with a capacitance multiplier like that of figure 75. R57 with C33 made up a low pass filter to pre-filter the input, the rail then is filtered again by another low pass filter made up by C34, R58 and R59 with corner frequency of 5Hz. The capacitance multiplied here is C34, whose value is multiplied by a factor equal to the beta of Q1 in this way the output sees a capacitance whose value is much greater than that of C34. The function of diodes D1 and D2 is to prevent any voltage reversals on Q1.

Figure 75, capacitance multiplier.

The main power supply of the amplifier is an unregulated one. Unregulated means that the transformer voltage is rectified and then applied to many capacitor which function is to give current bursts to the load when needed and to maintain the rail voltage at their nominal value. The current bursts in fact put a high current demand on the transformer thus loading it and lowering its output voltage, but if the rails have high value reservoir capacitors then the current required during the bursts will be provided by the transformer but also by the capacitors thus decreasing the loading on the transformer. All the signal grounds are connected on the PCB to different traces that joint at the same point called the star ground. All other grounds are connected outside the star ground, in this way ground loops are minimized.

80

MICROCONTROLLER

The project includes an alphanumeric LCD display controlled by a PIC18F2420, other functions of the microcontroller are loudspeakers protection against DC on outputs by opening the related relays, mute function, over-temperature protection and bar-graph meter function.

DC PROTECTION

Figure 76 DC protection trigger circuit.

The circuit of figure 76 measures the output DC voltage of the amplifier and if it is too high the circuit acts by modifying the voltage drop on R114 from 0V to 5V, which then generates an interrupt on the PIC. R111 and C51 made up a low pass filter with corner frequency of 0.22Hz, so all audio signals are not processed by the circuit. As for the DC servo for tweeter amplifiers the corner frequency can be increased to 700Hz to improve safety against high amplitude low frequency signals, possible values are 10kΩ with 22nF. The diodes are needed to keep both transistors on, while the function of the zener is to avoid excessive inverse voltages between the base and emitter of Q29 which will destroy the transistor. The DC trigger voltage is about +/- 2.4V, so when a higher voltage is present the transistors are turned on so the voltage drop on R112 increases, lowering the base voltage of Q29 which will turn on it generating almost 5V on the output. V+ and V- are the rail voltages while the last transistor is connected to the 5V supply of the PIC.

OVER-TEMPERATURE RPOTECTION

Figure 77 shows the over-temperature circuit, the circuit checks the heat-sink temperature and if it exceeds 70° a signal is sent to the PIC. Transistor Q30 is connected as a diode-connected transistor so it works like a simple diode, in the schematic it is indicated as a BD135 but any NPN transistor

81

with the screw hole will work. The circuit use the variation of the base to emitter voltage of Q30 to track the temperature, in fact as temperature rises Vbe decreases at an almost constant rate of

Figure 77 over-temperature protection.

-2.2mV/°C. The resistors network is composed of two resistors and a potentiometer Rp whose function is to perfectly set the trigger temperature. The op.amp. acts like a difference amplifier with the non-inverting input biased at a set voltage, in this way when the voltage on the + pin is lower than that at Q30 collector the circuit is inverting so the output saturates at 0V. When the + pin is higher than Q30 collector then the circuit becomes non-inverting and saturates at about 4V which is enough to produce a 1 at the PIC input.

BAR-GRAPH METER

The circuit of figure 78 takes the signal from the crossover treble output and accordingly to which transistor is on a high-pass filter is formed with corner frequency indicated above the related resistors, the signal then is applied to Q36 which is biased by R137 that keeps it on, so the output of the filter varies the collector current of Q36 also varying the voltage drop on R138 which is used by the PIC to display a bar-graph that varies accordingly to the peak voltage of the signal. R121 saturates transistor Q31 while R126 keeps the base of Q31 connected to ground when R121 is floating. The set switch is a simple 2 way 5 outputs switch that is turned by the user to define both the treble and bass frequencies. The circuit for the bass bar-graph meter is shown in figure 79.

82

Figure 78 treble bar-graph meter circuit.

Figure 79 bass bar-graph meter circuit.

83

PIC SOURCE CODE AND FLOW CHART

The microcontroller main program flow chart is shown in figure 80, from it at the start up the microcontroller checks if all outputs are at 0V and if mute is triggered, then accordingly to the mute state it turns on the relays or keep them off. If the first DC on outputs condition is not satisfied the microcontrollers displays a warning signal, then it waits other 3s and if the condition is not met yet an error message is displayed and the relays keep off. The program is explained in the source code, low and high priority interrupts are used where a high interrupt is caused by a PORTB pin state change, which can be caused by any of the protection circuits, while the low priority interrupt is caused by timer 0 which every 5ms reads the value of the ADC conversion and generates two bars on the LCD where the first shows bass frequencies while the second treble frequencies.

Figure 80 microcontroller flow chart.

START

INITIALIZE DISPLAY

DELAY 1.5s

CHECK DC ON OUTPUTS

OUT=0

YES

NO DC PROTECTION ACTIVATED

DELAY 3s

OUT=0

NO

SYSTEM FAILURE

RELAYS OPEN

CHECK MUTE SWITCH

MUTE=0

NO

YES

MUTE RELAYS OPEN

CLOSE RELAYS

END

YES

84

//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//

// HI-FI SYSTEM SOURCE CODE

//

//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

#include <p18f2420.h>

#define LCD_DEFAULT

#include <LCD_44780.h>

#include <delay.h>

// the clock is configured at high speed HS with a crystal of 4MHz

// the watchdog timer is disabled

// LVP disabled

// analog inputs disabled

#pragma config OSC = HS

#pragma config WDT = OFF

#pragma config LVP = OFF

#pragma config PBADEN = OFF

//global variables

int a,b,outputbass,outputtreble;

char j=0xFF;

int bass,treble;

int c,d,g,h,i,l;

double k,firstbass,firsttreble;

// interrupt functions declaration

// low priority interrupt

85

void Low_Int_Event (void);

// high priority interrupt

void High_Int_Event (void);

// high priority function

// when an interrupt is generated this instruction is executed, which then executes

// the code present at High_Int_Event

#pragma code high_vector = 0x08

void high_interrupt (void)

_asm GOTO High_Int_Event _endasm

#pragma code

#pragma interrupt High_Int_Event

// high priority function

void High_Int_Event (void)

// check if interrupt has been provoked by PORTB pin change

if (INTCONbits.RBIF == 1 )

ClearLCD();

// check if over-temperature is triggered i.e. 1

if(PORTBbits.RB5==1)

ClearLCD();

// open relays

PORTBbits.RB0=0;

// turn on backlight

PORTCbits.RC7=1;

ShiftCursorLCD(1,9);

WriteStringLCD("HEAT-SINK OVER-TEMPERATURE");

86

// check if DC protection is triggered i.e. 1

if(PORTBbits.RB6==1)

ClearLCD();

// open relays

PORTBbits.RB0=0;

// turn on backlight

PORTCbits.RC7=1;

ShiftCursorLCD(1,9);

WriteStringLCD("DC PROTECTION ACTIVATED");

// check if mute is activated

if(PORTBbits.RB7==1)

// stop timer

T0CONbits.TMR0ON = 0;

ClearLCD();

// open relays

PORTBbits.RB0=0;

// turn on backlight

PORTCbits.RC7=1;

ShiftCursorLCD(1,18);

WriteStringLCD("MUTE");

// close relays if nothing is activated

if(PORTBbits.RB5==0 && PORTBbits.RB6==0 && PORTBbits.RB7==0)

// turn off backlight

PORTCbits.RC7=0;

// close relays

87

PORTBbits.RB0=1;

// reset interrupt flag bit

INTCONbits.RBIF = 0;

INTCONbits.RBIE = 1;

// low priority function

#pragma code low_vector = 0x18

void low_interrupt (void)

_asm GOTO Low_Int_Event _endasm

#pragma code

#pragma interruptlow Low_Int_Event

// low priority function

void Low_Int_Event (void)

// check if timer interrupt

if(INTCONbits.TMR0IF == 1)

// turn on backlight

PORTCbits.RC7=1;

// number of characters to display calculation

k=4.8828125;

outputbass=(k*bass)/100;

firstbass= (outputbass/10)*20;

outputtreble=(k*treble)/100;

firsttreble= (outputtreble/10)*20;

88

// bass bar-graph

if(firstbass>=0)

ClearLCD();

WriteStringLCD("bass");

ShiftCursorLCD(1,3);

// write character j into LCD firstbass times

for(a=0;a<firstbass;a++)

WriteCharLCD(j);

ClearLCD();

// treble bar-graph

if(firsttreble>=0)

HomeLCD();

// go to LCD line 2

Line2LCD();

WriteStringLCD("treble");

ShiftCursorLCD(1,1);

// write character j into LCD firsttreble times

for(b=0;b<firsttreble;b++)

WriteCharLCD(j);

ClearLCD();

// reset interrupt flag bit

INTCONbits.TMR0IF = 0;

INTCONbits.TMR0IE = 1;

89

// reset timer

TMR0H = 0b11101100;

TMR0L = 0b01111000;

// main program

void main()

// ports setup

LATA=0X00;

TRISA=0b11000011;

LATB=0x00;

TRISB=0b11111110;

LATC=0X00;

TRISC=0x00;

// lcd initialization 4MHz

OpenLCD(4);

ClearLCD();

// backlight on

PORTCbits.RC7=1;

// HI-FI start message

// each letter enters from left and moves right until it reaches the final position

for(i=0;i<22;i++)

ClearLCD();

ShiftCursorLCD(1,i);

WriteCharLCD('I');

delay_ms(50);

90

for(g=0;g<21;g++)

ClearLCD();

ShiftCursorLCD(1,22);

WriteCharLCD('I');

HomeLCD();

ShiftCursorLCD(1,g);

WriteCharLCD('F');

delay_ms(50);

for(h=0;h<20;h++)

ClearLCD();

ShiftCursorLCD(1,21);

WriteStringLCD("FI");

HomeLCD();

ShiftCursorLCD(1,h);

WriteCharLCD('-');

delay_ms(50);

for(c=0;c<19;c++)

ClearLCD();

ShiftCursorLCD(1,20);

WriteStringLCD("-FI");

HomeLCD();

ShiftCursorLCD(1,c);

WriteCharLCD('I');

delay_ms(50);

91

for(d=0;d<19;d++)

ClearLCD();

ShiftCursorLCD(1,19);

WriteStringLCD("I-FI");

HomeLCD();

ShiftCursorLCD(1,d);

WriteCharLCD('H');

delay_ms(50);

// 1.5s delay

delay_ms(1500);

// registers set

// interrupt registers

// port B input change interrupt high priority

// timer 0 interrupt low priority

RCONbits.IPEN = 1;

INTCONbits.GIE = 1;

INTCONbits.GIEH = 1;

INTCONbits.PEIE = 1;

INTCONbits.RBIE = 1;

INTCON2bits.RBIP = 1;

// timer registers

// 16 bit timer

T0CONbits.T08BIT = 0;

// internal clock

T0CONbits.T0CS = 0;

// prescaler

92

T0CONbits.PSA = 1;

// timer interrupts

INTCON2bits.TMR0IP = 0;

INTCONbits.TMR0IE = 1;

// timer setup 5ms

// a low priority interrupt is generated every 5ms

T0CONbits.TMR0ON = 1;

TMR0H = 0b11101100;

TMR0L = 0b01111000;

// ADC registers

// AN0-AN1 analog inputs

// VREF = ground and VCC

ADCON1 = 0b00001101;

// stop timer

T0CONbits.TMR0ON = 0;

// check DC on outputs

if(PORTBbits.RB6==1)

ClearLCD();

// keep relays open

PORTBbits.RB0=0;

HomeLCD();

// turn on backlight

PORTCbits.RC7=1;

ShiftCursorLCD(1,9);

WriteStringLCD("DC PROTECTION ACTIVATED");

// wait 3s

delay_ms(1500);

93

delay_ms(1500);

// check again DC on outputs

if(PORTBbits.RB6==1)

ClearLCD();

// keep relays open

PORTBbits.RB0=0;

// turn on back light

PORTCbits.RC7=1;

ShiftCursorLCD(1,1);

WriteStringLCD("SYSTEM FAILURE DC PROTECTION ACTIVATED");

// check over-temperature

if(PORTBbits.RB5==1)

ClearLCD();

// check mute switch

// keep relays open

PORTBbits.RB0=0;

// turn on back light

PORTCbits.RC7=1;

ShiftCursorLCD(1,9);

WriteStringLCD("HEAT-SINK OVER-TEMPERATURE");

// check if everything is right

if(PORTBbits.RB7==0 && PORTBbits.RB6==0 && PORTBbits.RB5==0)

ClearLCD();

// turn off backlight and turn on relays

94

PORTCbits.RC7=0;

LATB=0b00000001;

// check if mute is activated

if(PORTBbits.RB7==1 && PORTBbits.RB6==0 && PORTBbits.RB5==0)

ClearLCD();

// turn off relays

PORTBbits.RB0=0;

// turn on backlight

PORTCbits.RC7=1;

WriteStringLCD("MUTE");

while (1)

// check if bar-graph mode is activated

if(PORTBbits.RB1==1 && PORTBbits.RB7==0 && PORTBbits.RB6==0 && PORTBbits.RB5==0)

// activate timer

T0CONbits.TMR0ON = 1;

// turn on backlight

PORTCbits.RC7=1;

// AN1 selected as input

ADCON0 = 0b00000100;

// acquisition time 4us with 4Tad and Fosc/4

ADCON2 = 0b10010100;

// ADC enabled

ADCON0bits.ADON = 0x01;

// conversion start

95

ADCON0bits.GO = 1;

// wait end of conversion

while(ADCON0bits.GO);

// conversion value

bass = ((((int) ADRESH) << 8) | ADRESL);

// AN0 selected as input

ADCON0 = 0b00000000;

// acquisition time 4us with 2Tad and Fosc/2

ADCON2 = 0b10010100;

// ADC enabled

ADCON0bits.ADON = 0x01;

// conversion start

ADCON0bits.GO = 1;

// wait end of conversion

while(ADCON0bits.GO);

// conversion value

treble = ((((int) ADRESH) << 8) | ADRESL);

else

// stop timer

T0CONbits.TMR0ON = 0;

// if everything normal turn off backlight

if (PORTBbits.RB1==0 && PORTBbits.RB7==0 && PORTBbits.RB6==0 && PORTBbits.RB5==0)

PORTCbits.RC7=0;

96

SCHEMATICS AND PCBs

The schematics presented here are built with the scope of minimizing noise and distortion, so the rail lines are, when possible, close to cancel the magnetic fields produced by each one, the ground traces are thick and in the amplifiers multiple grounds are used to avoid ground loops, all of these grounds then connect to the star ground of the power supply. To avoid half wave rectified currents reach the first two stages, the output stage has its own power supply lines, in this way is possible to use busted power supply rails for the first two stages thus increasing the clipping point.

IC1

IC2

IC5

IC3

IC4

IC6

IC7

IC8

IC9

TT

C1

C2

C13

C3

C4

C18

C17

R1

R2

R3

R4

R18

R14

R15

R24

R1

9

R2

0

R21

C15

C1

4C

16

R2

3

R2

2

C6

R6

R7

C7

R8

C8

C5

R5

R1

7

C9

R9

R1

0

R11

C111

C12

R12

R16

VIN

POT1L

POT1C

POT1R

POT3L

POT3R

POT3C

POT2CPOT2L

POT2R

POT4LPOT4CPOT4R

POT5LPOT5CPOT5R

POT6CPOTCLPOTCR

V+15

V-15

C11

GND

VINGND

C19

C200

C2

2

C2

3

C24

C2

5C

26

C27

C29

C30

C2

8

R255

R26

R2

7R

28 R29

R32

R3

4

R35

R42

R44

R4

6

R47

R4

8

R37

R39

R38

BASS

C1

99

C20

R30

R31

C2

1

OUTPREAMP

C1

0

R40

R41

R43

R4

5

C3

1

C3

2

R50

R5

2

R5

4

R5

5

R56

R49

R5

1

R5

3

TREBLE

R3

3

R36

R25

Preamplifier and crossover schematic.

97

NE

5532D

NE

5532D

GN

D5

GN

D5

GN

D5

GN

D5

GN

D5

NE

5532DN

E5532D

NE

5532D

NE

5532D

GN

D5

GN

D5

GN

D5

GN

D5

GN

D5

GN

D5

GN

D5

GN

D5

NE

5532D

NE

5532D

GN

D5

GN

D5

NE

5532D

NE

5532D

GN

D5

GN

D5

GN

D5

GN

D5

GN

D5

GN

D5

GN

D5

GN

D5

GN

D5

GN

D5

NE

5532D

NE

5532D

NE

5532D

NE

5532DN

E5532D

NE

5532DN

E5532D

NE

5532D

C1

C2

C13

C3

C4

C18 C17

R1

R2

R3

R4

IC1A

2 31

IC1B

657

R18

R14

R15

R24

IC2A

231

IC2B

657

IC5A

231

IC5B

6 57

R19

R20

R21 C15

C14

C16

R23

R22

C6

R6

R7

C7

R8

C8

C5

R5

R17

C9

R9

R10

R11

C111

C12

R12

R16

IC3A

231

IC3B

657

VIN

POT1L

POT1C

PO

T1R

POT3L

POT3R

POT3C POT2C

POT2L

POT2R

POT4L

POT4C

POT4R

PO

T5L

PO

T5C

PO

T5R

POT6C

POTCL

POTCR

V+

15

V-15

C11

GN

D

VIN

GN

D

C19

C200

C22

C23

C24

C25

C26

C27

C29C30

C28

R255

R26

R27

R28

R29

R32

R34

R35

R42

R44

R46

R47

R48

R37

R39

R38

BA

SS

C199

C20

R30

R31

IC4A

2 31

IC4B

6 57

C21

OUTPREAMP

C10

R40

R41

R43

R45

C31C32

R50

R52

R54

R55

R56

R49

R51

R53

TR

EB

LE

84

84

84

84

84

84

84

84

84

R33

R36

R25

IC7A

2 31

IC7B

6 57

IC6A

2 31

IC6B

657

IC8A

231

IC8B

657

IC9A

231

IC9B

657

+

+

+ +

+

+

+

+

+

+

98

1N49331N49332N

39

04

2N

39

04

2N

39

04

2N

39

04

2N

39

06

2N

39

06

2N

39

06

2N

39

06

2N

39

06

2N

39

04

2N

39

04

2N

39

06

2N

39

06

2N

39

04

2N

39

04

2N

39

06

2N

39

06

2N

39

04

2N

39

04

2N

39

04

2N

39

04

2N

39

04

BD

13

9

2N

39

06

BD

14

0

IRF

P2

53

IRF

P2

53

1N

49

33

1N

49

33

4N

35

lou

dsp

ea

ker g

rou

ng

sign

al g

rou

nd

po

we

r gro

un

d

V+

1N4933

1N4933 1N4933

V-

1N4933

OP

A1

34

D

+1

5

-15

inp

ut

inp

ut g

rou

nd

2N

39

06

TIC

22

5S

R5

7

R58R59

R6

0

R77

R78

D1D2

Q1

Q5

Q6

Q9

R65

R66

R67

R6

8

R6

9R

70

R7

2R

73

R7

6

R79

R81

R80

R83

R82

R21

R91

R86

R87

R88

R26R90R89

Q7

Q8

Q4

Q2

Q3

Q11

Q1

0

Q1

6

Q1

5

Q1

4

Q1

3

Q1

7

Q1

8

Q2

2

Q2

1

Q1

9

Q2

0R8

99 A

E

S

R7

5

R74

Q2

4

Q2

5

Q2

3

Q2

6

R95

R96

M2

M1

D5

D6

OK

112

64 5

R100

R94

R5

77

R5

77

7

R5

77

77

R5

77

77

7

R71

R1

08

R107

C4

9

C44

C43C41

C42

C4

7

R104

R1

05

PAD1

PAD2

PA

D3

PA

D4

PA

D6

R102R103

PA

D5

C3

3

PA

D8

PA

D9

D7

R6

1

R62 R63

R6

4

D4 D3

R6

11

R6

111

R6

1111

R6

11111

PA

D1

0

D8

R84

R8

5

R110

C39

C4

0IC

1

8

1

236

57 4

PA

D7

PA

D11

R106

C4

8

PA

D1

2

PA

D1

3R109

C3

4

C3

5

C3

6Q

12

C3

7

C3

8

R9

7

R9

8

R101R99

C4

6

C4

5

C50

T1

PA

D1

4

PA

D1

5

PA

D1

6

++

+

++

+

+

99

Vin

in gnd

sig gnd

+15

-15

lds gnd

Vout

power gnd

mains and chassis earth

op amp gnd

V+

V+

V-

V-

100

Vin

in gnd

sig gnd

+15

-15

lds gnd

Vout

power gnd

mains and chassis earth

op amp gnd

V+

V+

V-

V-

OPA134D

IC1

Vin

in gnd

sig gnd

+15

-15

lds gnd

Vout

power gnd

mains and chassis earth

op amp gnd

V+

V+

V-

V-

21

611

W

5W

5W

5W

23

1

23 1

23

1

23

1

123

12

3

12

3

123 123

23

1

23

1

12

3 1 2 3

23

1

2 31

123

12

3

2 31

2 31

2 31

2 31

23

1

123

123

123

12

3

R57

R58

R59

R60

R77

R78

D1

D2

Q1

Q5

Q6

Q9

R6

5

R6

6

R67

R68

R6

9

R70

R7

2

R73

R76

R79

R81

R8

0

R83

R82

R2

1

R91

R86

R87

R88

R2

6

R90

R8

9Q7

Q8

Q4

Q2 Q3

Q11

Q1

0

Q1

6

Q15

Q1

4Q13

Q17

Q1

8

Q22

Q21

Q19

Q20

R899

R75

R74

Q2

4

Q25

Q23

Q26

R95

R96

M2 M1

D5

D6

OK

1

R100

R94

R577

R5777

R57777

R577777

R71

R108R107

C4

9

C44

C4

3

C4

1

C42

C47

R104

R105

PA

D1

PA

D2

PA

D3

PA

D4

PA

D6

R1

02

R1

03

PAD5

C33

PA

D8

PA

D9

D7

R6

1

R6

2

R6

3

R6

4D

4

D3

R6

11

R6

111

R6

1111

R6

11111

PA

D1

0

D8

R84

R8

5

R110C39

C4

0

PAD7PAD11R

10

6

C4

8

PAD12

PAD13

R109

C34C35 C

36

Q1

2

C37

C3

8

R97R98

R101

R99

C46 C45

C50

T1

PA

D1

4

PA

D1

5P

AD

16

1N4933

1N

49

33

2N

39

04

2N3904

2N

39

04

2N

39

04

2N3906

2N

39

06

2N

39

06

2N3906 2N3906

2N

39

04

2N

39

04

2N

39

06

2N3906

2N

39

04

2N3904

2N3906

2N

39

06

2N3904

2N3904

2N3904

2N3904

2N

39

04

BD139

2N3906

BD140

IRFP253 IRFP253

1N

49

33

1N4933

4N35

1N4933

1N

49

33

1N4933

1N

49

33

2N

39

06

TIC225S

101

LM

34

0H

-12

33

7T

1N40041N4004

1N40041N4004

AG

ND

AG

ND

AG

ND

AG

ND

1N40041N4004

1N40041N4004

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

AG

ND

LM

34

0H

-12

AG

ND

AG

ND

AG

ND

AG

ND

B1

AC1AC2

-+B2

AC1AC2

-+

C6

5C

66

C6

4C

63

C9

7

IC1

GN

D

VI

1

2

VO

3

IC2

AD

J

VI

2

1

VO

3

C9

5C

96

D30D31

D32D33D34 D35

D36 D37

C9

9C

10

0C

10

1

C6

7C

69

C7

0C

68

C7

1C

72

C7

3C

74

C7

5C

76

C8

1C

82

C8

3C

84

C8

5C

86

C8

7C

88

C8

9C

90

C9

4

C9

8

C1

04

IC3

GN

D

VI

1

2

VO

3

C1

02

C1

03

V+1

V+2

V+3

V+4

V+5

V+6

V+7

V+8

V-1

V-2

V-3

V-4

V-5

V-6

V-7

V-8

-15V1

-15V3

-15V2

-15V4

-15V5

-15V6

-15V7

-15V8

-15V9 15V9

15V7

15V8

15V6

15V5

15V4

15V3

15V2

15V1

V-9

V-10

V-11

V-12

V+9

V+10

V+11

V+12

5V4

5V2

5V3

5V1

GND1

GND2

GND3

GND4

GND5

GND6

GND7

GND8

GND9

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND18

GND19

GND20

GND21

GND22

GND23

GND34

C7

8

C9

1C

92

C7

9C

80

C9

3

CAP1

CAP2-

X1

-1

X1

-2

X1

-3

CAP1-

CAP2

F1

F2

F3

F4

F5

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

+

++

+ +

++

CE

NT

RA

L TAP

E

102

GND

V+

V-

5V

+15V

-15V

AUDIO GND

SUB CIR GND

GND

V+

V-

5V

+15V

-15V

AUDIO GND

SUB CIR GND

12

3

B1

B2C65

C6

6

C64

C6

3

C97

IC1

IC2

C95

C96

D30

D31

D32

D33

D3

4

D3

5D

36

D3

7

C99

C1

00

C101

C67 C69

C70

C68

C71C72

C73 C74

C75

C76

C81

C82

C83

C84

C85

C86

C87

C88C89

C90

C94

C98

C104

IC3

C1

02

C103

V+1V+2V+3V+4V+5V+6V+7V+8

V-1

V-2

V-3

V-4

V-5V-6V-7

V-8

-15V

1-15V

3-15V

2

-15V

4 -15V

5-15V

6-15V

7-15V

8-15V

9

15V915V715V815V615V515V415V3 15V215V1

V-9

V-10

V-11V-12

V+9V+10V+11V+12

5V45V2 5V35V1

GND1

GND2GND3

GND4

GND5

GND6

GND7

GND8

GND9

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND18

GND19

GND20

GND21GND22

GND23

GND34

C78

C91

C92

C79

C80

C93

CAP1

CAP2-

X1

CAP1-

CAP2

F1

F2

F3

F4

F5

LM340H-12

337T

1N4004

1N4004

1N4004

1N40041N

40

04

1N

40

04

1N

40

04

1N

40

04

LM340H-12

103

GND

V+

V-

5V

+15V

-15V

AUDIO GND

SUB CIR GND

104

+5V

/1

AG

ND

1N4004

1N4004

1N4004

1N4004

2N3904

2N3906

AG

ND

AG

ND

AG

ND

2N3906

AG

ND

BZV10

AG

ND

V+

V-

+5V

1N4004

1N4004

1N4004

1N4004

2N3904

2N3906

AG

ND

AG

ND

AG

ND

2N3906

AG

ND

BZV10

AG

ND

V+

V-

+5V

1N4004

1N4004

1N4004

1N4004

2N3904

2N3906

AG

ND

AG

ND

AG

ND

2N3906

AG

ND

BZV10

AG

ND

V+

V-

+5V

1N4004

1N4004

1N4004

1N4004

2N3904

2N3906

AG

ND

AG

ND

AG

ND

2N3906

AG

ND

BZV10

AG

ND

V+

V-

+5V

74LS32N

74LS32N

74LS32N

E3206S

E3206S

E3206S

E3206S

+5V

+5V

/1

AG

ND

V+

V-

D1

4

D15

D1

6

D17 Q43

Q44

R154

C5

8

R153

R155

Q45

R156

D18

D2

4

D25

D2

6

D27 Q49

Q50

R163

C6

0

R162

R164

Q51

R165

D28

D9

D10

D11

D12 Q27

Q28

R112

C5

1

R111

R11

3

Q29

R114

D13

D1

9

D20

D2

1

D22 Q46

Q47

R159

C5

9

R158

R160

Q48

R161

D23

IC3A

123

IC3B

456

IC3C

9

10

8

IC3PGND VCC

7 14

K1

2 1

K1 O

S

P

K2

2 1

K2 O

S

P

K3

2 1

K3 O

S

P

K4

2 1

K4 O

S

P

PAD22

PA

D23

PAD25

PA

D26

PA

D28

PA

D30

PAD31

PAD32

R157

PA

D35

PA

D36

PA

D15

GN

D1

5V1

V+1

V-1

OU

TP

UT

RE

LA

YS

DC

ON

OU

TP

UT

S C

HE

CK

CIR

CU

IT

PA

DS

23 26 28 30 TO

AM

P O

UT

PU

TS

PA

DS

22 25 32 31 TO

LOU

DS

PE

AK

ER

S +

105

D14

D15

D1

6

D1

7

Q4

3

Q4

4

R154

C5

8

R1

53

R155

Q4

5

R156

D18

D24

D25

D2

6

D2

7

Q4

9

Q5

0

R163

C6

0R

16

2

R164

Q5

1

R165

D28

D9D1

0

D11

D12

Q27

Q28

R11

2

C51

R111

R11

3 Q29

R11

4

D1

3

D19

D20

D2

1

D2

2

Q4

6

Q4

7

R159

C5

9

R1

58

R160 Q4

8

R161

D23

IC3

K1

K2

K3

K4

PAD22

PAD23

PA

D2

5

PA

D2

6

PA

D2

8

PAD30PAD31 PA

D3

2

R1

57

PAD35

PAD36

PAD15

GND1

5V1

V+1

V-1

1N4004

1N4004

1N

40

04

1N

40

04

2N

39

04

2N

39

06

2N

39

06

BZV10

1N4004

1N4004

1N

40

04

1N

40

04

2N

39

04

2N

39

06

2N

39

06BZV10

1N

40

04

1N

40

04

1N4004

1N4004

2N39042N3906

2N3906

BZ

V10

1N4004

1N4004

1N

40

04

1N

40

04

2N

39

04

2N

39

06

2N

39

06

BZV10

74LS32N

E3206S

E3

20

6S

E3

20

6S

E3206S

106

PIC

18F2455_28D

IP

4MHz

15pF15pf

AG

ND

10k

+5V

/1

AG

ND

+5V

/1

AG

ND

AG

ND

+5V/1

AG

ND

2N3904

2N3904

2N3904A

GN

D

+5V

/1

2N3904A

GN

D

+5V

/1

2N3904

2N3904

AG

ND

2N3904

2N3904

2N3904

2N3904

2N3904

AG

ND

2N3904

AG

ND

AG

ND

+5V

/1

AG

ND

2N3904

1N4004

+5V

/1

AG

ND

+5V

/1

AG

ND

2N3904

AG

ND

+5V

/1

2N3904

AG

ND

+5V

/1+

5V/1

AG

ND

LM358N

+5V

/1

AG

ND

+5V

/1

+5V

/1

+5V

/1

+5V

/1

AG

ND

IC1

RC

7/RX

/DT

/SD

O18

VS

S8

VD

D20

RB

0/AN

12/INT

0/LFT

0/SD

I/SD

A21

RB

1/AN

10/INT

1/SC

K/S

CL

22R

B2/A

N8/IN

T2/V

MO

23R

B3/A

N9/C

CP

2/VP

O24

RB

4/AN

11/KB

I0/CS

SP

P25

RB

5/KB

I1/PG

M26

RB

6/KB

I2/PG

C27

RB

7/BK

I3/PG

D28

MC

LR/V

PP

/RE

31

RA

0/AN

02

RA

1/AN

13

RA

2/AN

2/VR

EF

-/CV

RE

F4

RA

3/AN

3/VR

EF

+5

RA

4/T0C

KI/C

IOU

T/R

CV

6

RA

5/AN

4/SS

/HLV

DIN

/C2O

UT

7

VS

S19

OS

C1/C

LKI

9

RA

6/OS

C2/C

LKO

10

RC

0/TIO

SO

/T13C

KI

11

RC

1/T1O

SI/IC

CP

2/UO

E12

RC

2/CC

P1/P

1A13

VU

SB

14R

C4/D

-/VM

15R

C5/D

+/V

P16

RC

6/TX

/CK

17

Q121

C62C61

R166

PAD1 PA

D2

R137

R136

R132

R131

R121

R122

Q31

Q32

Q36

R138

C52

PA

D3

PA

D4

PA

D5

R151

R150

Q42

R152

R134

R133

R124

R123

Q33

Q34

PA

D9

PA

D10

R135

Q35

R125

PA

D13

R140

R141

Q37

Q38

PA

D6

PA

D7

PA

D8

R143

R142

Q39

Q40

PA

D11

PA

D12

Q41

R144

PA

D14

R139

C57

C56

C55

C54

C53

R149

R148

R146

R147

R145

R130

R129

R127

R128

R126

PA

D19

R167

PAD20

R168

R169

Q53

D29

PA

D21

R170

PAD24Q52

R171

PA

D27

PA

D29

Q30

R115

R116

R117R118

RP

A E

SIC

2A

231

84

R119

R120

PA

D33

PA

D34

GN

D 5V

PA

D37

PA

D38

SV

2

1 3 5

2 4 67 9 11

8 10 12 1413

PA

D16

RE

SE

T

MU

TE

BA

CK

LIGH

T

BA

R G

RA

PH

ME

TE

R S

WIT

CH

BA

R G

RA

PH

ME

TE

R C

IRC

UIT

LCD

CO

NN

EC

TO

R

OV

ER

-TE

MP

ER

AT

UR

E C

IRC

UIT

to relaysto 7432 output

107

1

14

IC1

Q1

C6

2C

61

R166

PA

D1

PA

D2

R137

R136

R132R131

R1

21

R1

22

Q31Q32

Q36

R1

38

C52

PAD3

PAD4PAD5

R1

51

R150

Q4

2

R152

R134

R133

R1

24

R1

23

Q33Q34

PAD9 PAD10

R135

Q35

R1

25

PAD13

R140

R141

Q3

7Q

38

PAD6

PAD7

PAD8

R143

R142

Q3

9Q

40

PAD11

PAD12

Q4

1

R144PAD14

R139

C57

C56

C55

C54

C53

R149

R148

R146

R147

R145

R1

30

R1

29

R1

27

R1

28

R1

26

PA

D1

9R1

67

PA

D2

0

R168

R1

69

Q5

3D

29

PA

D2

1

R170

PA

D2

4

Q5

2

R171

PA

D2

7P

AD

29

Q30R115

R116

R117 R11

8

RP

IC2

R119

R120

PAD33

PAD34 GN

D

5V

PA

D3

7

PA

D3

8SV2

PA

D1

6PIC

18F2455_28D

IP4M

Hz

15

pF

15

pf

10k

2N39042N3904

2N3904

2N

39

04

2N39042N3904 2N3904

2N

39

042

N3

90

42

N3

90

42

N3

90

42

N3

90

4

2N

39

04

1N

40

04

2N

39

04

2N3904

LM

35

8N

108

109

FINAL CONSIDERATIONS

The PCBs have been designed with the scope of using as much as possible the components I had so reducing the overall cost which is still high. From the schematics is possible to see that some components are different than that described, this is so because the PCB software I used does not have all the right components so I used others with the same footprint, therefore to see all the right components refer to LTspice circuits figures. At the time of writing only one channel of the HI-FI system is completed and built, to see it working watch this video on youtube: http://www.youtube.com/watch?feature=player_embedded&v=GNI0hrs_nPc#!

Considering that the loudspeakers used are not of high quality the amplifier sounds good, a special thanks to the users of diyaudio.com who helped me with the dimension of the loudspeakers enclosure because I did not have the Thiele small signal parameter so I had to calculate them. The relays have their own PCB with the DC protection circuits, I did so because the PIC PCB will be near the frontpanel of the amplifier while the relays will be near the amplifiers on the back panel thus there is noneed to run long wires from the amplifiers to the PCB which will be likely to pick up distortion and generate crosstalk. Notice: No responsibility is assumed by the author for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions or ideas contained in the material herein.

Lucchi Davide

3/3/2013 Italy