Design of a Novel Dual-core Ultrasonic Nondestructive Testing System Based on ARM and FPGA

Chao Peng1*, Weiheng He1, Yue Song1, Sha Zou2 1School of Electrical Engineering and Intelligentization, Dongguan University of Technology, Dongguan,

523808, China 2HengNan County Seventh Middle School, Hengyang, 421000, China

*E-mail: pengchao@dgut.edu.cn

Keywords: Nondestructive testing;ultrasound imaging; ARM; FPGA;

Abstract: In this paper, a new system for nondestructive testing in the field of ultrasonic nonmetal detection is designed. The paper first analyzes the design difficulties and technical challenges in the ultrasonic nondestructive testing system. Then the complementarity between ARM and FPGA is used to design a complete set of ultrasonic non-destructive testing system with dual core as the main control. The system mainly includes ultra low noise variable gain amplifier module VGA, anti-aliasing filter module, high speed digital-to-analog converter module ADC, precision gain control DAC, precision voltage source and clock source module and ARM+FPGA master module. Finally, the correctness and rationality of the design are verified by establishing the circuit model of digital signal processing and the actual circuit. The dual-core ultrasonic nondestructive testing system designed in this paper not only has good expansibility, is easy to use in the field, but also has smaller size and lower power consumption. At the same time, it can further reduce the hardware cost of the ultrasonic imaging system, and also lay a solid foundation for other ultrasonic testing systems and equipment, and has good engineering application value.

1. Introduction

Ultrasound is a kind of sound wave whose frequency is higher than 20,000 Hz. It has the characteristics of good direction, high power, strong penetration, easy to obtain concentrated sound energy, and no damage to the detected substances and human body.These advantages make ultrasound widely used in medical[1, 2], military[3, 4], agricultural and almost all industrial flaw detection fields[5, 6]. In addition, ultrasonic detection has a lot of in-depth research and application in thickness measurement[7, 8], ranging and medical ultrasound imaging[9, 10].Nondestructive testing (NDT) is a frequently used analytical tool in scientific research and industry to evaluate the properties of materials and components without damaging or permanently changing them. This can save a lot of money and time, so it is widely used in machine engineering, electrical engineering and civil engineering in many areas of product evaluation, fault detection and research[11-13].At the same time, with the development of integrated circuits and digital signal processing algorithms, the requirements for the performance and diagnostic capabilities of ultrasonic non-destructive testing in the industrial and medical fields are also increasing.

The design of modern ultrasonic nondestructive testing systems has the following difficulties and technical challenges:

(1) Conventional ultrasound imaging systems require a large number of high performance transmitters and receivers, resulting in a large and expensive system. With the development of integrated circuits, we also need to reduce the size and power consumption of written ultrasonic non-destructive testing instruments, thereby extending battery life and simplifying field use.

(2) As devices become smaller, especially with the goal of improving image quality, heat dissipation becomes very important.

(3) In order to improve the signal penetration rate and harmonic imaging, a higher transmission voltage is needed

2019 7th International Conference on Machinery, Materials and Computing Technology (ICMMCT 2019)

Published by CSP © 2019 the Authors 732

2. Overall design of twin-core ultrasonic nondestructive testing system

After analyzing the difficulties and challenges of ultrasonic non-destructive testing system design, we designed the overall block diagram of the system using ARM+FPGA dual-core master control mode, as shown in Figure 1. The system includes ultra low noise variable gain amplifier module VGA, anti-aliasing filter module, high speed digital-to-analog converter module ADC, precision gain control module DAC, precision voltage source and clock source module, ARM+FPGA master module and transmit circuit driver modules etc.

Figure 1 Overall Block Diagram of System

The transmitting circuit driving module can use the conventional capacitor instantaneous discharge method to generate high voltage pulses, or can be realized by a combination of a new high speed waveform generator and a high voltage operational amplifier. Anti-aliasing noise filters are often used in conjunction with ADCs. The filter requirements depend on the application. When the ADC is on another board, most of the filter components should be placed nearby to suppress noise between the boards and to reduce the charge backlash at the ADC input.

3. Design of VGA Module

As shown in Figure 2, we use AD8334 to construct VGA module. AD8334 has four channels, ultra-low noise, linear dB, pre-amplifier and programmable input resistance.When the gain slope control pin MODE goes high (if available), the gain slope is negative. The pin is set to HI gain mode to select the reverse gain mode. It is from −4.5dB to +43.5dB in LO gain mode and +7.5 dB to +55.5 dB in HI gain mode. The LNA intermediate power supply bypass pin LMD must be bypassed to ground and the signal is supplied to the INH pin for capacitive coupling with a 2.2nF to 0.1μF capacitor. The LNA's unterminated input impedance is 6kΩ, allowing users to synthesize any LNA input resistor from 50Ω to 6kΩ.The common-mode voltage-AC bypass pin VCM is typically set to 2.5V. A 1nF capacitor should be placed in parallel with a 0.1μF capacitor and the 1nF capacitor should be placed as close as possible to the VCM pin. The gain control voltage GAIN recommends using a bypass capacitor of 100pF to 1nF.The output clamp level pin RCLMP provides the user with a way to limit the output voltage swing.

Figure 2 VGA Module Schematic Diagram

0.1uF

C22c

GND

C4c

1nFC16c

0.1uFC15c

0.1uFC5c

Ciz1c

Riz1c

GND

GND

GND

GND

0.1uF

C26c

0.1uFC9c

1nFC6c

C23c

0.1uFC18c

0.1uFC19c

1nFC10c

GND

0.1uFC3c

GND

1nFC14c

GND

0.1uFC37c

GND

0.1uF

C38c

Ciz3cRiz3c

GND

GND

GND

GND

0.1uFC32c22pF

C30c

0.1uF

C29c

0.1uF

C33c

0.1uF

C28c

0.1uF

C35c

GND

0.1uF

C34c0.1uF

C31c

0.1uFC39c

22pF

C36c

Ciz4cRiz4c

GND

GND

0.1uF

C1c

GND

GNDGND

0.1uF

C2c

GND

GND

0.1uF

C24c

22pFC27c

GND

0.1uFC25c

GND

Ciz2c

Riz2c

0.1uFC20c

0.1uFC21c

0.1uFC17c

GND

0.1uFC13c

GND

0.1uFC12c

1nFC11c

GND

0.1uFC8c

GND

0.1uFC7c

GND

GND

120nH

L5c

120nH

L6c

120nHL8c

120nHL10c

lop1

lop

3

lop4

lop2

lon1

lon2

lon

3

lon4

vgain34vgain12

120nH

L1c

120nH

L3c

120nH

L2c

120nH

L9c120nH

L7c

120nH

L4c

VCM249

VCM150

EN3451

EN1252

CLMP1253

GAIN1254

VPS155

VIN156

VIP157

LOP158

LON159

NC60

LMD161

INH162

COM163

COM264

CO

M3

43

3

VO

H4

34

VO

L4

35

VP

S34

36

VO

L3

37

VO

H3

38

CO

M3

43

9

NC

40

MO

DE

41

CO

M1

24

2

VO

H2

43

VO

L2

44

VP

S12

45

VO

L1

46

VO

H1

47

CO

M1

24

8

COM317

COM418

INH419

LMD420

NC21

LON422

LOP423

VIP424

VIN425

VPS426

CAIN3427

CLMP3428

HILO29

VCM430

VCM331

NC32

INH

21

LM

D22

NC

3

LO

N24

LO

P25

VIP

26

VIN

27

VPS

28

VPS

39

VIN

310

VIP

311

LO

P3

12

LO

N3

13

NC

14

LM

D315

INH

316

EP65

*1cComponent_01

vol2

vol3

vol4

voh

1

voh

2

voh

3

voh

4

GND

GND

GND

GNDGND

GND

GND

VOH1 VOL1 VOL2 VOH2 VOH3 VOL3 VOL4 VOH4

VGAIN12VGAIN34

Q6cQNPN

GND

Q7cQNPN

GND

Q8cQNPN

GND

Q5cQNPN

+5V+5V

+5V +5V

+5V

+5V

+5V+5V

hilo

733

4. Design of Precision Gain Control Module

The AD5686R is used to achieve precise gain control. The specific design is shown in Figure 3.

Figure 3 Precision Gain Control Module Schematic

The AD5686R is controlled by the FPGA, and then the control signal is transmitted to the VGA through digital-to-analog conversion to control its gain.The power supply VDD is decoupled to GND through a parallel 10μF capacitor and a 0.1μF capacitor. The power supply VLOGIC is powered by a +5V digital power supply.AD5686R data frame synchronization signal pin SYNC, serial data input SDIN, serial data output SDO, serial clock input SCLK, *LDAC, power-on reset pin RESTSEL, asynchronous reset input pin *RESET are all connected to the FPGA through the SPI bus, and the input and synchronization are controlled by the FPGA.AD5686R's controllable gain pin GAIN can control two-stage gain either at ground level or at high level. When this pin is connected to GND, the output range of all four DACs is 0V to VREF. If this pin is tied to VDD, the output range of all four DACs is 0V to 2 × VREF (VREF is the chip's own reference voltage, the value is 2.5V).The output pins of the chip, OUTA, VOUTB, VOUTC, and VOUTD, are the analog output voltages of the DAC and are connected to the corresponding ports of the VGA.

5. Design of High Speed Digital to Analog Conversion Module

The AD9257 is an 8-channel, 14-bit, 40/65 MSPS serial low voltage differential signaling (LVDS) analog-to-digital converter. The specific design is shown in Figure 4.

Figure 4 AD9257 Main Schematic

The AD9257 is available in an LFCSP package with an exposed pad on the bottom that requires adequate grounding for proper operation. It is connected to the analog ground through a square of multiple vias to help dissipate heat. The VCM pin should be decoupled to ground with a 0.1μF capacitor. All power supply pin inputs on the chip require a 0.1uF high frequency filter capacitor. The capacitor should be as close as possible to the power supply pin of the chip. The SPI port should be disabled when the converter is required to take full advantage of its full dynamic performance.

5.1. Design of analog input terminal for AD9257

The analog input of AD9257 is a differential switched capacitor circuit, which leads to its suitability for processing the differential signal converted from the single input signal of AD8334.

0.1uF

C1bCap

10uF

C2bCap

VDD5

VLOGIC11

*SYNC13

SDIN14

SDO8

SCLK12

*LDAC9

RSTSEL16

*RESET15 VREF 1

VOUTA 3VOUTB2VOUTC 6

VOUTD 7

GAIN 10

GND 4

U1b

AD5686RARUZ

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GND

GND

GAIN

+5V

VGAIN12VGAIN34 2

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SW-SPDT

*SYNCSDINSDOSCLK

*LDACRETSEL*RESET VREF

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C102a

GND

10KR80a

GND

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CD

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FC

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OD

CO

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ED

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C98a

VCC42

VCM

1.8V DUT-AVDD

GND

1.8V_DUT_AVDD

1.8V DUT-AVDD

1.0uFC104a

GND

AVDD1

VIN+G2

VIN-G3

AVDD4

VIN-H5

VIN+H6

AVDD7

AVDD8

CLK-9

CLK+10

AVDD11

AVDD12

DNC13

DRVDD14

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17

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FCO

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D51

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61A

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D62

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1.0uF

C99a

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R76a

49.9

R78a

GND

SYNC

1.0uF

C111a

GND

1.0uF

C112a

GND

1.0uF

C113a

GND

1.0uF

C114a

1.0uF

C107a

GNDGND

1.0uF

C106a

1.0uF

C105a

GND

1.0uF

C108a

GND

1.0uF

C109a

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2KR68a

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In order to reduce the high differential capacitance of the input and achieve the maximum bandwidth of ADC, low Q inductance or ferrite beads must be used to drive the front end of the converter at high and medium frequencies. Here we use differential transformer coupling drive ADC input mode. As shown in Figure 5.

Figure 5 Analog Input Schematic of AD9257

ADT1-1WT RF transformer is used to achieve input-output impedance matching, DC isolation, common-state suppression and balance transformation. The turn ratio is 1:1. Because the transformer is passive, it will not amplify the signal noise. The transformer without gain makes the signal ripple and roll-off more significant. The differential signal input on the left side has 0.1uF capacitor to isolate DC. The design of input impedance and output impedance is close to 50 ohms, so impedance matching can be achieved. The output terminal of transformer is also separated by 0.1uF capacitor. The differential signal indirect 5pF capacitor can suppress the differential mode interference. The effect of MABA007159-000000 transformer is similar to that of ADT1-1WT. Dual transformer topology can achieve better performance in analog input, but PCB layout plays an important role. When adding this transformer layout, it should be symmetrical as possible, otherwise the use of dual transformer topology will not work.

5.2. Design of AD9257 Power Supply Module

In order for the high speed analog-to-digital converter to perform at its best, it must be supplied with a clean DC power supply. High noise power supplies can cause signal-to-noise ratio (SNR) drops and/or undesirable spurious components in the ADC output. In this system we use the ADP1706, which operates from a 2.5V to 5.5V supply with a maximum output current of 1A. At the same time, the system also uses the DC-DC converter ADP2108 to provide 1.8V digital power and 1.8V analog power to the system. The ADP2108 is a high efficiency, low quiescent current, step-down DC-DC converter with excellent stability and transient response. The specific design is shown in Figure 6.

Figure 6 Schematic Diagram of AD9257 Power Module

The 4.7uF capacitor beside ADP1706 can achieve excellent transient response performance of line and load, while the decoupling capacitor of 0.1uF can reduce the fluctuation of power supply voltage. When using the DC-DC converter chip ADP2108, the EN can be connected to 100K and 1K resistor voltage divider first, and the EN level can be lowered. The conversion from ADP2108 to 1.8V_AVDD and 1.8V_DRVDD can be temporarily disabled.The front end of ADP2108 uses three 10uF capacitors to filter the DC input power supply, providing a stable voltage value for ADP2108. The output terminal of ADP2108 is connected with a second-order filter circuit to enhance the filtering of DC voltage and obtain a stable output voltage. In the power supply system, a number of 39 Euros magnetic beads are used to suppress high frequency noise and peak interference, and also

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to absorb electrostatic pulses. The magnetic beads have high resistivity and permeability, which are equivalent to series resistance and inductance. All output voltages are decoupled by parallel connection of multiple 0.1uF and 10uF capacitors to reduce the fluctuation of power supply voltage.

5.3. Design of AD9257 Clock Module

Considering the cost and complexity of implementation, the system adopts Silabs Si530 clock chip, which has excellent jitter performance. The typical value of phase jitter is 0.36 PS in the output frequency range of 125 Hz to 500MHz. Unlike traditional clock chip, its built-in fixed frequency can support arbitrary frequency output from 10 MHz to 945 MHz, and support three levels of LVDS, CMOS and LVPECL. To take full advantage of the performance of the AD9257, the Si530 differential LVDS output clock signal is ac-coupled to the AD9257 sample clock terminals (CLK+ and CLK-). The circuit design is shown in Figure 7.

Figure 7 Schematic Diagram of the AD9257 Clock Module

GND is analogically isolated from digital signals, OE pins are enabling pins, VDD pins are power supply pins, all use 3.3V_CLK, while R160, R161, R162 and R163 provide bias voltage to differential clock signals, which enhances the ability of low jitter. High-speed and high-resolution ADC is very sensitive to the quality of clock input signal. When designing the clock of ADC, the problem of aperture jitter should be carefully considered. In order to reduce the influence of aperture jitter on AD9257, the clock input signal is regarded as an analog signal, and the clock drive power supply is isolated from the ADC output driver power supply to avoid the clock signal mixed with digital noise.

5.4. Design of AD9257 Serial Port Function

The AD9257 serial interface (SPI) allows the user to configure the converter with a structured register space inside the ADC to meet specific functional and operational needs. SPI is flexible and can be tailored to specific applications. When the ADC needs to take full advantage of its dynamic performance, to disable the SPI port, usually the SLCK signal, CSB signal, SDIO signal and ADC clock are asynchronous, the noise in these three signals will reduce the conversion performance of the ADC, if other devices use the board When the SPI bus is on, it is recommended that the bus be connected to the AD9257 via the buffer NC7WZ16P6X to prevent these signals from changing during critical sampling periods. The specific design is shown in Figure 8.

Figure 8 AD9257 Serial Port Schematic

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is made into a physical board and simulated. The test results show that the new system has many advantages, such as low cost, small size, low power consumption, simple operation and so on. It also lays a solid foundation for the follow-up non-destructive ultrasound imaging system. The research results of this paper can provide technical support and theoretical guidance for ultrasonic nondestructive testing, and have great practical value.

Acknowledgments

This work was supported by Dongguan Municipal Science and Technology Bureau under grant No. 2016508140.

References

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