Design of a High Power Ampliﬁer for Earth-Moon-Earth ...

FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO

Design of a High Power Amplifier forEarth-Moon-Earth Communications

Pedro Manuel Moreira Teixeira

FINAL VERSION

Mestrado Integrado em Engenharia Electrotécnica e de Computadores

Supervisor: Hugo Miguel Guedes Pereira dos Santos

Co-supervisor: Sérgio Reis Cunha

July 27, 2021

Design of a High Power Amplifier for Earth-Moon-EarthCommunications

Pedro Manuel Moreira Teixeira

Mestrado Integrado em Engenharia Electrotécnica e de Computadores

July 27, 2021

Resumo

Comunicações rádio usando a Lua como repetidor de modo a permitir ligações de longa dis-tância sem linha direta de vista (line of sight), contornando a curvatura da terra são já realizadasdesde meados do século passado. Desde os inícios desta tecnologia, sempre foi necessário con-tornar a forte atenuação de espaço livre do sinal devido à enorme distância que a Lua se localiza eao seu baixo albedo.

Um dos métodos predominantes para tornar possível este tipo de comunicações é a transmissãode sinais de alta potência, que nos primórdios do Moonbouncing estava na ordem dos milhares deWatts, atualmente, com modulações mais complexas e recetores mais avançados é possível serfeita com apenas centenas de Watts, como demonstrado na secção de link budget do documento,continuando um desafio para entusiastas de Radioamadorismo.

Esta dissertação aborda essencialmente o processo de desenvolvimento de um amplificador depotência capaz de produzir 200 W à frequencia de 2.4 GHz com a melhor eficiência e linearidadepossíveis. Para conseguir concretizar o objetivo imposto, uma revisão do estado de arte na áreade desenvolvimento de amplificadores de rádio frequência mostrou ser essencial, estabelecendometodologias de trabalho e métricas para a análise desse mesmo tema. Foi ainda possível deter-minar que classe AB, classe F ou F inverso seriam as tipologias mais indicadas, permitindo altaspotências sem sacrificar demasiado a eficiência em aplicações em que a linearidade do dispositivonão é crítica.

Posto isto, o plano de trabalhos seguiu a forma canónica de desenvolvimento de amplificadoresde potência deste tipo de classes, tendo por base o circuito exemplo presente na datasheet dodispositivo ativo escolhido.

Em todo o processo de desenvolvimento foi usado o software Advanced Design System 2021que tornou possível as várias análises do circuito do amplificador, aliado à ferramenta de simu-lação Momentum, ambas da Keysight Technologies, que permitiu a obtenção de modelos compor-tamentais mais fiáveis nas várias etapas de desenvolvimento, evitando surpresas do ponto de vistade performance após a implementação prática do amplificador.

Diferentes pontos de funcionamento, biasing networks e matching networks foram experimen-tadas de modo a se obter um design estável capaz de cumprir o requisito mínimo de potência omais eficiente possível, sendo na simulação eletromagnética final obtido o requisito mínimo depotência com PAE = 51.6%. Na implementação prática o melhor resultado medido foi de 50.9dBm de potência de saída com 45% de eficiência do PA à frequência de 2.35 GHz.

Durante o processo de desenvolvimento foi essencial uma atitude de compromisso entre a efi-ciência, potência, estabilidade e linearidade do amplificador, sendo cada uma das etapas essencialpara estabelecer o equilíbrio entre cada um desses fatores.

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Abstract

Radio communications using the Moon reflection to overcome the Earth’s curvature in longdistance communication have been in practice for more than 70 years. Since the beginning, a largesignal attenuation due to the enormous distance the signal has to travel and the low albedo of theMoon, is a great challenge to beat.

Usually to make this type of communication possible a great transmission power is required,made possible by the use of high power RF amplifiers. Initially, thousands of watts were required,but with the advances in modulation techniques and better reception systems, the transmitter powerrequirements go as low as hundreds of watts, as shown in the link budget section of this document,remaining, however, relevant problems to tackle amongst the Amateur Radio community.

This thesis documents the development process of a Power amplifier capable of giving 200 Wof power at 2.4 GHz with the best efficiency possible. To fulfill these goals, a revision on the stateof the art of power amplifiers was made, establishing metrics and methodologies to use during thedevelopment. Furthermore, it was determined that a class AB, Class F or inverse class F wouldbe the most interesting topologies, since they allow high power outputs without sacrificing theefficiency in application where the linearity is not critical.

With this is mind, the workflow followed the standard development in this type of classes, us-ing the circuit example present in the transistor’s datasheet as a starting point. During all process,the Advanced Design System 2021 software was the tool used, aided by the Momentum simu-lation system, also by Keysight, allowing the generation of more realistic models of the circuit’sbehavior, thus, avoiding performance deviations at the implementation stage of the real devicewhen compared to the results of the simulated model.

Different bias points, bias networks and matching network configurations were tried in orderto obtain a stable design capable of fulfilling the requirements. In the simulation of the last designthe output power was Pout = 53.25 dBm and with a power added efficiency of PAE = 51.6% at2.4 GHz. The best measured result for the PA were frequency shifted, with a Pout of 50.9 dBm anda PAE of 45% at 2.35 GHz.

Throughout the whole process a compromise mentality between efficiency, power, stabilityand linearity of the amplifier was essential, balancing the different factors into the best performingcircuit of the given application.

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Acknowledgements

While trying to remember everyone, I will start by giving a special thanks to my supervisorHugo Santos that answered all my questions during the realization of this thesis and the necessaryguiding directions to do so. A thanks to my co-supervisor Sérgio Cunha that was always a helpinghand, especially in the last minute tests. The welcoming help from the Bexus team elements alsoneeds to be recognized, specially from Tiago Martins and Bernardo Moreira.

A thank you to all the people from which I keep good memories during my specializationyears, particularly, Sérgio Gonçalves and Tiago Cunha.

A special space in the acknowledgements should also be saved for my family, that alwaysprovided the support I needed during the elaboration of this thesis, as well as during the full 5years of this degree.

A thank you to all my "academic friends", all the 16 of you, for providing unforgettable storiesduring and after class, that made the university experience mean a lot more.

Last but not the least important, I would like to thank my girlfriend Vitória for all the supportprovided, specially in the difficult days where things did not went according to plan, acting as mysafe shelter.

Pedro Teixeira

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“Don’t believe everything you read on the internet just because there is a quote with a picturenext to it”

Abraham Lincoln

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Contents

Resumo i

Abstract ii

1 Introduction 11.1 Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Literature review 42.1 Link Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1.1 Antenna theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1.2 Friis transmission formula . . . . . . . . . . . . . . . . . . . . . . . . 72.1.3 Radar equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72.1.4 Other losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1.5 Noise theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82.1.6 Synthetic aperture radar . . . . . . . . . . . . . . . . . . . . . . . . . . 102.1.7 EME modulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.2 Active RF devices history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122.3 RF fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.3.1 Two-Port Network Parameters . . . . . . . . . . . . . . . . . . . . . . . 162.3.2 Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4 Power Amplifier characterization . . . . . . . . . . . . . . . . . . . . . . . . . 212.4.1 Load Pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.4.2 Loadline Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212.4.3 Transistor operating point . . . . . . . . . . . . . . . . . . . . . . . . . 242.4.4 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.5 Power Amplifier metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.5.1 Amplifier Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272.5.2 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282.5.3 Linearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292.5.4 Gain compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302.5.5 Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . 312.5.6 IP2 and IP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.6 Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332.6.1 Class A B AB and C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352.6.2 Class D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

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CONTENTS vi

2.6.3 Class E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372.6.4 Class F and F-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

2.7 Efficiency techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392.7.1 Envelope Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392.7.2 Envelope Elimination and Restoration . . . . . . . . . . . . . . . . . . . 402.7.3 Load Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

2.8 Power Amplifier Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412.8.1 Push-Pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412.8.2 Multistage PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

2.9 State of the art high power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 432.10 Proposed solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

2.10.1 Link Budget Realization . . . . . . . . . . . . . . . . . . . . . . . . . . 442.10.2 Amplifier solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3 PA design steps and simulations 503.1 Active device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.1.1 Active device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.1.2 Active device interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

3.2 Layout generation and simulation . . . . . . . . . . . . . . . . . . . . . . . . . 533.3 Operation point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543.4 Surrounding networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.4.1 Power Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563.4.2 Bias network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.5 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.5.1 Schematic simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.5.2 Layout simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

3.6 Load Pull . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.7 Matching Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.7.1 Output matching network . . . . . . . . . . . . . . . . . . . . . . . . . 693.7.2 Input matching network . . . . . . . . . . . . . . . . . . . . . . . . . . 693.7.3 Final matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.8 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713.9 Monte Carlo Simulation and yield analysis . . . . . . . . . . . . . . . . . . . . . 723.10 AM-PM distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753.11 Board generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4 PA practical validation 784.1 Implementation difficulties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784.2 DC characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804.3 Small signal measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824.4 Large signal measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

5 Conclusions 945.1 Objectives accomplishment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945.2 Difficulties encountered . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 945.3 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 955.4 Final Remarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Bibliography 97

List of Figures

1.1 Earth Moon Earth link illustration at 2.4 GHz (adapted from [2]) . . . . . . . . . 1

2.1 Cascaded amplifier configuration [4, Chapter 10] . . . . . . . . . . . . . . . . . 102.2 Power output to frequency [4, Chapter 11] . . . . . . . . . . . . . . . . . . . . . 132.3 Different technology’s performance . . . . . . . . . . . . . . . . . . . . . . . . 152.4 Power amplifier simplistic model (image adapted from [18]) . . . . . . . . . . . 152.5 Two-Port power gains configuration, with S meaning source and L meaning Load

[19, Chapter 2] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.6 S parameters for two-port networks. [20, ch 3] . . . . . . . . . . . . . . . . . . 172.7 Generic L-matching network sections (images adapted from [20, Chapter 5]) . . 192.8 Smith chart mapping from the Z plane [20, Chapter 5] . . . . . . . . . . . . . . 202.9 Adding components using ZY Smith chart. [20, Chapter 5] . . . . . . . . . . . . 212.10 Class A configuration [26, Chapter 2] . . . . . . . . . . . . . . . . . . . . . . . 222.11 Class A linear power amplifier with high and low resistance load [26, ch 2] . . . 222.12 Load–pull contours corresponding to a class B PA with output power (PStep = 1

dB and PMax=55 dBm ) and efficiency (ηStep = 5 and ηMax = 78.5% ) [27] . . . . 232.13 I-V curve, defined as "soccer pitch" in [28] . . . . . . . . . . . . . . . . . . . . . 242.14 Two port network configuration [29, Chapter 3 ] . . . . . . . . . . . . . . . . . . 252.15 Smith Chart with stable and unstable regions (left to right) in the ΓS plane [29,

Chapter 3] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262.16 1-db compression point representation[20, Chapter 1] . . . . . . . . . . . . . . . 312.17 Frequency spectrum of third-order non-linearity system with two-tone sinusoidal

inputs [19, Chapter 1] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322.18 Intermodulation Distortion (IMD), IP2, IP3, and gain compression [19, Chapter 1] 322.19 Load lines and bias points for linear amplifiers [20, Chapter 1] . . . . . . . . . . 332.20 Class A, B, and C. typical configuration [20, Chapter 1] . . . . . . . . . . . . . . 342.21 AB amplifier excursion [20, Chapter 1] . . . . . . . . . . . . . . . . . . . . . . 362.22 A to C class comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372.23 Class E simplified configuration [20, Chapter 1] . . . . . . . . . . . . . . . . . . 382.24 Class E simplified configuration [20, Chapter 1] . . . . . . . . . . . . . . . . . . 382.25 Envelope tracking behavior of DC voltage [33] . . . . . . . . . . . . . . . . . . 392.26 Envelope tracking implementation [24, Chapter 9] . . . . . . . . . . . . . . . . 392.27 Envelope Elimination and Restoration implementation [31, Chapter 9] . . . . . . 402.28 Block diagram of the Doherty PA [24, Chapter 9] . . . . . . . . . . . . . . . . . 402.29 Typical push–pull configuration [19, Chapter 1] . . . . . . . . . . . . . . . . . . 422.30 RF performance of 500W AlGaN/GaN Vds=65V, Idsq=2.0A, Freq=1.5GHz [35] . 432.31 Interstage match for driver-PA [26, Chapter 13] . . . . . . . . . . . . . . . . . . 432.32 Approximation of the obtained SAR image . . . . . . . . . . . . . . . . . . . . 47

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LIST OF FIGURES viii

3.1 Transistor ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513.2 Circuit example presented in the datasheet for 2.4 GHz [51] . . . . . . . . . . . 523.3 Transistor footprint integration . . . . . . . . . . . . . . . . . . . . . . . . . . . 533.4 DC IV simulation with the transistor model . . . . . . . . . . . . . . . . . . . . 553.5 DC IV simulation of the transistor model with footprint . . . . . . . . . . . . . . 563.6 Transmission line equivalent of the WPD . . . . . . . . . . . . . . . . . . . . . 573.7 Wilkinson Power Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.8 Wilkinson Power Divider magnitude and phase balance between each branch (S21

and S31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.9 Capacitor impedance and ESR obtained from [57] . . . . . . . . . . . . . . . . . 603.10 First iteration of the circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613.11 Stability analysis first iteration results, stability factors on the left and gain on the

right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.12 Stability first iteration layout, stability factors on the left and output voltage on the

right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633.13 First stable design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653.14 Stability results, stability factors on the left and output voltage on the right . . . . 663.15 Hybrid circuit layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663.16 Hybrid design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673.17 Hybrid circuit stability circles from from 1 Hz up to 16 GHz . . . . . . . . . . . 673.18 Hybrid circuit load pull maximum PAE point obtained with 38.8 dBm of input power 683.19 Hybrid circuit load pull power delivered and efficiency contours with 38.8 dBm of

input power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683.20 Hybrid circuit load selection with 3 dB of gain compression . . . . . . . . . . . 683.21 Ideal output matching network configuration . . . . . . . . . . . . . . . . . . . . 693.22 Output matching network microstrip design . . . . . . . . . . . . . . . . . . . . 703.23 Final matching optimization, with intermediate matching networks in schematic

form inside the HYBRID_Sample_PA block as shown is figure 3.15 . . . . . . . 703.24 Harmonic content of final matching optimization, with a -147 dBm of DC isolation 713.25 Final layout for simulations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713.26 Efficiency and gain versus input power on the left and output power on the right . 713.27 Fundamental, first and second harmonic powers . . . . . . . . . . . . . . . . . . 723.28 S Parameters results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723.29 Performance comparison between layout and schematic conversion . . . . . . . . 733.30 Monte Carlo analysis output power efficiency and power delivered with 1000 iter-

ations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743.31 Monte Carlo analysis harmonic power relative to the carrier . . . . . . . . . . . . 743.32 Monte Carlo analysis S(2,1) variation relative to the nominal value . . . . . . . . 753.33 AM-PM distortion for operation frequency and neighbours . . . . . . . . . . . . 763.34 Layout tuning techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763.35 Boards ready to print layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.1 Stability results of the miss placed resistor layout, stability factors on the left andoutput voltage on the right . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.2 Harmonic power difference, between previous design and the miss placed resistordesign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

4.3 Normalization of the layout using copper tape . . . . . . . . . . . . . . . . . . . 804.4 Assembled design with 50 Ω terminations . . . . . . . . . . . . . . . . . . . . . 804.5 DC IV comparison between simulation and measured . . . . . . . . . . . . . . . 81

LIST OF FIGURES ix

4.6 Stress test of current consumption, being blue and orange the first and second trialsrespectively without active cooling along with yellow the last trial with active cooling 82

4.7 Implemented resistive divider on protoboard . . . . . . . . . . . . . . . . . . . . 824.8 Small signal measurement setup, with the VNA (A), PA (B), attenuator (C), power

supply for the drain bias network (D), power supply for the resistive divider (E)and resistive divider (F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.9 S21 Measured at malfunction VNA with nominal bias conditions . . . . . . . . . 834.10 S Parameters measurement with nominal bias conditions . . . . . . . . . . . . . 844.11 S Parameters measured at right and simulated at left with nominal bias conditions 844.12 Tektronix attenuation chain S parameters . . . . . . . . . . . . . . . . . . . . . . 854.13 50 m RG-58 coaxial cable S parameters . . . . . . . . . . . . . . . . . . . . . . 864.14 Driver Gain and PAE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 864.15 Large signal measurements setup, with the signal generator (A), Driver (B), PA

(C), RG-58 coaxial attenuation cable (D), spectrum analyzer (E), external cooling(F), power supply for the driver (G1), power supply for the resistive divider (G2),and power supplies for PA’s drain bias network (G3-G8) . . . . . . . . . . . . . 87

4.16 Large signal measurements results with 2 V of gate voltage at 2.464 GHz . . . . . 874.17 First driver tested . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884.18 DC IV comparison between simulation and measured with new transistor mea-

sured at 2 V to 1.6 V with steps of 0.1 V . . . . . . . . . . . . . . . . . . . . . . 894.19 S Parameters measurement with nominal bias conditions using the new transistor 894.20 Output power measurements versus frequency for 0 dBm (orange), 10 dBm (blue),

and 15 dBm (red) of input power . . . . . . . . . . . . . . . . . . . . . . . . . . 904.21 S Parameters measurement with nominal bias conditions using the 2 DC block

capacitors at the output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904.22 Device’s performance curves (with a sweeping input power from -20 dBm to 15

dBm) for 2.4 GHz at the left (a, c, e) and 2.35 GHz at the right (b, d, f), being theyellow traces relative to the chain, the blue traces relative to the Driver, and redrelative to the PA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

4.23 Performance curves (with a sweeping frequency from 2.25 GHz to 2.65 GHz ) ofthe chain at the left (a, c, e) with 13 dBm (orange), 15 dBm (blue) and 16 dBm(red) of input power, as well as the system components’ performance at the right(b, d, f) for 15 dBm of input power, being the yellow traces relative to the completechain, the blue traces relative to the driver, and red relative to the PA . . . . . . . 92

List of Tables

2.1 State of the art high power amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 432.2 Link Budget Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442.3 Transmission Losses for a Radar Cross Section of 6,92E+9 m2 . . . . . . . . . . 452.4 Noise Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462.5 Link Budget Calculation EME . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.1 Substrate characteristics obtained from [54] . . . . . . . . . . . . . . . . . . . . 533.2 Tolerance values used in Monte Carlo Simulation with a Gaussian distribution . . 73

x

Abreviations and Acronyms

PA Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

EME Earth Moon Earth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SNR Signal to Noise Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

RADAR Radio Detection and Ranging . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

PAMOR Passive Moon Relay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

TX Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

NRA Núcleo de Radio Amador (Amateur Radio Organization) . . . . . . . . . . . . 2

FEUP Faculdade de Engenharia da Universidade do Porto . . . . . . . . . . . . . . . 2

TWT Traveling Wave Tube . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

BWO Backwards Wave Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CFA Crossed Field Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

EIRP Equivalent Isotropic Radiated Power . . . . . . . . . . . . . . . . . . . . . . . 7

RCS Radar Cross Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

FET Field Effect Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

BJT Bipolar Junction Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CAD Computer Aided Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

DUT Device Under Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

IMD Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

THD Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

SAR Synthetic Aperture Radar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

OOK On-Off Keying . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

CW Continuous Wave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

ECC Error Correcting Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

RF Radio Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

TWT Traveling Wave Tube . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

BWO Backward Wave Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

CFA Crossed-Field Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

BJT Bipolar Junction Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

MESFET Metal–Semiconductor Field-Effect Transistor . . . . . . . . . . . . . . . . . . 13

HBT Heterojunction Bipolar Transistor . . . . . . . . . . . . . . . . . . . . . . . . 14

xi

FET Field Effect Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MOSFET Metal Oxide Semiconductor FET . . . . . . . . . . . . . . . . . . . . . . . . . 14

HEMT High Electron Mobility Transistor) . . . . . . . . . . . . . . . . . . . . . . . . 14

GaAs Galium Arsenide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Si Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SiGe Silicon Germanium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

AlGaN/GaN Aluminium Gallium Nitride . . . . . . . . . . . . . . . . . . . . . . . . . . 14

GaN Galium Nitride . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MICS Microwave Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 14

LDMOS Laterally Diffused MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

VNA Vector Network Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

SOLT Short Open Load Through . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

TRL Through-Reflect-Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

DC Direct Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

AC Alternated Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

IMD Intermodulation Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

THD Total Harmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

IP3 Third-Order Intercept Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

IP2 Second-Order Intercept Point . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

VM Voltage Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

CM Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

PRF Pulse Repetition Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

LNA Low Noise Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

ADS Advanced Design System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

WPD Wilkinson Power Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

ESR Equivalent Series Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

EM Electromagnetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

SMD Surface Mounted Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

OMN Output Matching Network

IMN Input Matching Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

PAE Power Added Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

SMA SubMiniature version A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

PCB Printed Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

HB Harmonic Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

TOSM Through, Open, Short, Match . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

ESD Electrostatic Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

W-CDMA Wide-Band Code-Division Multiple Access . . . . . . . . . . . . . . . . . . . 75

PAR Peak to Average Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Chapter 1

Introduction

The twentieth century was a time of great development of transatlantic communications. In

the early days, prior to 1926, only a few telegraph cables were laid, the number was limited and

they were unable to support voice communications. Alternatives that used radio wave bouncing

were explored, such as reflections from large balloons and the moon itself [1].

The first successful Earth Moon Earth (EME) communication was made possible in 1946,

where a team of scientists in New Jersey was able to detect the first radio signals reflected from

the Moon, the so-called project Diana. Using a 3 kW power transmitter and a large phased array

antenna with a 30 dB gain, the echo of the 112 MHz signal was captured [2, 3]. Another honorable

mention in this field is the American project Passive Moon Relay (PAMOR), which in the fifties

aimed to recover Soviet Radar signals reflected from the Moon, this time using a 67 by 80 meter

parabolic antenna, and 750 W of power, and project Moonbeam that allowed amateur radio EME

communications, allowing the use of the Arecibo Observatory in Puerto Rico, with a 300 meter

dish, firstly in the sixties and more recently in 2010 [3].

Figure 1.1: Earth Moon Earth link illustration at 2.4 GHz (adapted from [2])

1

Introduction 2

1.1 Context

Although the usage of the moon to overcome the Earth’s curvature between two points is less

and less relevant accounting the number of man-made satellites in orbit, the challenge continues

to be very popular amongst the amateur radio community. With this in mind, the Faculdade

de Engenharia da Universidade do Porto (FEUP)’s Núcleo de Radio Amador (Amateur Radio

Organization) (NRA) is also trying to make EME communications with the available resources.

The difficulty of using the moon as a repeater is clear once we analyze the simplified link of

Figure 1.1. The emitted signal is highly attenuated due to the enormous distance from the Earth to

the Moon and the low Moon albedo (6 to 7%).

1.2 Motivation

To solve the high attenuation problem, several approaches can be taken:

• Highly directive antennas;

• Powerful transmitting amplifiers;

• Very Low noise amplifiers;

• Highly complex signal;

• Narrow band signal.

Given the fact that the most directive antenna available is only a 3 meter dish, and that, ideally,

the projected system must be capable of both capturing radar images and performing Morse or

voice point to point communication, efforts must be made to transmit high power, have a good re-

ception system, and implement complex signals, that are associated with considerable processing

gains.

The purpose of this thesis makes part of the NRA to-do list, which includes the amplification

task, i.e, design of a transmission amplifier chain with transmission power in the order of hundreds

of watts, allowing the link to be possible.

1.3 Objectives

Given the motivation, the objectives of this thesis are the following:

1. Design, simulation, manufacturing, and testing of a high power amplifier (greater or equal

than 200 W) capable of operating in S or L band.

2. Design, simulation, manufacturing, and testing of a driver amplifier that is able to increase

the power of a 20 dBm input all the way up to the required input power of the high power

amplifier.

1.4 Structure 3

The success of this thesis is measured essentially by these objectives, where the first is seen

as the minimum requirement. However, given the motivation of this thesis, the author considers

the implementation of the amplifier chain in a moon bouncing application as a personal objective,

proving the usefulness of the developed product.

1.4 Structure

This document’s structure is divided by chapters, each one with its one purpose.

In Chapter 1, it is explained the context, goals and motivation for this dissertation.

In Chapter 2 there is a presentation of the state of the art. Firstly, a brief description of link

budget theory and RF circuits fundamentals is provided, which will facilitate the characterization

of the problem task. After that, the types, architectures and techniques associated with power

amplifiers are presented and lastly, an evaluation of the link budget to clarify the definition of the

problem. To close out the section, a solution to solve the problem is proposed.

In chapter 3 the design of the amplifier is exposed where the several design steps where fol-

lowed, with multiple design iterations until a circuit that fulfilled the minimal requirements was

encountered, all this in simulation environment.

Chapter 4 details the practical implementation of the developed design and its results, while

comparing them to the simulations and other reference materials.

In the last chapter (chapter 5) several conclusions are pointed out, as well as the future work

to be done and possible improvements to the final product.

A list of the reference material used throughout this thesis can be found at the end of the

document.

Chapter 2

Literature review

2.1 Link Budget

In this subsection, a brief explanation about the link budget related matters for an EME con-

figuration will be presented. Initially, it is provided an explanation of antenna topics, followed by

propagation loss concepts, radar theory, other losses and noise theory.

2.1.1 Antenna theory

Antennas can be viewed as a converter of RF guided waves into a plane wave propagating

in free space. This device is known to be bidirectional by nature so, it also has the capability to

capture free space waves into guided waves [4, Chapter 14].

Without entering in details on Maxwell’s equations, Pozar shows that in the far-field of the

antenna, the distance at which the ideal planar phase front of a plane wave, the direction of the

energy flux, the radiated power, Prad, to the surrounding space can be written as

Prad =∫ 2π

φ=0

∫π

θ=0Savg · rr2 sinθdθdφ =

∫ 2π

φ=0

∫π

θ=0U(θ ,φ)sinθdθdφ (2.1)

where Savg is the time-average Poynting vector, calculated from the Magnetic and Electric fields.

And where U(θ ,φ) is the radiation intensity in a given direction that is being integrated over a

unit sphere.

2.1.1.1 Radiation Pattern

[5] states that the radiation pattern is defined as "a mathematical function or a graphical rep-

resentation of the radiation properties of the antenna as a function of space coordinates. In most

cases, the radiation pattern is determined in the far-field region and is represented as a function

of the directional coordinates. Radiation properties include power flux density, radiation intensity,

field strength, directivity, phase or polarization". This way, the radiation pattern can be plotted

4

2.1 Link Budget 5

from the pattern functions, Fθ (θ ,φ) and Fφ (θ ,φ), that are present in the definition of the electric

field and magnetic fields [4, Chapter 14].

2.1.1.2 Directivity

Directivity is defined "as the ratio of the radiation intensity in a given direction from the an-

tenna to the radiation intensity averaged over all directions. The average radiation intensity is

equal to the total power radiated by the antenna divided by 4π . If the direction is not specified, the

direction of maximum radiation intensity is implied" [5].

Considering Umax as the maximum radiation intensity and Uavg as the overall average radiation

intensity, we get equation (2.2). It can also be expressed in order of the radiated power, which is

the integration of the radiation intensity of all space.

D =Umax

Uavg=

4πUmax

Prad=

4πUmax∫π

θ=0∫ 2π

φ=0U(θ ,φ)sinθdθdφ(2.2)

2.1.1.3 Radiation efficiency

Radiation efficiency of an antenna is defined by "the ratio of the desired output power to the

supplied input power" [4, Chapter 14].

ηrad =Prad

Pin=

Pin −Ploss

Pin= 1− Ploss

Pin(2.3)

With Prad as the power radiated by the antenna, Pin the power supplied to the input of the antenna,

and Ploss, the power lost in the antenna.

2.1.1.4 Aperture efficiency

Aperture efficiency, ηap, of an antenna is defined as "the ratio of the maximum effective area

Aem of the antenna to its physical area Ap", where the maximum effective area is the maximum of

the power delivered to the load divided by the power density of incident wave, from the reception

point of view [5].

ηap =Ae

Aph(2.4)

Generically, the effective area (aperture), Ae is defined by [5] as “the ratio of the available

power at the terminals of a receiving antenna to the power flux density of a plane wave incident

on the antenna from that direction, the wave being polarization-matched to the antenna. If the

direction is not specified, the direction of maximum radiation intensity is implied".

Ae =Pr

Sr(2.5)

Literature review 6

It is also shown that the maximum effective aperture of any antenna is related to its maximum

directivity [5, Chapter 2].

Aem = ηrad

(λ 2

4π

)Dmax (2.6)

2.1.1.5 Gain and realized Gain

Gain of an antenna is defined as “the ratio of the intensity, in a given direction, to the radiation

intensity that would be obtained if the power accepted by the antenna were radiated isotropically.

The radiation intensity corresponding to the isotropically radiated power is equal to the power

accepted (input) by the antenna divided by 4π" [5]. This is typically referred as the relative gain

because it is defined with respect to a reference, usually an isotropic antenna.

G(θ ,φ) =4πU(θ ,φ)

Pin( lossless isotropic source )(2.7a)

G(θ ,φ) = ηrad

[4π

U(θ ,φ)

Prad

]= ηradD(θ ,φ) (2.7b)

Gmax = ηradDmax (2.7c)

Taking equation (2.3) and (2.2) one can obtain (2.7a). When the direction is not stated, the

power gain is usually taken in the direction of maximum radiation (2.7b). In [5] it is also defined

another gain, the realized gain, Gre, that takes into account the reflection/mismatch losses (due to

the connection of the antenna element to the transmission line that connects to it).

Gre = G(1−|Γ|2) (2.8)

In a perfect match to the transmission line, Γ = 0, as it will be shown in the RF fundamentals

section. In the mentioned case, the realized gain corresponds to the relative gain.

Combining (2.7c), (2.6) and (2.6), one can also write the gain in terms of the physical area of

the antenna Aphy.

G = ηapηrad4πAph

λ 2 (2.9)

2.1.1.6 Equivalent isotropic radiated power

EIRP is the power input that a lossless isotropic antenna would require to obtain the same

maximum power density in the far-field of the antenna under test. Results from the product of the

power input come in Watts (W), with the isotropic antenna gain.

EIRP = PtGt (2.10)

EIRP can be expressed in Watts, dB relative to one Watt (dBW) or relative to one milliwatt (dBm).

For more details about this antenna subsection, consider that the literature used was [3–5] .

2.1 Link Budget 7

2.1.2 Friis transmission formula

In a common configuration, the transmitter and the receiver are separated by a given distance

R with Transmitter (TX) radiating according to its radiation pattern.

If one assumes that the RF devices are pointed in their maximum directivity direction, and

considering that an eventual misalignment is later compensated via a loss term, it can be said that

the average power that reaches the receiver is the Equivalent Isotropic Radiated Power (EIRP)

divided by spherical cap area at that distance. Another interpretation is the power density of

an isotropic antenna at a distance R, times the gain relative to said isotropic antenna. [6], [4,

Chapter 14]

Savg =GtPt

4πR2 W/m2 (2.11)

Taking in mind the definition of the effective aperture area, the power in the receiver can easily be

given as

Pr = AeSavg =GtPtAe

4πR2 =GtGrλ

2

(4πR)2 Pt W (2.12)

From (2.12) one can derive the free space losses that express the attenuation effect of the power

spreading across the space [4, Chapter 14]

LFSL =

(4πR

λ

)2

(2.13)

2.1.3 Radar equation

When point-to-point communications are made possible by an intermediate passive reflector,

it is fundamental to study the Radio Detection and Ranging (RADAR) equation. For this subject,

refer to [3, 4] for more information.

The fundamental concept to be presented is the Radar Cross Section (RCS), which is defined

as "the ratio of the scattered power in a given direction relative to the incident power density", and

expressed in square meters.

σ =Ps

Stm2 (2.14)

Taking equation (2.14) and considering that the transmitter power density at the reflector is just

like in expression (2.11), the radar equation results in equation (2.15)

Pr =PtG2λ 2σ

(4π)3R4 (2.15)

A useful rearrange of equation (2.15) can express the maximum distance an object can be posi-

tioned to make the link possible, expressing the maximum range, Rmax, of the system.

Rmax =

[PtG2σλ 2

(4π)3Pmin

]1/4

(2.16)

Literature review 8

2.1.4 Other losses

EME communication systems have losses associated with them that need to be taken into

account [3]. One can notice losses regarding the antenna, related with the conductor and di-

electric material. Losses regarding the network that connects the system to the antenna can be

ohmic/dissipative or mismatch related [5].

Another loss can come from the fact that the antenna will most likely not be perfectly pointed

in its maximum direction, suffering depointig loss, since the gain decreases as one moves away

from the point of maximum.

A last concern is that the received wave when crossing the ionosphere suffers from depolar-

ization, meaning that some power will be transferred to the perpendicular polarization causing a

degradation of the antenna’s gain, since the cross-polarization gain is usually inferior to the co-

polarization gain [5]. For more information about other losses associated with EME systems refer

to [7, Chapther 3] and [3].

2.1.5 Noise theory

To understand the sensibility of a receiver, it is important to mention that it is essentially a

competition with receiver noise signal. In a noiseless receiver, the minimum energy would be

theoretically infinite [8].

The following analysis on noise theory was inspired in [4, Chapter 10].

2.1.5.1 Noise temperature

A given device can have various types of noise associated: thermal noise, resulting from the

charges vibrating within the device, shot noise, flicker noise, plasma noise, and quantum noise.

Typically, a RF system is dominated by what can be globally evaluated as white noise.

A good modelling of a random noise source is the thermal noise of a resistor R at a temperature

T , with a measure of noise in a given bandwidth B, given by (2.17), where k = 1.380×10−23 J/K

is the Boltzmann constant.

No = kT B (2.17)

In a passive device, the equivalent noise temperature can then be calculated by (2.18a), which

represents the temperature a resistor would have to be to produce the same noise power.

Te =No

kB(2.18a)

Te =No

GkB(2.18b)

For an active device, one can isolate the noise from the device itself, creating a configuration where

we have the noise source resistance followed by an ideal amplifier with gain G, thus the output

2.1 Link Budget 9

noise is the noise in (2.17) times the device gain. This way, its temperature has an extra G term in

the denominator.

2.1.5.2 Noise figure

Noise figure is another way to characterize a component. It is a measure of the degradation in

the Signal to Noise Ratio (SNR) between the input and output of the component.

F =Si/Ni

So/No= 1+

Te

T0≥ 1 (2.19)

It can also be written as a relation of the device equivalent temperature and the input temperature,

T0.

The equivalent noise temperature Te, can also be solved in terms of F T0. In a noiseless

network, F = 1(0 dB), giving Te = 0.

Te = (F−1)T0 (2.20)

2.1.5.3 Lossy medium

The particular case of a signal across a lossy medium is of interest to study. The output power

of said medium will be given by the sum of the output power, assuming a clean gain/attenuation,

plus the thermal noise of the medium itself. This way, one can express

No = kT B = GkT B+GNadded (2.21)

And since the gain of said medium is less than one, G = 1/L < 1, the noise added is

Nadded =1−G

GkT B = (L−1)kT B . (2.22)

With this in mind, one can say the output noise temperature is given by

Tout = LTin +(1−L)T0. (2.23)

An antenna is a particular case of a lossy device, so its temperature can be written as

TA =Tb

L+

(L−1)L

Tp = ηradTb +(1−ηrad)Tp (2.24)

where Tb is the brightness temperature, resulting of an integration of all the noise sources an

antenna can see, and Tp is the physical temperature.

Tb =

∫ 2π

φ=0∫

π

θ=0 TB(θ ,φ)D(θ ,φ)sinθdθdφ∫ 2π

φ=0∫

π

θ=0 D(θ ,φ)sinθdθdφ(2.25)

Literature review 10

2.1.5.4 Amplifier chain

Considering two amplifiers in the configuration of figure 2.1, one can simplify it to a single

Figure 2.1: Cascaded amplifier configuration [4, Chapter 10]

amplifier, by summing No with amplified N1 to get the new No,

No = G2N1 +G2kTe2B = G1G2kB(

T0 +Te1 +1

G1Te2

)= G1G2kB(Tcas +T0) (2.26)

where Tcas is the noise temperature of the cascade system, expressed as

Tcas = Te1 +1

G1Te2 (2.27)

This analysis can be extrapolated to more stages getting the following noise figure, where one can

easily identify that the first amplification level is the more critical, noise wise.

Fcas = F1 +F2−1

G1+

F3−1G1G2

+ · · · (2.28)

Tcas = Te1 +Te2

G1+

Te3

G1G2+ · · · (2.29)

2.1.6 Synthetic aperture radar

A short overview of Synthetic Aperture Radar (SAR) will be given here, with special attention

to range and azimuth resolution and compression gains.

2.1.6.1 SAR operation

SAR is a variation of conventional RADAR that uses the motion of the radar antenna over a

target region to achieve better spatial resolution than conventional beam-scanning radars. It does it

by combining measurements of different positions with specific algorithms that enhance the data

per target [9, Chapter 2].

2.1.6.2 Fundamental variables

In a SAR configuration several pulses of a given duration Tp, are transmitted with a pulse

repetition frequency PRF , resorting to an antenna with area A and side La. The received echoes

are collected to be processed during an integration time, Ti [10, Chapter 1].

2.1 Link Budget 11

2.1.6.3 Azimuth resolution and Range resolution

It is shown in [10, Chapter 4] that the maximum distinction in the direction of movement of

the SAR antenna is given by

δaz =La

2(2.30)

In the same chapter, it is also shown that the range resolution in the direction perpendicular to the

direction of the antenna, is given by

δR =c

2B(2.31)

being B the bandwidth of the signal, and c the speed of light.

2.1.6.4 Processing Gain

To better understand SAR processing gain related matter, please refer to [10, Chapter 7] where

this section was inspired.

The collected data is then processed by a series of algorithms that improve the Signal to Noise

Ratio by combining the different echoes of the same location.

This processing gain, Gproc, is a combination of the pulse compression gain, Gpulse , and the

azimuth compression gain, Gazimuth .

Gproc = Gpulse +Gazimuth (2.32)

The pulse compression gain is given by the product of the signal length in time, Tp,, by its band-

width B.

Gpulse = TpB (2.33)

The azimuth compression gain, Gazimuth is given by the Pulse Repetition Frequency (PRF) multi-

plied by the Radar Integration Time, Ti

Gazimuth = TiPRF (2.34)

2.1.7 EME modulations

EME signals are always weak, so modulations need to be chosen in order to get the best

out of it. As stated in [11] On-Off Keying (OOK), Morse code is an excellent general purpose

communication mode that performs well in weak signal conditions. Some operating procedures

for Continuous Wave (CW) consist on repeating the message so that fragments of the message can

be reassembled.

In the late twentieth century, digital modulations were popularized. In these modulations

there is redundancy, that is sent along with the message. That redundancy associated with Error

Correcting Codes (ECCs) was proven to be way more efficient than the simple repetition used in

Morse.


An example is the JT65 transmission mode that is present in the 2001 WSJT software program,

popular amongst the radio amateur community [12]. This mode uses structured messages to allow

lossless compression of information, using 64-FSK, Frequency-shift keying, plus a fundamental

frequency for synchronization purposes, being a constant envelope system. This has particular

relevance to this thesis because, in a constant envelope system non linearities on the PA gain are

more tolerable. In the same document, it is also shown that with the JT65 mode, one can receive

messages with 2.5 kHz, with signal to noise ratios of about−24 dB, that according to [11] is close

to a 10 dB gain compared to a typical CW EME configuration.

Taking into account the concepts presented in this section, one can analyze the EME link

budget either for narrow band communications or for larger band Synthetic Aperture Radar. Both

cases will be analyzed in section 2.10 of this chapter.

2.2 Active RF devices history

The history of Radio Frequency (RF) active devices is long, however, it can be divided into

two main chapters, being that the breakthrough was the appearance of solid state RF power devices

in the late sixties.

2.2.0.1 Vacuum devices

From the twenties until the mid-seventies, the amplification of RF signals was dominated by

vacuum tube Power Amplifiers (PAs), inspired by Lee de Forest’s triode audion, an amplification

vacuum tube where a small electrical signal applied to the grid could control a larger current across

the device [13].

Along the years, vacuum PAs evolved having a vast type of geometries, nevertheless the fun-

damental behavior is still the same.

The process occurs in an envelope where an electron beam interacts with an electromagnetic

field. Firstly, a hot cathode generates a stream of electrons by thermionic emission, this stream

is then focused by the anode that requires a large bias voltage. If pulsed modulation is required,

a modulating electrode is placed between anode and cathode, putting together the electron gun.

According to the type of interaction of the electron beam with the field, vacuum tubes can be

classified as linear-beam or crossed-field whether the focusing field is parallel or perpendicular to

the accelerating electric field. The stability on the tube can be labelled as oscillator or amplifier.

Most of the vacuum devices have the duality between amplifier and oscillator. A good example

are klystrons, linear-beam tubes, that in the amplifier configuration the RF input is accepted in a

resonating cavity. That signal travels to the next cavities, being amplified in each one of them.

These have a practical limit of four cavities, giving about 90 dB of gain and several kilowatts peak

power. Klystrons are known by their high quality factors that make them have very low noise

levels. However, this affects their operation bandwidth making it very narrow. To overcome this

problem, the Traveling Wave Tube (TWT) and Backward Wave Oscillator (BWO) configurations

can be used, having better frequency range but a degraded efficiency.

2.2 Active RF devices history 13

In the Crossed-field tubes the cylindrical cathode is surrounded by a cylindrical anode with

resonators along the inside of its periphery. A rotating cloud of electrons results from the applied

magnetic field provoking, similar to the linear field, electron bunching and transferring power to

the outside via probe, loop or aperture couplers.

Examples of Cross-field tubes are: magnetrons, with good efficiency and great power output,

but usually noisy and incapable of maintaining phase coherence in a burst operation; Crossed-

Field Amplifiers (CFAs), the TWT equivalent of cross-field; and Gyratrons optimal for high output

power at higher frequencies [4, Chapter 11]

.

(a) Vacuum tube amplifiers (b) Vacuum tube amplifiers vs solid state

Figure 2.2: Power output to frequency [4, Chapter 11]

Figure 2.2 presents an essential result that, despite many of the vacuum amplifier technolo-

gies being discovered before the solid state ones, the first still have an astonishing output power

capability, sometimes unobtainable by the solid state.

Nowadays, most of RF amplification is made possible by solid state, avoiding the need to

operate at great voltages that require transformers, making the design a lot more bulky, more

expensive, and more prone to mechanical damage and aging.

2.2.0.2 Solid State devices

From the sixties to the seventies, RF engineers made efforts to improve the 1947 Bipolar Junc-

tion Transistor (BJT). The technology evolved, but up until the late seventies the only transistor

types available were BJT and Metal–Semiconductor Field-Effect Transistor (MESFET) [14].

It is important to take a break and mention a transistor domain division. One can divide three

terminal semiconductor devices as junction transistors or field effect transistors, depending on the

said transistor’s behavior.

The junction transistor is a semiconductor device with doping zones, n and p, that when dis-

posed in a npn or pnp configuration allows that a small injection current controls a much larger

one, usually cheaper, comparatively to their counterparts field effect transistors.


Known configurations are the bipolar junction transistor BJT Heterojunction Bipolar Transis-

tor (HBT), being the latter an adaptation of the first, achieving higher operating frequencies [4,

Chapter 11].

The other type that will be discussed is Field Effect Transistor (FET), a transistor that controls

the current flow with the application of an electric field. Once again varying the properties, many

forms are recognised, comprising the Metal Oxide Semiconductor FET (MOSFET), the High

Electron Mobility Transistor) (HEMT), MESFET.

The initial semiconductor material used was Galium Arsenide (GaAs), since then, new ma-

terial properties and applications were studied. Examples of materials were Silicon (Si), Silicon

Germanium (SiGe), and others like Aluminium Gallium Nitride (AlGaN/GaN), that in a HEMTs

configuration possess high breakdown voltage, which allows large drain voltages, an excellent

characteristic to power amplifier transistors [15]. In spite of the fact that GaAs MESFETs are

among the most commonly used transistors for microwave and millimeter waves, the high power

capacity of the Galium Nitride (GaN) makes them the optimal solution high power RF and mi-

crowave amplifiers [4, Chapter 11].

The tendency of the microwave technology is to have more complex devices, more efficient,

more portable, and cheaper, moving towards Microwave Integrated Circuits (MICS) architecture.

There is great history behind the transistor, with many variations of the MOSFET being stud-

ied, like the Laterally Diffused MOSFETs (LDMOS), a planar double-diffused MOSFET with

high power operation at frequencies between 1 GHz and 2 GHz. However, that is a subject too

vast to be fully covered here.

Summing up the different solid state configurations, they have their ups and downs in terms

of cost, power capacity, and noise, as we can see in Figure 2.3a, but this is completely dependent

on the semiconductor being used with its unique characteristics, Figure 2.3b. Nevertheless, solid

state solutions are the most elegant solution to nowadays problems, due to their size, weight, and

price, with some exceptions like radar systems in the order of 1–10 kW, where electron tubes are

better. [4, Chapter 11].

2.2.0.3 Solid State devices modelling

A good way to end this revision on the evolution of the active devices, is to mention the

evolution of their modelling over the years. There is a vital distinction that needs to be made in

the modelling formats.

There are compact models that try to replicate the behavior of a given device with empirical

equations, popular after the seventies, and the behavioral device modelling, a measurement-based

model that gained relevance in the 1990’s.

The advancement in Vector Network Analyzer (VNA) technology provided S-parameter mea-

surements and the availability of pulsed testing equipment, allowing procedures like pulsed load-

pull measurements, and non-linear modelling, revealed essential for the progress of the RF Power

Amplifier area [17].

2.3 RF fundamentals 15

(a) Transistor’s performance comparison [4, Chapter 11]

(b) Material’s performance comparison [16]

Figure 2.3: Different technology’s performance

2.3 RF fundamentals

As discussed before, RF active devices have come a long way across the years, since the

change in the paradigm in the seventies, to newer and better solid state technologies. Not only the

technologies evolved, but also the way they are studied, designed, and implemented, mainly with

the aid of Computer Aided Design (CAD) [4, Chapter 12]. An amplifier is one of the most studied

RF devices, because of its usefulness, so there is a list of canonical aspects to be considered when

talking about a PA.

The behavior of a PA is intuitive for anyone with basic knowledge in electronics, an input

power must be amplified at a cost of an external source of power with losses associated.

Figure 2.4: Power amplifier simplistic model (image adapted from [18])

Certainly the gain and efficiency need to be analyzed, but also other aspects like stability, noise


figure and linearity. To do that, one must firstly understand the basics of RF, namely how to model

the behavior of a circuit.

2.3.1 Two-Port Network Parameters

Figure 2.5: Two-Port power gains configuration, with S meaning source and L meaning Load [19,Chapter 2]

If one considers the voltage, impedance, respective currents and input voltages of the linear

time-invariant two-port network, LN, both for the side of the source and load as presented in Figure

2.5, one can write the following relations [20, Chapter 3]

V1 +ZsI1 =Vs (2.35a)

V2 +ZLI2 =VL (2.35b)

These relations, if reorganized (equation 2.35), are indicative that a matrix-like relation, expression

(2.37), can be written to relate the network voltage and currents.

V1 = Z11I1 +Z12I2 (2.36a)

V2 = Z21I1 +Z22I2 (2.36b)

[V1

V2

]=

[Z11 Z12

Z21 Z22

][I1

I2

](2.37)

These Z parameters can subsequently be measured by evaluating boundary conditions, such as the

following, having in mind that this rationale can be scaled to a N port Network.

Z11 =V1

I1

∣∣∣∣I2=0

(2.38)

Other types of parameters can be considered like Y, ABCD or H parameters, depending on the way

the voltages and currents are related. However, scattering parameters, S parameters are usually the

more used to characterize RF devices like amplifiers. These have the advantage of being easier

to measure, since they are not based on total current or voltages, and give the engineer useful

measures like gain (S21), load isolation (S12), load reflection coefficient (S22) and source reflection

coefficient (S11) [21].


2.3.1.1 Scattering Parameters

Scattering parameters are obtained by the relation of the incident waves, a, and reflected waves,

b. Although there is a formal way of calculating these parameters, they are usually obtained using

a Vector Network Analyzer. One can measure the magnitude and phase of said waves and extract

the S parameters from that. The VNA however, is a very sensible device that must be methodically

calibrated before each use [20, Chapter 3].

Short Open Load Through (SOLT) is a simple method. Since the response to each situation

is standard, errors can be defined and taken into account. QSOLT is a variation that removes the

need to measure the one-port standards at the second VNA port, speeding up the process, hence

the name quick SOLT [22].

Through-Reflect-Line (TRL) is another method that uses a significantly longer transmission

line compared to the previous method, and is usually used in waveguides and non-coaxial envi-

ronments [23].

Figure 2.6: S parameters for two-port networks. [20, ch 3]

Just like in equation (2.38), the calculations of S parameters have a similar approach.

S11 =b1a1

∣∣∣a2=0

S12 =b1a2

∣∣∣a1=0

S21 =b2a1

∣∣∣a2=0

S22 =b2a2

∣∣∣a1=0

(2.39)

2.3.2 Impedance Matching

A PA can be seen as a cascade of several parts, each one of those parts must be matched

with the following/previous part’s electric characteristics. The metric of this agreement is made

in terms of impedance matching, the better the matching, the bigger is the percentage of power

delivered to the next stage.

The matching can be done resorting to discrete/lumped elements, and/or distributed elements,

i.e., transmission lines. Lumped elements are usually used with lower frequencies, while dis-

tributed elements are used at higher frequencies, usually supporting higher power values [20,

Chapter 5].

2.3.2.1 Transmission lines

In [20, Chapter 5] it is shown that taking Kirchhoff’s voltage and current laws and applying

them to a transmission line model with the resistance, inductance, and capacitance as a sum of


infinitesimal contributions of pieces with length δ z, one can extract the travelling wave solutions

of the line that tell us the voltage and current at any point of the line in terms of the incident (+)

and returning (-) voltages and currents, with γ being given by expression (2.41)

V (z) =V+0 e−γε +V−0 e+γz (2.40a)

I(z) = I+0 e−π + I−0 e+γx (2.40b)

γ = α + jβ =√

(R+ jωL)(G+ jωC) (2.41)

One can also express the characteristic impedance, Z0, as presented in equation (2.42).

Z0 =R+ jωL

γ=

√R+ jωLG+ jωC

(2.42)

In [20, Chapter 5] it is also shown a fundamental concept of RF circuits. A transmission line

with characteristic impedance Z0, terminated with a load ZL, presents a relation of the incident

and reflected wave in terms of both impedances, being that relation the reflection coefficient of the

load ΓL (in this case).V−0V+

0=

(ZL−Z0

ZL +Z0

)= ΓL (2.43)

The power delivered to the load can then be calculated with the reflection coefficient (2.44), that

in a perfectly adapted load is one, resulting in a maximum of the delivered power of (2.45), which

is the same as one half of the voltage times current at a given time.

Pavg =12

∣∣V+0

∣∣2Z0

(1−|ΓL|2

)(2.44)

Pmax =12

∣∣V+0

∣∣2Z0

=12

VdcIdc (2.45)

At last, a fundamental result is how the input impedance of a line with length l with a given

impedance and a load impedance is calculated.

Zin (z) = Z0

(ZL +Z0 tanh(γl)Z0 +ZL tanh(γl)

)(2.46)

From this expression, many others can be derived exploring limit cases, for example, using open

or short circuit loads, or using multiples of quarter, half, and eighth wavelength lengths. In [19,

Chapter 8], various techniques that resort to distributed elements are shown, being one example

commensurate lines, lines with length λ/8, resulting in an inductive behavior when short circuited,

and a capacitive behavior when the load is open.


Another particular case is when quarter wave length lines are used, if one considers a lossless

line, γ = β = 2π/λ , resulting in β l = π/2.

Zin = limβ l→π/2

Z0ZL + iZ0 tan(β l)Z0 + iZL tan(β l)

= Z0iZ0

iZL=

Z20

ZL(2.47)

The typical process to adapt a load is, firstly, to separate the load by a transmission line with a

given length so that the input impedance of load plus line is purely real, and then a quarter wave

length line with a specific impedance Z0 is chosen so that the input impedance of the whole system

is the required [24, Chapter 5].

2.3.2.2 Impedance Matching Network

To match different impedances, the most common method is the use of L-matching networks

that, depending on the needed adaptation, can take eight configurations. These eight configura-

tions take capacitances and inductors that can be both in series and parallel. The inductive and

capacitive elements can be implemented via short circuit or open circuit transmission lines or

lumped elements.

Figure 2.7: Generic L-matching network sections (images adapted from [20, Chapter 5])

2.3.2.3 Biasing circuits and networks

To impose the operation point of a PA, one needs to impose two voltages, the gate and drain

voltages, maintaining them stable for the device operation to be the projected one. The simplest

biasing for a power MOSFET device is to use the potentiometer-type voltage divider for the gate

bias, with a choke inductor in the drain circuit. To reduce the current across the resistor divider, it

is common to use a diode [19, Chapter 1].

When a bipolar device is used, another problem rises, related to its thermal shift of the thresh-

old voltage, that is much more notorious than with MOSFET. In the junction case, temperature

compensation circuits must be used.

To ensure that the bias points are kept stable, the bias network should allow the Direct Current

(DC) to pass to the gate and drain off the transistor, while preventing RF signals from leaking

through it, presenting a high impedance at the fundamental frequency.

In [25] the RF choke was made possible by two radial stubs that ensure a short circuit at

fundamental and second harmonic frequencies, followed by a quarter-wavelength line added to

create an open circuit at the fundamental and, therefore, a short circuit at second harmonic. DC


block capacitors were also used before the input and output, making sure that only RF signal

crosses.

2.3.2.4 Smith Chart

Before continuing with further subjects like stability and load pull, an explanation on what is

the Smith chart concept and its usefulness must be made.

The Smith Chart is a graphical method proposed by Phillip Hagar Smith. It provides a graphic

of displaying impedances and all related parameters using the reflection coefficient. For the Smith

Chart to be used, normalized impedances must be applied [20, Chapter 5].

zL =ZL

Z0=

RL + jXL

Z0(2.48)

Remembering the reflection coefficient formula (2.43), where ΓL is an imaginary number that can

be written as follows

ΓL = |ΓL|e6 ΓL = ΓLr + jΓLi (2.49)

Equation (2.43) can be rewritten in terms of ZL

ZL = Z01+ΓL

1−ΓL(2.50a)

zL = rL + jxL =ZL

Z0=

1+ΓL

1−ΓL(2.50b)

As shown, one can represent the load in terms of the reflection coefficient. In [20, Chapter 5] it is

referred that one can map the imaginary plane, Z, into a Γ plane, as suggested in 2.8 with centers(rL

1+rL,0)

for the real part, and(

1, 1xL

)for the imaginary part. Some of the properties that can be

Figure 2.8: Smith chart mapping from the Z plane [20, Chapter 5]

spotted in figure 2.8 and are worth noticing are that r-circles, centered in the real part of Γ, become

progressively smaller as r increases from 0 to ∞, all passing (Γr = 1,Γi = 0) point.

The centers of all x-circles lie on the Γr = 1 line, those for x > 0 (inductive reactance) lie

above the Γr-axis, and those for x < 0 (capacitive reactance) lie below the Γr-axis, becoming

2.4 Power Amplifier characterization 21

progressively smaller as ΓxL increases from 0 to ∞, ending at the (Γr = 1,Γi = 0) point for an

open circuit and being the Γr axis when x = 0.

An analogous analysis can be made for admitances, obtaining a mirrored version of 2.8.

Combining both can be a useful way to study circuits with series and parallel elements, as

one can simply start from a given point in the chart and move/rotate according to the circles as

suggested in 2.9.

Figure 2.9: Adding components using ZY Smith chart. [20, Chapter 5]

2.4 Power Amplifier characterization

2.4.1 Load Pull

As explained in section 2.3.2, to get the most of the active device, a matching network must be

built in order to match both the source and the load. However, in the past it was particular difficult

to predict the exact value of the power match impedance at RF, and microwave frequencies and

was regarded as something which could only be measured experimentally [26, Chapter 2].

Two mechanical tuners would be connected to the input and output of the Device Under Test

(DUT), varying the source and load impedance while measuring the network parameters, this way

giving a practical measurement of the device’s behavior. Nowadays, this technique, associated

with CAD tools, remains a great way to measure devices, providing accurate and extensive load

pull data that can be used to design the amplifier itself, or to confirm the nonlinear data that might

be provided by the manufacturer [19, Chapter 3].

To understand how load pull works, one must first understand Loadline theory.

2.4.2 Loadline Theory

Considering a highly idealized model of the transistor represented on figure 2.10b, and assum-

ing that the device is operating over the ideal model presented in 2.10a, in a way that it has a linear


response in all input signal swing, i.e., a class A amplifier.

If the load is matched for maximum power (2.45), one can calculate the optimal resistance for

maximum delivered power with:

Ropt =VdcImax

2

=Vdc

Idc(2.51)

Assuming a factor p, such that the obtained power PRF is equal to POPT/p, one can get two

(a) Ideal strongly nonlinear device model. (b) Linear power amplifier

Figure 2.10: Class A configuration [26, Chapter 2]

results for the possible solutions that give the said power. Maximizing the voltage and minimizing

current when the resistance is high, RHI , and the other way around when the resistance is low, RLO,

as presented in figure 2.11.

Figure 2.11: Class A linear power amplifier with high and low resistance load [26, ch 2]

The same rationale can be used taking into account a load with a generic impedance with both

imaginary and real parts, being that a phase difference will be introduced between voltage and

current. The rest of the ellipsoid like shape will have RLO±XM in the extremities, being XM the

maximum reactance for the defined p factor [26, Chapter 2].


This way, several ellipsoids can be drawn centered at the optimum load with a "radius" depend-

ing on the p factor, being that the further away from the optimal point the less power is delivered

to the load.

The measured curves tend to be more oval compared to the proposed ideal model once they

are measured in a real device with a behavior that is not the same as the model in figure 2.10a.

In the previous analysis, it was assumed a class A amplifier, the canonical configuration for

PA, known for its low efficiency, as will be presented in section 2.6.

If one wants to analyze the efficiency contours in the Smith Chart, just like in the maximum

power case, the efficiency evolution with respect to load must be evaluated. [27] reviews Cripps’

efficiency load–pull contours. From the DC power consumption, (2.52), one can derive the drain

efficiency dividing the output power by (2.52), obtaining (2.53).

Pdc =VDDI0 =1π

VDDImax =2π

VDDVDD−Vk

|ZL|(2.52)

η =π

4RL

|ZL|VDD−VK

VDD=

π

8RLIMax

VDD(2.53)

The same reasoning can be made to draw the efficiency contours that can be plotted in the same

Smith Chart as the maximum power ones.

Figure 2.12: Load–pull contours corresponding to a class B PA with output power (PStep = 1 dBand PMax=55 dBm ) and efficiency (ηStep = 5 and ηMax = 78.5% ) [27]

Analyzing 2.12, one can see that the optimal point in terms of efficiency usually differs from

the output power one, so a compromise must be made depending on the application. In this thesis,

this analysis is very useful since a high power good efficiency PA is the objective.


2.4.3 Transistor operating point

The fundamental behavior of a transistor based amplifier can be characterized by two main

factors regarding the input voltage, output current relation. Firstly, the behavior of the device itself

can be characterized by its I-V curve.

One can identify the middle rectangular zone where signal clipping, compression and other

nonlinear distortions do not occur, at least compared to what happens outside this region, as stated

by [28]. In the graphic 2.13 one can see the knee voltage (Vk), the breakdown voltage (VBR) that

Figure 2.13: I-V curve, defined as "soccer pitch" in [28]

limits the "pitch". The horizontal axis corresponds to the gate-to-source pinch off voltage (Vpo)

and the maximum current (Imax) can also be identified in the m1 marker.

The spacing of the I-V curves for different values of Vgs is related to what is called the transcon-

ductance (gm ≈ ∆lds/ ∆Vgs), the intrinsic gain of the device.

In 2.13 it is also shown in the grey and blue doted line possible operation points for the tran-

sistor, which along with load matching, define the class of the amplifier. The gray line is related to

class A amplifiers and the blue line to class B amplifiers. More on this will be presented in section

2.6.

2.4.4 Stability

The tendency of an amplifier to oscillate must be a key aspect to take into account when

designing an amplifier. In RF amplifiers, residual oscillations are pretty common due to transistor

feedback, meaning that the load isolation can be imperfect, and due to path delays that can create

situations of instability. This way, a minor signal could keep being amplified until it reaches a

power that cannot be dissipated, potentially damaging the system [29, Chapter 3].

As mentioned by Gonzalez, to have an oscillation in a two-port network one must have a

negative resistance port, which can be defined in terms of the reflection coefficient magnitude of


the input and output of the network. Therefore, the unstable case is obtained when |ΓIN | > 1 or|ΓOUT |> 1, results that can be easily spotted in the Smith Chart.

Figure 2.14: Two port network configuration [29, Chapter 3 ]

If one remembers how to calculate ΓIN and ΓOUT , it is easily identified a dependence of the

input and output reflection coefficient on the load and source matching networks, respectively.

This way, two situations might occur: either the system is unconditionally stable, meaning that|ΓIN |< 1 and |ΓOUT |< 1 for |ΓS|< 1 and |ΓL|< 1; or the system is conditionally stable, meaning

that |ΓIN |< 1 and |ΓOUT |< 1 is only verified for some passive source and load impedances.

ΓIN = S11 +S12S21ΓL

1−S22ΓL(2.54)

ΓOUT = S22 +S12S21ΓS

1−S11ΓS(2.55)

2.4.4.1 Stability circles

Taking equation (2.54) and (2.55), applying the conditions |ΓIN | = 1 and |ΓOUT | = 1 and

rearranging some terms, one can obtain stability boundaries, stated as circles [4, Chapter 12]

|ΓL−CL|= rL

|ΓS−CS|= rS(2.56)

where CL and CS are the center and the rL and rS radius of the circles are calculated by the following

expressions, where |∆|= |S11S22−S12S21|.

CL =(S22−∆S∗11)

∗

|S22|2−|∆|2rL =

∣∣∣ S12S21|S22|2−|∆|2

∣∣∣CS =

(S11−∆S∗22)∗

|S11|2−|∆|2rS =

∣∣∣ S12S21|S11|2−|∆|2

∣∣∣ (2.57)

These circles are obtained as a limit condition, so after they are drawn, one should identify which

side of the boundary is stable, both for the ΓIN and ΓOUT .

Taking in mind that when Zs = Z0, meaning ΓS = 0, ΓOUT can be evaluated at the center of the

Smith Chart. So the equation (2.55) can be calculated as simply as |ΓOUT | = |S22|. This way, to

determine if the center of the ΓOUT chart is stable, one only checks if |S22|< 1, being unstable if

otherwise.


The same rationale can be made for ΓIN with ΓS = 0 and evaluating |S11|. An example of the

ΓS circles can be seen in figure 2.15. .

Figure 2.15: Smith Chart with stable and unstable regions (left to right) in the ΓS plane [29,Chapter 3]

Other important aspects to be taken into account relating stability are that, to have an uncon-

ditionally stable system, the stability zone must cover the entire Smith Chart. In other words,

||Cs |−rs|> 1 for |S22|< 1 (2.58)

and

||CL |−rL|> 1 for |S11|< 1 (2.59)

being evident that, to have an unconditionally stable system, one must have |S11|< 1 and |S22|< 1,

because the termination ΓL = 0 or ΓS = 0 will produce |ΓIN|> 1 or |Γour |> 1.

2.4.4.2 Stability tests

Taking into consideration what was just said in the previous section, formal methods have

been proposed to calculate the potential stability of an amplifier. K − δ test shows that a de-

vice will be unconditionally stable if Rollet’s condition (2.60) is met, having in mind that |∆| =|S11S22−S12S21| as defined before, should be less than one.

K =1−|S11|2−|S22|2 + |∆|2

2 |S12S21|> 1 (2.60)

An alternative also mentioned in [4, Chapter 12] involving a single parameter is the µ test, that

tells that an amplifier is stable if (2.61) is met.

µ =1−|S11|2∣∣S22−∆S∗11

∣∣+ |S12S21|> 1 (2.61)

2.5 Power Amplifier metrics 27

Both tests are necessary and sufficient to prove unconditional stability, but the µ test has the

advantage of measuring said device stability by how much larger than one the µ value is, allowing

comparisons between different devices to be made.

Important to notice that if the test fails, circle analysis must be made. Stability depends on the

frequency being analyzed, since the matching network has a frequency dependent impedance and

new tests must be made if the analysis frequency is changed.

2.4.4.3 Maximum stable gain

In a perfectly isolated amplifier, with S12 = 0, to obtain maximum gain, one must have conju-

gate matching networks, Γin = Γ∗S and Γout = Γ∗L. In this case, one is set to obtain the maximum

possible gain, also known as matched gain, in an unconditionally stable device.

GTmax =|S21||S12|

(K−

√K2−1

)(2.62)

A more relaxed definition is the maximum stable gain, applicable to every device, not needing to

be unconditionally stable [4, Chapter 12].

Gmsg =|S21||S12|

(2.63)

2.5 Power Amplifier metrics

In order to measure the performance of an amplifier, one must review how those metrics are

defined and what exactly do they measure.

2.5.1 Amplifier Gain

Remembering the configuration of figure 2.1, one can deduce several expressions relating the

the power transference along the system, in terms of the scattering parameters and the reflection

coefficients at the interfaces [29, Chapter 3].

Transducer Power Gain (GT ), the most used definition depending on both load and source

impedance, ZL and ZS, relates the gain from source to load. A special case is when the load

isolation scattering parameter is negligible. Thus, S12 is taken as zero representing the unilateral

transducer power gain.

GT =PL

PAVs=

power delivered to the loadpower available from the source

(2.64)


The Transducer Power Gain can be calculated as

GT =1−|Γs|2

|1−ΓINΓs|2|S21|2

1−|ΓL|2

|1−S22ΓL|2

GT =1−|Γs|2

|1−S11Γs|2|S21|2

1−|ΓL|2

|1−ΓOUTΓL|2

(2.65)

The Power Gain (GP) expresses the gain from input to load, assuming an ideal input matching

network (complex conjugated), with maximum power being transferred from source to input.

Gp =PL

PIN=

power delivered to the loadpower input to the network

(2.66)

Determined by

Gp =1

1−|ΓIN|2|S21|2

1−|ΓL|2

|1−S22ΓL|2(2.67)

The Available Power Gain (GA) is the load dual of the power gain, since it represents the gain from

source to the output terminal, assuming an ideal output matching network (complex conjugated),

with maximum power being transferred to the load.

GA =PAVN

PAVS=

power available from the networkpower available from the source

(2.68)

Having the following formula

GA =1−|Γs|2

|1−S11Γs|2|S21|2

1

1−|ΓOUT|2(2.69)

Another special case to be taken into account is if the matching networks are built for zero reflec-

tion, ΓL = ΓS = 0, resulting in a transducer gain of

GT = |S21|2 (2.70)

2.5.2 Efficiency

As the power of an amplifier increases, so does the dissipated power. Therefore, power ampli-

fiers must be designed with this in mind. A common way to measure the efficiency of the device

is defined as the collector/drain efficiency, depending on the technology, being the ratio between

the output power and the power supplied by the DC source, which can be rewritten in terms of the

dissipated power Pdiss [20]

η(%) =Pout

PDC×100 =

1

1+(

PdissPout

)−( 1

G

) ×100 (2.71)


If one wants to define the efficiency taking into account the input power, the power-added effi-

ciency, ηPAE , can be used.

ηPAE(%) =Pout−Pin

PDC×100 =

11−( 1

G

) ×100 (2.72)

2.5.3 Linearity

A. Grebennikov reviews in [19] how to characterize the linearity of a system. It is remembered

that, for a system to be considered linear, it must respect two properties. The first one is the

superposition, i.e., the system’s response to the sum of many input signals must be the same as

the sum of the responses of the system to the individual signals. The second property states that

multiplying the input signal by a constant k must have the same result as the scaling of the output

signal by the same scale factor.

This rationale can be directly applied to RF devices, being the signals, electric signals, and the

superposition property applied means that in a system with multiple frequencies they are amplified

independently, homogeneously, without interaction with each other.

As mentioned in [4, Chapter 10], all PAs can be considered as non-linear, since they require

the input signal to be within a minimum and maximum value to display the desired behavior. If the

excitation lies outside these limits, non linear effects like harmonic generation and gain saturation

might occur. The range where the device will have the desired behavior is known as the dynamic

range.

The enumeration of the non linear phenomena that one should take into account are the fol-

lowing [30, Chapter 1]:

• Harmonic generation - appearance of multiples of the fundamental frequency;

• Saturation - output signal as a limit, from that the gain reduces;

• Intermodulation distortion - interaction between two products resulting in other tones, caus-

ing spectral regrowth in signals with close input tones;

• Cross and AM-PM modulation - modulation transfer from one signal to another, and ampli-

tude modulation cause phase variations, respectively.

To portrait these non-linearities, one must know how to measure them. The book [30, Chapter 4]

demonstrates that in a weakly non-linear system, the output response of such system can be mod-

eled as a power series, Taylor series type of approximation, or a Volterra-series analysis, a more

complex model that captures memory effects of the device under analysis. An example is if the

system under consideration contains a capacitor, that has a different response at a given instant,

depending on the charge stored, which will itself depend on the past value of the input signal. In

such cases, integro-differential equations of time are needed, taking into account both phase and

magnitude [19, Chapter 1], [24, Chapter 1]. In this thesis, however, we will detail the simpler


characterization power series analysis, that can be expressed as

v0 = a0 +a1vi +a2v2i +a3v3

i + · · · (2.73)

where the Taylor coefficients are defined as

a0 = vo(0) (DC output) (2.74)

where a0 expresses the rectification factor, ie, Alternated Current (AC) to DC conversion

a1 =dv0

dvi

∣∣∣∣vi=0

(linear output) (2.75)

a1 measures the linear term, gain or attenuation factor depending if the value is lesser or larger

than one

a2 =d2v0

dv2i

∣∣∣∣vi=0

(squared output) (2.76)

a2 is related to the frequency conversion factor, as will be evident in the analysis of intermodulation

distortion. This factor is particularly useful in mixers and frequency converters.

2.5.4 Gain compression

To understand the gain limit of an amplifier, one must consider the case where a single-

frequency signal excites the system with a given magnitude and frequency.

vi =V0 cosω0t (2.77)

Combining equation (2.73) and (2.77) one gets

v0 =a0 +a1V0 cosω0t +a2V 20 cos2

ω0t +a3V 30 cos3

ω0t + · · ·

=

(a0 +

12

a2V 20

)+

(a1V0 +

34

a3V 30

)cosω0t +

12

a2V 20 cos2ω0t +

14

a3V 30 cos3ω0t + · · ·

(2.78)

Considering the three order terms, the gain at the frequency ω0 can be obtained in (2.79). In an

ideal case, the gain would only be the linear term a1. The presence of the a3 term usually occurs

with the opposite signal, so that for higher values of input signal the gain decreases, reflecting

the physical saturation of the device when the signal goes close to the power supply voltage.

This effect is called gain compression, or saturation and is usually characterized as the 1 dB

compression point.

Gv =v(ω0)

0

v(ω0)i

=a1V0 +

34 a3V 3

0

V0= a1 +

34

a3V 20 (2.79)


As the name suggests, the 1 dB compression point for an amplifier is the point where the amplifier

gain becomes 1 dB below its ideal linear gain, being calculated as below [20, Chapter 1].

PIdB. out −PIdB. in = GldB = G0−1 (2.80)

Figure 2.16: 1-db compression point representation[20, Chapter 1]

2.5.5 Intermodulation Distortion

Using the same analysis, resorting to the Taylor series, and exciting the system with a two-tone

signal (2.81), where α = ω1t,β = ω2t,ω1 and ω2 are the different frequencies one gets (2.82).

x(t) = A[cosα + cosβ ] (2.81)

d(t) =[a1(cosα + cosβ )+a2(cosα + cosβ )2 +a3(cosα + cosβ )3]− k cosα− k cosβ (2.82)

Expanding the relation, it can be shown that the output signal will have the aspect of figure 2.17.

Despite the fact that all second-order products are undesired, the most troublesome are usually

ω1−ω2 (difference frequency) and ω1 +ω2 (sum frequency), considering that the input frequen-

cies are close [4, Chapter 10]. This effect is usually measured by the Total Harmonic Distor-

tion (THD), which is the ratio between the sum of the powers of all harmonic frequencies above

the fundamental frequency of the input signal, and the power of the fundamental frequency, all

measured at the output of the system [19, Chapter 1].

THD =∑

ni=2 Pi

P1(2.83)


Figure 2.17: Frequency spectrum of third-order non-linearity system with two-tone sinusoidalinputs [19, Chapter 1]

2.5.6 IP2 and IP3

Expression (2.82) shows that for small input powers, the third-order intermodulation products

will be very small, but will increase quickly as the input power increases [4, Chapter 10]. The

figure shows that the fundamental product is proportional to the input power, with a unity slope

(before the onset of compression). The line describing the response of the third-order products has

a slope of 3, and the second order has a slope of 2.

Third-Order Intercept Point (IP3) and Second-Order Intercept Point (IP2) are intersection

points of the third-order and second-order powers with first-order power, respectively. This point

can be used to further characterize the IMD when the gain compression is not the dominant factor,

i.e., in the absence of large signals.

Figure 2.18: IMD, IP2, IP3, and gain compression [19, Chapter 1]

2.6 Classes 33

2.6 Classes

PA classes can be divided into two big subgroups based on their operation mode. Classes A,

B, and AB operate in linear mode and classes C, D, E, F, and S function in non-linear mode.

Depending if the transistor is taken as a controlled switch, or a controlled current source, one

has D to S as switched mode amplifiers, and A to C known as transconductance based amplifiers

[20].

Transconductance amplifier differences are based on the concept introduced in 2.4.3, that vary-

ing the operation point of the transistor results in getting different values of linearity, gain and

efficiency. This can be more clear once we investigate the conduction angle of each class, θ .

Conduction angle can be defined as the transistor’s active interval over one period duration,

taking values from 0 to 2π . The dots in 2.19 mark the bias points, so it is clear that a vGS signal

Figure 2.19: Load lines and bias points for linear amplifiers [20, Chapter 1]

(horizontal lines) with adequate amplitude, not more than vmaxGS /2, will have 100% of current swing

with respect to the input voltage, θ = 2π . Class B with the bias point at the pinch-off point will

operate half the time, θ = π . With the same analysis, AB will have π ≤ θ ≤ 2π and C will have

0 ≤ θ ≤ π . The conduction angle is very useful because it allows the efficiency to be calculated

directly from it. Equation (2.84), can be used in transconductance amplifiers [20].

η =Pout

Pdc=

θ − sinθ

4[sin(θ/2)− (θ/2)cos(θ/2)](2.84)

The result in (2.84) comes essentially from a spectral-domain analysis.

Reviewing once again the typical configuration of a transconductance amplifier, 2.20, and

assuming a drain current that has the DC component and modulation component, iD = IDC +

Im cos(θ), the same definition can be made to vDS =VDC−Vm cos(θ) and to vGS =Vt+Vgsm cos(θ).

Considering this, one can expand the drain current and drain to source voltages as a Fourier ex-

pansion.

iD(t) = Io +∑∞n=1 Ian cosnωot + Ibn sinnωot = Io +∑

∞n=1 In cos(nωot +αn)

vDS(t) =Vo +∑∞n=1Van cosnωot +Vbn sinnωot =Vo +∑

∞n=1Vn cos(nωot +βn)

(2.85)


Figure 2.20: Class A, B, and C. typical configuration [20, Chapter 1]

The calculation of these coefficients goes as follows

Io =1T

∫ T/2

−T/2iD(t)dt

Ian =2T

∫ T/2

−T/2iD(t)cos(kωot)dt

Ibn =2T

∫ T/2

−T/2iD(t)sin(kωot)dt

(2.86)

so considering the iD = IDC + Im cos(θ), one can, in a class A amplifier, get a I0 = IDC, Ia1 = Im

with remain coefficients of a and b being zero [20, Chapter 1 ]. One can then calculate the class

A DC power, Pdc, and the output power of the fundamental Pout , assuming that the drain to source

voltage can be neglected, compared to the DC voltage.

Pout =12

Re [V1I∗1 ] =12

VdcIm (2.87)

Pdc =V0I0 =VdcIdc (2.88)

The same rationale can be made having in mind the conduction angle, reaching more generic

expressions by dividing Pout by Pdc, getting (2.84) resulting in 50% for the class A configuration.

In [31, Chapter 2] it is also mentioned that DC and fundamental powers depend on the con-

duction angle.

Pout =12

VdcImax

2π

2θ − sin(2θ)

1− cosθ(2.89)

Pdc =VdcImax

π

sinθ −θ cosθ

1− cosθ(2.90)

Another detailed approach to get the same result is stated in [19, Chapter 1 1], the known picewise-

linear approximation. Writing the output current as a function of the input voltage

i(t) = f [v(t)] (2.91)

2.6 Classes 35

Assuming a signal excursion like (2.85) that goes past the pinch off point Vp, one can write

i =

0 vin ≤V

gm(vin −Vp

)vin ≥Vp

(2.92)

Taking the conduction angle as θ according to cosθ = −Vbias −VpVin

, one can get that (2.92) can be

rewritten as

i(ωt) =

Iq + Im cosωt −θ ≤ ωt < θ

0 θ ≤ ωt < 2π−θ(2.93)

Calculating the (2.86), they can be rewritten in terms of the output current amplitude Im.

In = Imγn(θ) for n = 1 · · ·n where Im = gmVin (2.94)

γ0(θ) =1π(sinθ −θ cosθ)

γ1(θ) =1π(θ − sinθ cosθ)

γn(θ) =1π

[sin(n−1)θ

n(n−1) −sin(n+1)θ

n(n+1)

] (2.95)

being that the γ coefficients can be solved in terms of the conduction angle, one can derive again

the efficiency formula as (2.96), where ξ = VmVcc

.

η =PP0

=12

Im

Iq

Vm

Vcc=

12

Im

Iqξ (2.96)

2.6.1 Class A B AB and C

As already detailed before, the distinction between these three classes is the selection of the

operating point. The bias point in the class A mode of operation is selected at the center of the

I–V curve between the saturation voltage and the maximum operational transistor voltage, giving

a DC current between 0 and the maximum allowable current. With a 2π conduction angle and a

constant quiescent current, even when no current is being applied, the maximum efficiency is only

50% [20, Chapter 1 ].

For class B, the biasing point is such that the transistor is turned on only one-half of the cycle

θ = π . One can calculate its efficiency by (2.96) or (2.84), giving η = π/4 = 78.53%. Since half

of the signal is cut, harmonic generation occurs. When compared to a class A amplifier, class B

requires twice the amount of the voltage swing at the gate of the transistor, i.e., reducing the gain

to half.

Another important aspect is that the transistor only imposes the shape of the voltage and cur-

rent waveforms while on. When it is off, it is the external passive circuitry that determines the

shape of current and voltage, and their overlap, meaning that the external passive circuitry will be

a main factor to impose a device’s efficiency [31, Chapter 2].


Class AB does a compromise between efficiency and linearity, having better efficiency but

worst linearity and gain compared to class A, and the opposite compared to B. Such occurs because

the conduction angle stays between π and 2π .

Figure 2.21: AB amplifier excursion [20, Chapter 1]

Sliding the operating point N in 2.21, one gets the behavior of A, B or AB. Moving this point

horizontally, one gets different values of β . This angle is directly related to the equivalent load

resistance RL, where V =Vm is the modulation voltage.

tanβ =I

V (1− cosθ)=

1γ1RL

(2.97)

The load resistance at the fundamental frequency can be further calculated by the ratio of output

voltage and current [19, Chapter 1], that has an equivalent form in [31, Chapter 2].

RL(θ) =Vm

γ1(θ)Im(2.98a)

RL =VDD

I1= 2π

VDD

Imax

1− cos(θ/2)θ − sin(θ)

(2.98b)

Class C, as indicated in figure 2.19, has a bias point below the pinch-off level so that it conducts

less than 50% of the time, resulting in a higher efficiency, but lower linearity and lower gain.

An overview of the normalized behavior of these classes can be seen in figure 2.22a, where it is

evident that the most adequate choices for this thesis purpose are Classes B and AB, where the

output power is larger with a decent efficiency 2.22a. The linearity gets worse once we reduce the

angle of conduction, noticeable by the increase in the number and power of the harmonics 2.22b.

Another graphical result presented in [31, Chapter 2], is that the optimal load resistor has a minor

2.6 Classes 37

decrease from A to B and then an exponential growth from B to C, a consequence of the (2.98b)

equation.

(a) A to C performance curves [31, Chap-ter 2]

(b) Fourier analysis of the drain current[31, Chapter 2]

Figure 2.22: A to C class comparison

2.6.2 Class D

Class D amplifiers can operate in two modes, either in Voltage Mode (VM), a configuration

that uses a series resonator, or Current Mode (CM), a configuration that uses a parallel resonator

circuit.

A typical VM configuration is implemented with two complementary transistors, PMOS and

NMOS for example, being that each transistor will conduct half the time, actively switching on

and off [20] so they can, in theory, obtain 100% efficiency.

However, because of the parasitic capacitances on the switches, this implementation is tricky

to do at higher frequencies. The efficiency also gets degraded due to power dissipation in the

switches.

In [20] is also shown that Class S is a variation of the class D, where all the signal amplification

is made digitally with a modulator and a demodulator before and after the active element.

2.6.3 Class E

Continuing the rationale, one can theoretically get 100% efficiency by using switching. To

overcome the parasitic inconvenience, one can use the aforementioned parasitic in the tuning

network resulting in 2.23, with a single transistor that acts as a switch S, RF choke, a parallel-

connected capacitance Cp, a resonator circuit L–C, and a load RL. The resonator circuit and Cp

make sure that the sinusoidal output continues when the switch is off. This simple topology is

compatible with high frequency operation obtaining high efficiency, that can be justified by the

fact that no overlap of transistor current and voltage curves is present, the efficiency of this ideal-

ized case is 100% with relatively low gain [32].


Figure 2.23: Class E simplified configuration [20, Chapter 1]

Figure 2.24: Class E simplified configuration [20, Chapter 1]

2.6.4 Class F and F-1

The principle of class F is the same as class E, to minimize the overlap region between voltage

and current, reducing the transistor power dissipation. The goal is accomplished by the multireso-

nant load network in the class F amplifier, that helps to control the harmonic contents of the drain

voltage and current.

In this configuration all, even harmonics, are short circuited. Conversely, an open circuit is

presented to all odd harmonics, while allowing power flow to the load only for the fundamental.

This operation results in a voltage that is shaped towards a square wave, and a drain current that is

shaped towards a half-sine wave in a phase opposition [20, Chapter 1].

This conceptually simple topology suffers from what class E solved. Once again, the parasis-

tics complicate the design and reduce the efficiency [32].

It is important to notice that the inverse Class F is also a common topology. This time, the

resonant behavior towards odd and even harmonics is reversed, compared to Class F. This results

in a voltage square wave and half sinusoidal current.

The short circuit and open circuit are commonly obtained with quarter wavelength lines, as a

RF choke in the class F and in series with the load in the inverse class F, both of which can rise

problems of implementation once these lines do not present their ideal behavior [32].

2.7 Efficiency techniques 39

2.7 Efficiency techniques

To obtain a PA with good efficiency, one must choose an adequate class, however the solution

is not that simple. Power amplifiers only give maximum efficiency at a single power level, usually

around the maximum rated power of the device. As the input gets lower the efficiency also drops

fast, increasing the heat dissipation [26, Chapter 10]. To solve this problem, two approaches can

be made, either the DC supply changes with the demand of the input signal or the load is the one

that changes. To control Vdc, a sensing mechanism must exist for the amplifier to know when to

shift. Effectively, the load line stays with the same slope, because the load is supposed to be the

same, and it slides horizontally towards minor values if needed.

2.7.1 Envelope Tracking

Envelope tracking can be easily understood analyzing figure 2.25. When non-constant enve-

lope signals are used, the amplitude variations must be preserved, since these effectively contain

the information. As shown in the image, when the input signal gets low so does the DC power,

this way the ratio between the DC power and the amplified signal stays more or less the same,

independently of the signal envelope.

Figure 2.25: Envelope tracking behavior of DC voltage [33]

To implement the configuration presented above, one must include, besides the envelope

tracker, a time delay Td , to make the DC/DC converter react in time.

Figure 2.26: Envelope tracking implementation [24, Chapter 9]


2.7.2 Envelope Elimination and Restoration

Analyzing the name of the technique and 2.27 the way the technique works comes naturally.

Firstly, the input modulated RF signal is split. One branch goes into an envelope detector, ex-

tracting the envelope, and the other branch goes through a limiter, creating a phase modulated

signal.

Those two signal feed a switching amplifier, Class D to F, with high efficiency, obtaining the

amplified signal [24, Chapter 9].

Figure 2.27: Envelope Elimination and Restoration implementation [31, Chapter 9]

2.7.3 Load Modulation

Solutions to implement load modulation have already some history. The Doherty amplifier

was first proposed in 1936 [34], and remains a popular solution to the Load modulation technique.

Figure 2.28: Block diagram of the Doherty PA [24, Chapter 9]

The Doherty architecture is composed by two amplifiers: the carrier/main and the peak-

ing/auxiliary, connected by a quarter-wavelength transmission line.

2.8 Power Amplifier Architecture 41

The principle of operation is impedance modulation. The load impedance of a current source

can be modified by applying a current from another current source. In [26, Chapter 10] is shown

that the effective output impedance of one device can be modified by the driving signals phase and

magnitude, according to (2.99).

Z1 = RL

(1+

I2

I1

)(2.99)

The main amplifier, typically class AB or B, is active at low input signal amplitudes, and reaches

the compression point when larger signals are presented. At this point, the auxiliary PA, typically

a Class C, turns on, injecting current into the inverting network and causing the impedance seen

by the carrier to decrease.

With this, the load line slope of the main amplifier increases, keeping near saturation for higher

input power levels, increasing its efficiency for a larger range of output power.

2.8 Power Amplifier Architecture

Previously on this thesis, the term PA was mainly referred as a single stage based amplifier

with a single transistor. However, any practical implementation is made possible with multiple

transistor configuration. Some of these configurations are the push-pull power combining, and

multistage amplification, that will be discussed now, that can increase the overall output power of

the system [26, Chapter 13].

2.8.1 Push-Pull

Push pull configuration, a type of power combining, is commonly used in situations where low

distortion, high efficiency and high output power are required, being mostly used in frequencies

up to the GHz mark [18, Chapter 13].

The signal to be amplified is first split into two identical signals 180° out of phase. This

splitting can done using an input coupling transformer, as shown in 2.29. The split signals are then

fed to each transistor, being that each one of them is active half the time.

The balanced circuit created by the two identical transistors and the phase deviation create a

virtual ground that helps with stability and gain [19, Chapter 1].

This concept can be applied from Class A to Class C, being used to cancel out even harmonics

reducing distortion [24]. In [26, Chapter 13] is also referred the balanced amplifier configuration,

that uses a 90° phase difference, that has the same principle as push pull but with the advantage of

improving interstage matching, being a good solution for narrowband applications.

2.8.2 Multistage PA

A general approach to achieve high gain systems, is to divide the amplification process into

steps. The signal before getting to the last output stage where the output power meets the re-

quirements, goes first to stages that "prepare" the mentioned signal to be amplified. As shown in


Figure 2.29: Typical push–pull configuration [19, Chapter 1]

2.30, where a Class E amplifier was developed, the output power gain relative to the input power

remains more or less constant. Such thing does not happen with the efficiency that is optimal at

greater values. This conclusion can be generalized and has particular importance when no effi-

ciency techniques are used.

This way it is common for a High power PA to have multiple stages, namely, driver or pre-

driver, and driver followed by an output stage thus, dividing the problem into smaller problems

and optimizing efficiency.

The linearity of the driver is usually correlated with the linearity of the desired product. When

nonlinear amplifiers are acceptable, and the PA stage is a saturated design, one could use a non

linear driver stage. However, since the driver has a low impact on the overall efficiency when

there is a PA stage with over 10 dB power, this driver chain can be implemented using linear

design and improving the overall gain up to 40 dB [26, Chapter 13]. One important thing to notice

is that active device adaptation and DC isolation blocking capacitors just like in 2.31 still need

to be present. The design of the interstage match between a driver and PA stage can be just as

challenging as the matching of the load itself, being sometimes neglected.

2.9 State of the art high power amplifiers 43

Figure 2.30: RF performance of 500W AlGaN/GaN Vds=65V, Idsq=2.0A, Freq=1.5GHz [35]

Figure 2.31: Interstage match for driver-PA [26, Chapter 13]

2.9 State of the art high power amplifiers

To understand the state of the art regarding high power amplifiers some research was done,

obtaining the following values where CW stands for continuous wave operation. As one can see,

Frequency [GHz] Output Power [W] PAE [%] Mode Reference2,3 150 54 Pulsed [36]2,8 100 58 Pulsed [37]1,5 500 49 Pulsed [35]1,3 1000 501 Pulsed [38]2,6 95 72 Pulsed [39]L-Band 360 65 Pulsed [40]1,575 300 44 CW [41]

Table 2.1: State of the art high power amplifiers

many solutions have already been proposed in the 100 W range. By investigating these references,

one can see that the ones with greater power used some type of power amplifier architecture as

described in the previous section, being this an indicator that this thesis design should use it too.

1The only efficiency mentioned in this article was the 50% drain efficiency


2.10 Proposed solution

In this section a solution to the context problem will be proposed, after the SAR and EME link

budgets are analyzed.

2.10.1 Link Budget Realization

To evaluate if the proposed 200 W of power (53 dBm) is enough to do both Moon SAR and

EME communication, two link budgets will be evaluated.

2.10.1.1 Link Budget SAR application

The antenna gain was calculated with expression (2.9), assuming Aph as the area of the 3

meter parabolic. The radiation efficiency was assumed to be 100%, a typical approximation [3],

and the aperture efficiency was taken as 50% [42]. Considering the central frequency of 2.4 GHz

(λ =0.125 m), one has all data to calculate the gain relative to an isotropic antenna, reaching a

value of 34.5 dBi.

It is important to notice that the mismatch losses of the antenna and other losses, like depoint-

ing losses and depolarization losses, have been considered in a common factor with a typical value

of 3 dB associated [3].

Designation Gain UnitsTX Power 53,0 dBmTX Antenna Gain 34,5 dBiTransmission Losses -308,50 dBRX Antenna Gain 34,5 dBiOther Losses -3,0 dBReceived Signal Power -189,4 dBmNoise Level -134,4 dBmReceiver Noise Figure 2,0 dBRaw SNR -57,0 dBPulse Compression Gain 47,8 dBAzimuth Compression Gain 21,9 dBNet SNR 12,7 dBMinimum SNR 10,0 dBLink Margin 2,7 dB

Table 2.2: Link Budget Calculation

The transmission loss term was calculated according to table 2.3, where the forward and back-

wards free space losses, L f sl , were obtained by (2.13) considering a distance of 390.000 km. That

distance was obtained with a simulation in the software Orbitron being the worst case (apogee) for

a base station in Porto.

The moon gain, Gm, was calculated with (2.9), using a 6,92× 109 m2 area and the moon

albedo as 6% ( -12.21 dB) [3], a moon gain, Gm, equal to 115.24 dBi was obtained. With the

2.10 Proposed solution 45

previous data, one can obtain the expected power at the receiver, Pr, adding all the gains and losses

to the transmitted power, Pt , obtaining, in the receiver, a power of -189,4 dBm.

Pr = Pt +Gt +Gr +2×L f sl +Gm( dB) (2.100)

The selected area was chosen as the minimal individualization detected by the SAR experiment,

in other words, it was the minimal area that made the link possible as presented in table 2.2.

The variables relative to SAR were the folowing: Bandwidth of 30 kHz; pulse duration of 2

seconds; PRF of 0.217 Hz, chosen so that just after one receives the end of the first echo, 4.6

seconds later (2 of signal duration plus 2,6 of travel time) the next signal is transmitted; radar

integration time of 720 seconds, corresponding to the time that the 2,9 degree antenna beamwidth

is able to capture moon reflections when considering an azimuthal velocity of 1258.6 kmh−1,

calculated by the tangential velocity of the earth at Porto’s 41,15 latitude.

Designation Value UnitsMoon Total Physical Cross section 9,49E+12 m2

Radar Cross Section Physical Area 6,92E+9 m2

Moon Total CS / RCS (Ratio) 0,07% -Pixel Resolution after filtering (side) 83,21 kmRadar Cross Section 127,45 dBAlbedo (6%) -12,21 dBMoon Gain 115,24 dBiFwd Free Space Losses -211,9 dBRev Free Space Losses -211,9 dBTransmission Loss -308,50 dB

Table 2.3: Transmission Losses for a Radar Cross Section of 6,92E+9 m2

One important thing to notice is that, although using (2.31) one would obtain a range resolution

of 171.6 m, this would be only possible if the system was not limited link wise. A typical practice

is to project minimal resolution, being more precise than the objective resolution, and then use

low-pass image filters that take advantage of the mentioned oversampling to improve the image

quality [10].

The pulse compression gain was obtained with (2.33) getting 47,8 dB. For the calculation of

the azimuth compression gain, (2.34) was used, resulting in a gain of 21,9 dB.

To get the noise level at the receiver, one must first calculate the equivalent noise temperature

of the receiver, as suggested by (2.17). For temperature calculation, the steps taken are detailed in

table 2.4.

Firstly, the brightness temperature was calculated according to (2.25), where an approximation

that the directivity is somewhat constant inside the 2,9 degree beamwidth, results in a weighted

average of the squared radius area of 3,65% [43]. This way, Tb = 0,0365Tmoon+Tcosmos = 10,67K.

After getting the brightness temperature, the process was repetitive. Using (2.23), one can cal-

culate the temperature after an attenuator as a weighted average of the equivalent input temperature


Designation Value UnitTcosmos 3 KTmoon 210 KWeighted Average Moon Influence (%) 03,65 -0,0365Tmoon +Tcosmos 10,6691 KTsky (Physical) 274,8 KSky Losses 0,7470 W/WTsky 77,5086 KTantenna (Physical) 290 KAntenna Radiation efficiency (%) 100% -Teq.Antenna 77,5086 KCable Losses 0,9550 W/WTeq (After Cable) 87,07 K

Table 2.4: Noise Temperature

and the physical temperature of the attenuator.

This way, Tsky results in 77,51 K, where the physical temperature of the medium was taken

from [44]. As mentioned before, the radiation efficiency was assumed to be 100% and a small

cable was considered between the antenna and the Low Noise Amplifier (LNA), with 0.2 dB of

attenuation.

This way, an equivalent temperature just before the LNA was obtained and equal to 87,07 K,

which is in agreement with typical values presented in [8].

Having the noise and signal levels at the receiver, one can calculate the raw signal to noise

ratio at the LNA entry port. It is important to mention that this was considered the noise level

however, in a normal operation of the system, the actual noise level of the receiver will be larger

because of the contribution of the LNA noise, the LNA to receiver cable, and the receiver noise

itself. To have this into account, one can define the noise figure of the receiver as a contribution

of these three elements using (2.28). Actually, the 2 dB of noise figure that was used to obtain the

raw SNR was an estimate, since the reception system is not defined yet.

Adding the processing gain to the raw SNR and considering a minimal SNR value of 10 dB

to ensure that the image of the SAR moon is distinguishable from the surrounding noise, a link

margin of 2,7 dB was obtained, meaning that the link is just possible.

The obtained link margin could be further improved if one considered a value of 380.0000 km,

a more typical value, resulting in an improvement of 0.5 dB. Another approach is that, if for some

reason the amplifier can only provide 100 Watts of power, one can double the considered area for

the RCS, worsening the resolution by a factor of two.

A rough simulation of what the moon image would look like in the final project was studied,

considering the 6,92× 109 m2 area. This simulation was made possible with a pixelation tool,

where the grouping factor of the pixels is related with the minimal area considered relative to the

full moon area, indicated in 2.3. Each pixel represents the area mentioned above, meaning a side

resolution of about 83 km.


(a) Moon Stock image [45] (b) Moon pixelated image with groupingfactor of 40 (obtained from [46])

Figure 2.32: Approximation of the obtained SAR image

Nevertheless, an important disclaimer must be made: the actual result of the moon SAR would

be 2.32b with the contribution of the top half pixels with the bottom half pixels. This happens

because when doing SAR, while moving horizontally over a spherical object, one can have dis-

tinction over the horizontal axis, as the different echoes are distinguishable, but not in the vertical

axis, since the delay time from a point in the north pole of the moon is the same as the south pole

of the moon if the incident wave is perpendicular to the Moon’s equator, as shown by [47].

2.10.1.2 Link Budget EME communication

For the EME communication case the link budget does not change too much. The changes are

mainly the way the Moon Gain is calculated, the processing gain, that this time is related to the

chosen modulation and respective error correction methods, and the bandwidth, that can be quite

smaller.

All the data regarding system characterization remains the same, with the exception of the

bandwidth used, that this time was considered to be 3 kHz, an acceptable value to use the JT65

transmission mode [12]. This time, the radar cross section was calculated according to [48],

similarly to what was done in [3], where the radar cross section is calculated with (2.101), that

dividing by the area of an isotropic antenna, as suggested in (2.9), allows to achieve a moon gain

of 146,96 dBi, that adding two times the free space losses gives a transmission loss of 276,78 dB.

σ = (0.065±0.008) ·Amoon (2.101)

Changing the bandwidth, one can recalculate the noise level, assuming the same noise temperature

and using (2.17) to achieve a noise level of -144,4 dBm. The processing gain considered was 24

dB, as mentioned in [12].

Repeating the rest of the calculations just like before, a link margin of 8,7 dB was obtained,

which comfortably supports the JT65 transmission mode.


Designation Gain UnitsTX Power 53,0 dBmTX Antenna Gain 34,5 dBiTransmission Losses -276,78 dBRX Antenna Gain 34,5 dBiOther Losses -3,0 dBReceived Signal Power -157,7 dBmNoise Level -144,4 dBmReceiver Noise Figure 2,0 dBSNR -15,3 dBProcessing Gain 24 dBNet SNR 8,7 dBMinimum SNR 0 dBLink Margin 8,7 dBTable 2.5: Link Budget Calculation EME

2.10.2 Amplifier solution

Evaluating section 2.1.7, one can say that the amplifier solution will not have the bandwidth

as a harsh requirement to be met, since both cases are implemented using narrow bands. This

logic keeps being valid if the amplifier is designed for SAR applications because, as concluded in

section 2.10.1, only 30 kHz would be an adequate solution.

Regarding the operation frequency, 2.4 GHz was used due to a limitation on the available feed,

as mentioned in 2.10.1, so this should be the central operating frequency of the amplifier chain.

Another detail that should be taken into account is that, for either application, constant enve-

lope signals are an option, meaning that, even though the linearity is usually a key aspect in certain

applications like amplitude modulation, it is not a critical aspect, so some margin of nonlinearity

can be considered in favour of more efficient and more powerful designs. Considering this, and

even though [49] was able to obtain 100 W in a CW configuration, this does not mean that class

A is a good option for high power applications, especially in this thesis context, where linearity is

not crucial.

Regarding the technology of the active device to be used, there are some options, like Si

BJT and Si LDMOS, but there are not many options as viable as GaN over HEMTs, due to the

difference in the power density. This can be easily seen looking into the state of the art solutions

regarding high power S band applications.

Since the future design should resort to discrete active devices, due to availability restrictions

of integrated circuitry, balanced designs like Class E implementation or push pull configurations

should be avoided, since matching is particularly hard when discrete elements are available. This

way, the most adequate PA architecture is a multistage PA.

Class C amplifiers are not common when a high gain is required, having particular interest

when high efficiency is the main objective, or in some cases, in the last stage of gain to help with


efficiency [50]. Since the order of priorities consists in efficiency, then gain and finally linearity, a

Class C is not the best option.

This leaves Class B, AB, F and F inverse, all as viable options, with the most adequate solution

probably being an AB or B for driving, since the efficiency is not critical at that stage, and a F or

F inverse in the last stage, to guarantee a reasonable efficiency.

Chapter 3

PA design steps and simulations

The main goal of this thesis was to design a high power amplifier (greater or equal than 200 W)

capable of operating in S or L band. In the previous chapters, it was concluded that the operation

frequency to be used would be 2.4 GHz with the best possible efficiency, ideally over 50% with

little restrictions regarding the bandwidth and linearity.

In this chapter, the several steps necessary to develop a good performing amplifier are de-

scribed.

Starting with the active device section, where the device is selected and it is explained how the

device model is included in the following simulations.

Then, the operation point of the chosen device is studied, followed by the development of

the surrounding networks of the active device, mainly power splitter, power combiner and bias

networks, responsible to enforce the correct behavior of the circuit at the bias point.

A stability analysis is the next step in the process, where it is tested if the system is stable in a

small and large signal operation.

Adjustments to the surrounding networks to stabilize the system are made, creating the neces-

sary conditions to inspect what is the optimum load to present to the device’s output and input in

order to maximize efficiency power and gain wise, a process commonly called Load Pull.

Given the desired output and input impedances, one must create a matching network capable

of adapting the 50 Ω ports into the required impedances at the various harmonics.

To top off the design process, a detailed performance characterization of the device is made in

the last section.

Some mistakes were made during the developing process, which forced the repetition of most

of the design process. Despite the fact that most of the presented results and details about the

development process contemplate the final iteration, occasional descriptions of the former attempts

will be done, focusing on the errors made and on why they were important to overcome.

50

3.1 Active device 51

3.1 Active device

3.1.1 Active device selection

To begin the design process of a power amplifier, the active device selection must be the first

step. After the selection is made, a simulation model can be obtained from the manufacturer’s

design support.

The selection process took into account three main factors: the selected device should be

capable to output at least 200 W of power; the operation frequency of the amplifier should cover the

2.4 GHz, and it should be an economic solution since this project has a limited budget. Searches

on multiple vendors revealed that the BLP2425M10S250P power LDMOS transistor by Ampleon

is suitable for applications of up to 250 W at frequencies from 2.4 GHz to 2.5 GHz [51].

Despite the fact that Laterally Diffused MOSFETs technology is not the best power density

wise, the selected transistor manifested promising results in the datasheet with drain efficiency

of 66.5% in the continuous mode and 67.5% in a pulsed mode with a duty cycle of 10%. It is

important to also point out that this results were obtained by the producer having a gain of 16.4 dB

at 2.45 GHz. So it is expected to have a slight performance degradation when operating at 2.4 GHz,

since one is operating on the edge of the suitable frequencies.

The device has a double transistor configuration being the source terminal shared and acces-

sible at the bottom part of the piece, maximizing the contact to the ground plate where it will

be mounted. Besides that, it has four more pins being the two gates and two drains, as one can

see in figure 3.1a. Regarding the thermal terminal T in figure 3.1b not much information was

(a) Transistor outline (image adapted from[51]) (b) Transistor model symbol

Figure 3.1: Transistor ports

found. Documentation regarding the ADS model was not available and the design support team

by Ampleon was not very helpful when contacted.

PA design steps and simulations 52

The only information found was on a model of the transistor for the Microwave Office software

by Cadence, that stated that the "T_ext" is the thermal node of the device and should be connected

to ground or used in thermal networks [52].

Since no documentation was provided for the ADS model, several tries were made to under-

stand the operation mode of that port. Applying different voltages showed no difference in the

device performance, and probing the terminal voltage a constant value of zero was always mea-

sured, so its usefulness was disregarded for the rest of the design process.

3.1.2 Active device interface

In order to integrate the transistor model in the circuit, one firstly used the symbol model

directly in the simulation, but quickly realized that in order to accurately take advantage of the

transistor model behavior, an adequate interface should be implemented between the transistor

component, presented in figure 3.1b, and the surrounding networks.

Since the active device has two drain ports, a power combiner must be made in order to convert

them into a single output. Besides that, there must be ports to the bias networks and also ports for

the two gate inputs and the transistor pad ports.

Because the operation frequency of the layout model presented in the datasheet is not very

different from the operation frequency goal, most of the design process took the circuit example,

presented in figure 3.2, as a good starting point.

Figure 3.2: Circuit example presented in the datasheet for 2.4 GHz [51]

In order to develop a more exact model, the printed circuit PCB datasheet of the example

circuit, also provided by the manufacturer was used [53], from which an accurate layout of the

3.2 Layout generation and simulation 53

transistor’s footprint was extracted. After that, an electromagnetic simulation of the layout was

made, generating the EM model to be used. A symbol was generated from the layout, allowing an

integration with the ideal model, as one can see in figure 3.3.

Figure 3.3: Transistor footprint integration

It is important to mention that as the source terminal will be connected to the ground plane

through a relatively large pad, it was considered an ideal ground for the simulation, simplifying it.

More information on the layout simulation process will be given in the layout section 3.2.

3.2 Layout generation and simulation

Before proceeding to the next development stages, it is important to detail the methodology

regarding the Electromagnetic simulations, model generation, as well as the chosen substrate. The

chosen substrate was the two layer FR-4 by JLCPCB. The choice was made with the producer of

the boards in mind, since they are known to make reliable RF Boards at good prices.

The substrate specifications were obtained in [54], presenting the following characteristics:

Substrate Height, H 0.8 mmDielectric Constant, Er 4.5Conductor Thickness, T 0.035 mmDissipation Factor, TanD 0.015

Table 3.1: Substrate characteristics obtained from [54]

An important detail to take notice is that the considered dielectric constant was not 4.5 as men-

tioned but 4.4, a common value used by RF engineers at the 2 GHz frequency range, as revealed

in a research of the FR-4 dielectric properties variation for higher frequencies [55].

Across all the layout simulations, the port configuration was essential to capture the most accu-

rate behavior of the circuit. Edge ports were configured as TML zero length with 50 Ω impedance,

as suggested in [56]. In ports with component connections auto mode was used with a high


impedance, 10000 ohm, also suggested in [56], where the geometry of the pad was drawn on top

of the main copper layer, recreating the Surface Mounted Devices (SMDs) pads interaction with

the mounting surface.

Since the operation frequency of the amplifier is in the gigahertz range, the wave length is in

the order of centimeters, so it was considered that the component pads should be simulated as area

pins, since their size is relatively close to the signal wavelength, as suggested in [25].

The frequencies swept in the Electromagnetic (EM) simulation were an adaptive sweep from

1 Hz up to 15 GHz, including the fifth harmonic, being this information particularly used to in-

vestigate the device’s stability. Furthermore, frequencies from DC up to 12 GHz with a 2.4 GHz

step were also swept, the DC being used for DC/IV purposes, and the remaining for Harmonic

Balance (HB) simulations and single tone simulations.

A final notice to make is, while the study of the effect of the different passive components

values was being made, ideal models were used. Once the values were decided, a spice model of

a more realistic performance was utilized.

For the case of the inductors, there were no models available, and for the resistors it was made

an assumption that the behavior would be close to ideal.

The ceramic capacitor models were obtained from the Kemet simulator [57]. Even though

some of the capacitors used were not from the mentioned brand, it was considered that they would

not differ too much between manufacturers. The electrolytic capacitor model was obtained directly

from the producer website.

3.3 Operation point

With the active device selected, one is in good condition to start the PA design flow. As stated

before, the most interesting classes of operation would be class AB, F or F inverse, as they usually

present good efficiency in situations where linearity is not critical.

The first step to investigate the limits of operation is to define the "soccer pitch" mentioned in

section 2.4.3. After checking the datasheet, it was concluded that the breakdown voltage is 65 V

and the VGS must be between −6 V and 13 V. Considering this information, a DC simulation was

made sweeping the VGS and the VDS in the mentioned range.

Using an Advanced Design System (ADS) display template, one was able to directly estimate

the performance of the device while varying the operation point.

Another factor that conditioned the selection of the bias point was the available power sources

at FEUP for this thesis. There were two options, one of them with 12 V and a maximum current

of 25 A, and the other with 28 V and maximum current of 5 A. The author considered that for an

easier implementation the 28 V one would be used and associated in parallel if more current was

required. The value sits close to the rule of thumb of half the breakdown voltage and close to the

VDS voltage of the datasheet examples of 32 V [51].

So, the selected point of the marker 2 was with a VDS of up to 28 V being the VGS = 2.279

chosen such that the output power PDC in figure 3.4a would be bigger than the required power,

3.3 Operation point 55

all this while maximizing efficiency and gain. The results obtained evidence a class AB with a

conduction angle of about 193 deg and a drain efficiency of almost 70% with a gain larger than the

20dB mark and an output power of 53.74dBm.

(a) DC IV simulation results with the transistor model

(b) DC IV simulation circuit with the transistor model

Figure 3.4: DC IV simulation with the transistor model

It is important to notice the mentioned results followed a simulation of the transistor model.

As the next step in the design is the stability analysis, more attention was put into simulate the

circuit more accurately, so the DC IV examination was repeated, now with the transistor footprint

mentioned in section 3.1.2.

The results in figure 3.5a differed from the previous ones, specially on the DC current and

the output power, as this time the biasing was only done in one side of the transistor, just like the

datasheet example of figure 3.2.

Nonetheless, the purpose of the template used was met. It was shown that a VDS of 28 V and

a VGS between 2 V and 3 V would fulfill the output power requirement with a good efficiency and

gain, if an adequate inclination of the load line is presented, that only happens if a suitable load

resistance is applied, as explained in section 2.6.1.


(a) DC IV simulation of the transistor model with footprint

(b) DC IV simulation circuit of the transistor model with footprint, circuit detailed in figure 3.3

Figure 3.5: DC IV simulation of the transistor model with footprint

3.4 Surrounding networks

In order to analyze the stability of the device, it is important to insert it in a somewhat complete

circuit that resembles the final one. This way, the behavior of the surrounding networks is taken

into account stability wise.

Due to the double transistor nature of the active device, a power divider to split the input signal

into the two gates is required to be implemented, as well as a power combiner to merge the drains

signal into the output.

Since the transistor footprint presented in figure 3.3 has already present the combiner, the

remaining networks to be implemented are the power splitter and the gate and drain bias gate.

Only then an accurate stability analysis can be made.

3.4.1 Power Divider

The power divider was implemented referring to [56], where a brief theoretic explanation is

given, followed by the design process of the Wilkinson Power Divider (WPD). The document by

3.4 Surrounding networks 57

Keysight regarding power dividers, [58], was also an important resource, giving practical infor-

mation for the circuit implementation with microstrip and how to simulate it in ADS.

A Wilkinson Power Divider is a three port network that splits the signal of one port into the

remaining two. This division can be regulated, being usually equitable, without dissipation and

mismatch losses, suffering a loss of only 3 dB relative to the input [56].

To optimize the splitting process, obtaining a lossless, reciprocal, matched and providing high

isolation between the output ports, the scattering parameters of the three ports network must re-

spect equation (3.1). To do so, the configuration presented in figure 3.6 must be realized, where a

line with a characteristic impedance Z0 divides into two quarter wavelength of√

2Z0 lines with an

isolation resistor of 2Z0 [4, Chapter 7].

S =

S11 S12 S13

S21 S22 S23

S31 S32 S33

=− j√

2

0 1 1

1 0 0

1 0 0

(3.1)

Figure 3.6: Transmission line equivalent of the WPD

In order to implement the WPD in microstrip, the steps mentioned in [58] were followed. The

considered Z0 along the circuit was 50 ohm, so using the linecalc tool, the width of the 50 ohm and

70.7 ohm lines was calculated, as well as the length of the quarter wavelength section for 2.4 GHz

and the chosen substrate. The chosen substrate and how it was simulated is detailed in section 3.2,

as well as the port configuration and the frequency plan.

It is always worth reminding that the linecalc tool uses equations internally to calculate the

dimensions of the microstrips, which are well defined in conditions where the substrate width

(d) is much smaller than the wavelength (λ ). When this condition is met, approximations of the

microstrip performance can be done regarding phase velocity (vp), propagation constant (β ) and

characteristic impedance Z0.

Since some field lines are outside the conductor, mainly in the surrounding air and substrate,

a correction is applied at the dielectric constant called effective dielectric constant (εe), being


calculated by the following equation:

εe =εr +1

2+

εr−12

1√1+12d/W

(3.2)

With all the mentioned variables and the line width (W), one can calculate the respective charac-

teristic impedance Z0.

Z0 =

60√εe

ln(8d

W + W4d

)for W/d ≤ 1

120π√εe[W/d+1.393+0.667ln(W/d+1.444)] for W/d ≥ 1

(3.3)

The reverse process can also be done to determine the dimensions for a given Z0,

Wd

=

8eA

e2A−22π

[B−1− ln(2B−1)+ εr−1

2εr

ln(B−1)+0.39− 0.61

εr

] (3.4)

being A and B given by:

A = Z060

√εr+1

2 + εr−1εr+1

(0.23+ 0.11

εr

)B = 377π

2Z0√

εr.

(3.5)

The length (`) of a given line is directly related with its electric length (φ ), that is, the phase offset

of a given signal will be obtained by a product of the length and the coefficient that measures the

phase delay per unit of space, which corresponds to the propagation constant (β ). This way, to

determine a line’s length one just needs to use

φ = β`=√

εek0`

`= φ(π/180)√εek0

(3.6)

where β = k0√

εe and k0 =2π f

c .

With the EM model generated, and associated with the isolation resistor in the respective place,

the performance of the WPD was simulated. The first results showed the input resonance, the S11,

minimum value at 2.5 GHz. A small adjustment of quarter wavelength section length centered it

back in 2.4 GHz, leading to the results presented in figure 3.7b. It is important to notice that the

output ports isolation was not ideal, being maximum at a frequency different than the operation

frequency, however that did not affect the symmetrical splitting of the signal, since an analysis of

the output ports signal in phase and amplitude showed no notorious differences, as one can see in

figure 3.8.

Another last detail is that the 50 Ω lines in the output ports were distanced to be in line with

the transistor gates, an aspect that would help the implementation of the intermediate matching

network, to be detailed in the following sections.

3.4 Surrounding networks 59

(a) WPD layout(b) WPD S parameters with a 100 Ω isolation resistor

Figure 3.7: Wilkinson Power Divider

Figure 3.8: Wilkinson Power Divider magnitude and phase balance between each branch (S21 andS31)

3.4.2 Bias network

The bias network is a fundamental part of the circuit that ensures the DC operation point. This

way, it should impose a DC voltage at the drain and gate, being completely independent of the RF

behavior of the circuit, if not used for matching simultaneously.

The classic method for bias networks is the use of a RF choke between the power supply and

the terminal that will be biased, together with a DC block capacitor between RF inputs/outputs and

the bias ports. A short circuit is created at DC by the RF choke, while simultaneously developing

an open circuit for the RF signal. The DC block capacitor does the opposite, as it creates a low

impedance path for the RF signal and, ideally, an open circuit for DC, preventing the DC signal

from escaping to the RF parts of the circuit.

The bias network design was inspired by the datasheet [51], where the impedance chokes re-

sulted from the impedance of the decoupling capacitors being inverted by the quarter wavelength

line connecting to the gate/drain. The decoupling capacitors resonate close to 2.4 GHz, presenting

low impedance at that frequency and being close to an open circuit at very low frequencies. In-


verting this behavior, one allows the DC signal to freely travel from/into the bias network, whilst

preventing the RF signal from escaping.

Analyzing figure 3.2, one can also identify a snubber created by the R3 and C7. These two el-

ements have the function of removing unwanted transient peak voltages in the drain bias network.

This is particularly important when there is some inductance present, since peak voltages may be

common when switching the power source [59].

To furthermore filter power source noise in the bias networks, ferrite beads were used in the

gate side, as they are useful to create small value RF chokes, with low Q factors and being lossy

at higher frequencies, working as an effective low pass filter in situations where the current value

is not critical [60, Chapter 10]. An inductor rated for up to 28 A was used for the same job in the

drain bias network.

The ferrite beads chosen were 2743019447 by Fair-Rite [61], and the inductor was SLC7530D-

500MLC [62] by Coilcraft, connected in a dual inductor mode.

In order to select the most ideal DC block capacitor, a capacitor behavior simulator was used.

As a general rule, the size of the capacitors and resistors used throughout the circuit were intended

to have the canonical 1206 footprint size. With that in mind, and using the Kemet capacitor

simulator [57], with the C0G dielectric as it was the more common, and with voltage rating of

50 V, a sweep of the available capacitors was made, analysing the impedance and the Equivalent

Series Resistor (ESR) along the frequencies. The selected capacitor should ideally be a short

circuit for the operation frequency, 2.4 GHz, having minimal impedance and minimal ESR.

The resistors chosen were the thin film type, since their production process results in more

stable resistances with less parasitic and noise and better heat dissipation compared to their thick

film resistors counterparts [63]. The increase in price is justifiable, since mass production is not

the goal here, where the price difference starts to be notorious.

Figure 3.9: Capacitor impedance and ESR obtained from [57]

The selection of the adequate DC blocker was disregarded in the first iterations of the design,

since in those iterations other mistakes were made, to be discussed in the following section, that

"benefited" the performance of the circuit. So, for some iterations the capacitor used was 22 pF

3.5 Stability 61

following the circuit example of figure 3.2. However, examining figure 3.9, one can easily say that

capacitors around the 7 pF mark resonate much more closely to the operation frequency.

The remaining capacitors and resistors configuration and values followed the reference design

[51], since they should present a promising point to start the stability analysis on. As previously

mentioned, the first iteration of the transistor and surrounding networks was simulated only on the

schematic level, being the final result presented in figure 3.10.

Figure 3.10: First iteration of the circuit

The schematic simulation did not accurately represent the behavior of the circuit, presenting

results of an apparent good performing stable circuit. This gave the author a false confidence

to proceed with the design. The complete layout generation and simulation after load pull and

matching network, revealed a non stable system.

This required a different approach, the surrounding networks were tested in order to, in the

first place, obtain a stable circuit. The improvements will be discussed in the stability section 3.5.

3.5 Stability

Although there were multiple network configurations that needed a stability analysis, the pro-

cess was the same for every one.

The drain voltage decided was 28 V, as stated before, and a sweep of the gate voltage from

2 V to 3 V was made while analyzing the S-parameters.

To determine the effective operation point, one analyzed the small signal stability of the circuit,

applying the µ test to the load and the source across the interest frequencies while sweeping the

gate voltage. This was the chosen method since it expresses an intuitive result (distance from the

smith chart to the least stable point), effectively quantifying how stable a system is for the given

conditions.


3.5.1 Schematic simulations

The first circuit to be analyzed was the one in figure 3.10. Initially, the circuit was unstable, so

adjustments in the networks needed to be made with the tuning and optimization tools.

Varying the passive values did not affect the results, but varying the widths of the quarter

wavelength lines did. In addition, two intermediate matching networks were introduced after the

WPD and after the combiner, where the width of the series lines were also adjusted.

Between line segments with potentially very different widths, tapered lines were introduced to

smooth the impedance transition, minimizing wave reflections as suggested in [4, Chapter 5].

During the optimization process the small signal gain was also introduced as a stability goal,

working like a trade-off since the gain usually suffers when one strives for stability.

With a gate voltage of 2.8 V and adjusting the dimensions of the lines, an unconditionally

stable circuit with a S21 of 15 dB was obtained.

Figure 3.11: Stability analysis first iteration results, stability factors on the left and gain on theright

With these values, one was in good condition to proceed to the next stage, however, as men-

tioned, the process had to be repeated two more times. The final validation of the layout already

with matching networks revealed an unstable system for low frequencies, that is evident in the µ

test, but also in the oscillations of the large signal stability test of figure 3.12, even though a 2 V

gate voltage was used in the later stages of the development process.

The large signal stability analysis consists of a step in the gate voltage, exciting several fre-

quencies while doing so. If the output voltage does not oscillate, or if these oscillations die out

quickly, it means that the loop is stable. This is usually done with a harmonic balance simulation as

done when extraction of the transfer function is necessary [64]. However, the transient simulation

proved to be a quick way of evaluating the large signal stability.

3.5.2 Layout simulations

To solve the problems of the first design, a more strict approach was made, where every step of

the design process would be required to have a EM simulation of the whole circuit. This made the

3.5 Stability 63

Figure 3.12: Stability first iteration layout, stability factors on the left and output voltage on theright

tuning and optimizing methods less appealing, since the validation process of a circuit’s alteration

required a new EM model generation, being very time consuming.

The more formal approach, took [65] as the main reference, where refinements of Biasing

Networks for high PA low-frequency stability are discussed.

As stated in [65], the bias networks are the dominant factor in low frequency stability, as-

suming that the DC blocking capacitors are small enough to remove the effect of the matching

networks.

In the same article it is also shown that, typically, there is negative resistance in the real part of

the gate input impedance for up to a few hundred megahertz. To remove this instability, one can

increase the value for the drain inductance. When implemented with a quarter wave length, the

low frequency inductance is given by (3.7), where Z0 is the line impedance, l is the length and c is

the speed of light [26].

L = Z0lc

(3.7)

So, to increase the inductance one could decrease the width of the line, effectively increasing the

characteristic impedance, which could affect the current handling capabilities, or increase the line

length in multiples of λ /2 increasing the inductance while maintaining the impedance inverting

capabilities.

To decrease the current handling problems with negligible change in microstrip characteristic

impedance, one could increase the thickness of the line by soldering a small sheet of metal onto

the line [19, Chapter 3].

One other method to reduce dissipation in narrow microstrip lines is to use a double bias

topology, which makes more sense in the context of this thesis, since inside the active device there

are two transistors.

The other important technique to address the negative resistance in the gate input is to use

a series resistor in the gate bias network. Various circuit topologies are presented in [65] with

the position of the resistor in various points, however in [66] it is said that the gate resistance

should be placed as close as possible to the device gate for better protection against Electrostatic


Discharges (ESDs) and oscillations in situations where the bias network does not serve matching

purposes, which is the case in this thesis.

With this in mind, various layouts were simulated. Firstly, an attempt was made to vary the

position of the gate resistor, which did not produce significant effects. Increasing the length of the

drain bias line improved the stability, but it was still not enough. The same happened with a dual

feed configuration with reduced width drain lines.

The stability problem was solved adding an extra resistor after the ferrite bead in the gate bias

before the decoupling capacitor of 1 µF, creating a low pass filter. Any resistor with a value greater

than 1 Ω did the job, independently of the remaining configuration of the circuit, meaning, even

the most "simple" case, with single feed and a shorter line (λ/4) resulted in a stable circuit, so

this was the selected one as optimal design, since it was stable with the same S21 as the others

and easier to implement. In the end, the selected resistor was 10 Ω creating a RC low pass with a

cutoff frequency of about 16 kHz.

The simulated design was already done with the capacitor’s models, with 22 pF as DC blockers

and 10 Ω resistors close to the gate and in the combiner. The stability results of this design can be

seen in figure 3.14.

In the following design steps it was realized that, since the design of the layout until the

load DC blocker was already established, the matching could only be done in a network after

that one. This way, it had less degrees of freedom compared to a circuit where the intermediate

matching networks (the networks after the WPD and the combiner) could be tweaked to improve

the matching and, consequently, the performance.

Following this rationale a new approach was made, restarting from the stability analysis point

where a hybrid design was followed. Some tests were made, concluding that the layout simula-

tions were close to the schematic simulations when the connections of the different elements have

the same width. This way, the intermediate matching networks were simulated in schematic as

suggested in figure 3.15, with tapers on each end to match the width of the connections. By doing

this, the use of T-junctions, that also degrade the reliability of schematic simulations, was avoided

[25].The schematic networks were, as previously, composed by two microstrips with independent

widths and tapers.

On this third try of development, it was realised that the DC blockers used were not ideal for

2.4 GHz operation, being replaced by the 7.5 pF capacitors mentioned in section 3.4.2.

With the double resistor in the bias of the gate, the dimensions of the intermediate networks

were optimized to maximize stability. The layout of the unconditionally stable circuit was obtained

to assure the stability of the design. The obtained layout can be seen in figure 3.16a with the results

in figure 3.16b

Although not necessary, the author decided to seek an unconditionally stable circuit. Analyz-

ing the stability circles from 1 Hz up to 16 GHz of the final layout, one can see that all the circles

are outside, meaning that every load value is possible, always leading to a stable system, at least

as long as the circuit’s |S11| and |S22| are less than one, as stated in subsection 2.4.4.1.

3.6 Load Pull 65

(a) Large signal stability simulation circuit

(b) Gate bias network lumped elements

(c) Gate drain network lumped elements

Figure 3.13: First stable design

In a non unconditionally stable circuit certain regions of the unitary smith chart would contain

unstable circular regions, meaning that the possible load selections would be limited.

3.6 Load Pull

Since the stability analysis led to always unconditionally stable circuits, or at least apparently

in the first iteration, the load selection was not limited, being a similar process in all cases, there-

fore only the last implementation will be documented here.

An ideal design would, firstly, satisfy the minimum 53 dB of power delivered with the best

efficiency possible, with the best possible gain.

Like so, the selection of an optimal load was necessary. A load that, balancing the different

goals, could guarantee 53 dB of power delivered, with a Power Added Efficiency (PAE) of at least


Figure 3.14: Stability results, stability factors on the left and output voltage on the right

Figure 3.15: Hybrid circuit layout

50% and the best possible gain.

The load pull was made possible by the ADS Load Pull One-Tone Load Pull Simulations

Constant Available Source Power and Load Pull One-Tone Load Pull Simulations Swept Avail-

able Source Power. In these simulations, a harmonic simulation is made, while the load tuner

sweeps a given interval of loads, calculating the power delivered, efficiency and gain for every

load, resulting in constant efficiency and power delivered contours.

Some initial simulations were made to understand the impedance range that one should focus

on to maximize efficiency, and the source impedance to use. The source impedance 50 Ω was

initially updated as the complex conjugate of the ZIn_at_MaxPAE , being a recursive process.

The first template calculated the load that gives maximum efficiency, however, in that load,

the power delivered was not enough, so a nearby load should be chosen with slightly more power

delivered and, obviously, less efficiency (figure 3.18). The contours could also be seen in this

template (figure 3.19), being a very important tool to a designer.

3.6 Load Pull 67

(a) Hybrid design circuit

(b) Hybrid design stability results, µ factor on the left and large singal stability on the right

Figure 3.16: Hybrid design

Figure 3.17: Hybrid circuit stability circles from from 1 Hz up to 16 GHz

To find the ideal point, a sweep around the 38.8 dBm input power was made with the other

template. Using the data display that allows the selection of the gain compression (Display con-

tours at X-dB Gain compression) the 3 dB compression point was selected, as linearity is not

critical. The point was selected in order to satisfy the minimum required output power of 53 dBm,


Figure 3.18: Hybrid circuit load pull maximum PAE point obtained with 38.8 dBm of input power

Figure 3.19: Hybrid circuit load pull power delivered and efficiency contours with 38.8 dBm ofinput power

while maximizing the Power Added Efficiency (figure 3.20). On figure 3.20, one can also see

Figure 3.20: Hybrid circuit load selection with 3 dB of gain compression

the suggested harmonic impedances for the load and for the source. Regarding the tuning of the

harmonics, several values were tested, such as alternating odd and even harmonics with open and

closed circuits, all closed, all open, only imaginary, and a slight benefit presenting an open circuit

to all the harmonics in the load and in the source.

3.7 Matching Networks 69

Therefore, the goal of the matching networks, should be 47.644− j15.09 for the source

impedance at fundamental, 15.759− j36.624 for the fundamental load impedance and open circuit

for the remaining harmonics.

3.7 Matching Networks

To achieve the required impedances, the Impedance matching tool was given a shot, as this

tool allows for experimentation of different typologies of matching networks quickly with various

complexities. However, it felt counter-intuitive, with various simulation errors, so the idea was

abandoned.

Firstly, the output matching was tackled, as it was the most critical, being succeeded by the

input matching network development.

3.7.1 Output matching network

The first output matching network to be developed was supposed to be for a class F amplifier,

with the even harmonics short circuited, being the typology of the matching network inspired by

[67]. Although the impedance matching required in the hybrid approach was not characteristic of

a class F, the typology was maintained, as it was versatile and it did not require the use of lumped

elements that could be a problem to find in the 200 W range of power.

The microstrips with the two open stubs where initially implemented with ideal lines, optimiz-

ing the impedances of each harmonic to the requested ones.

Figure 3.21: Ideal output matching network configuration

The ideal design was later converted into microstrips, with the substrate of table mentioned in

section 3.2 with the help of the Linecal ADS utility. Tapers and T junctions were added, as well as

50 Ω lines in the end and the beginning, to make the circuit ready for layout conversion. After the

conversion, another optimization was made, integrating the output matching network maximizing

the PAE and the load power, as well as minimizing the harmonic content of the second and third

harmonic, reducing distortions.

3.7.2 Input matching network

For the matching of the input the same approach was done, developing the Input Matching

Network (IMN), starting with ideal microstrip lines.

Despite that, a quick integration test revealed that even the input matching network with ideal

behavior did not present substantial changes in the performance of the circuit and, it was decided


Figure 3.22: Output matching network microstrip design

that the input matching would be done by the intermediate matching network that followed the

WPD.

3.7.3 Final matching

Figure 3.23: Final matching optimization, with intermediate matching networks in schematic forminside the HYBRID_Sample_PA block as shown is figure 3.15

To finish the optimization process of the hybrid design, both intermediate matching networks,

as well as the OMN, were taken as variables, where the optimization goals continued to be effi-

ciency, power delivery, and harmonic minimization. When the best solution was found and the

layout was generated, the obtained results of the layout achieved a PAE of 51.625%, maintaining

a power delivered of 53.25 dBm with the spectral content of figure 3.24. Since the stability con-

ditions of the last stability test were altered, meaning the intermediate matching networks were

slightly changed and a new matching network was added, a new stability test with the new lay-

out was made, revealing that the hybrid design was still stable. The final layout for RF signal

simulation can be seen in figure 3.25, where the bias network layout is disregarded since the first

3.8 Results 71

Figure 3.24: Harmonic content of final matching optimization, with a -147 dBm of DC isolation

decoupling capacitor presents a short circuit for signal. And for DC simulations the electric length

between the components is irrelevant.

Figure 3.25: Final layout for simulations

3.8 Results

Figure 3.26: Efficiency and gain versus input power on the left and output power on the right

With the final layout obtained, a second HB simulation with a sweeping signal power to un-

derstand the variation of the different variables with increasing power was made.


Figure 3.27: Fundamental, first and second harmonic powers

One can notice a drain efficiency of 55%, which falls short from the 65% from the datasheet,

value at a bias condition of 32 V in the drain with a quiescent current of 100 mA. Analyzing figure

3.27, one could easily calculate IP2 and IP3 in order to conclude about the linearity of the system.

Figure 3.28: S Parameters results

Additionally, the S-Parameters were also studied for the normal bias conditions of VGS = 2 V

and VDS = 28 V.

3.9 Monte Carlo Simulation and yield analysis

To analyze the susceptibility of performance degradation due to process variations and compo-

nent tolerances, a Monte Carlo simulation was done, which tested the circuit behavior for different

variations of the discrete components and used the accuracy of the PCB printing process. The

uncertainties considered can be consulted in table 3.2.

The uncertainty of the microstrip dimensions were considered to be 25% of the drilling accu-

racy (0.2 mm with JLPCB [54]), following the error percentage used in [25].

The substrate thickness tolerance was obtained directly from [54] for boards with less than

1 mm of thickness (0.8 mm). Although the source mentions a tolerance of 0.1 mm, it is relative

to the whole board thickness. A first statistical analysis revealed that a 0.1 mm tolerance greatly

3.9 Monte Carlo Simulation and yield analysis 73

dispersed the results, so a more realistic value of the substrate thickness tolerance of 0.05 mm was

used.

The capacitor tolerance was extracted from its datasheet [68], and the chosen resistors were

all chosen to have 1% tolerance, as one can see in [69]. To apply the variations of the circuit

Variable UncertaintySubstrate thickness tolerance ± 0.05 mmMicrostrip line Heigth ± 0.05 mmMicrostrip line Width ± 0.05 mmCapacitor Value ± 0.25 pFResistance values ± 1%

Table 3.2: Tolerance values used in Monte Carlo Simulation with a Gaussian distribution

dimensions, the layout of 3.25 had to be converted to schematic and the capacitor models extracted

from [57] were replaced by ideal capacitors, so the analysis was valid.

The layout was converted to schematic, excluding the transistor footprint that had no easy

implementation.

During this conversion, it was noticed that the performance of the device was affected, once

again, proving that the schematic simulation alone is not a good representation of a circuit com-

portment.

5 10 15 20 25 30 35 400 45

20

30

40

50

10

60

Input Power (dBm)

Sch

emat

ic O

utp

ut

Po

wer

(d

Bm

)L

ayo

ut

Ou

tpu

t P

ow

er (

dB

m)

5 10 15 20 25 30 35 400 45

10

12

14

16

18

8

20

Input Power (dBm)

Sch

emat

ic T

ran

sdu

cer

Gai

n (

dB

)

Lay

ou

t Tr

ansd

uce

r G

ain

(d

B)

5 10 15 20 25 30 35 400 45

10

20

30

40

50

0

60

Input Power (dBm)

Sch

emat

ic P

AE

(%

) L

ayo

ut

PA

E (

%)

Figure 3.29: Performance comparison between layout and schematic conversion

Notwithstanding, Monte Carlo simulation dispersion of the different trials traduces the relia-

bility of the design.

Ideally, the designed PA should have an efficiency greater than 50%, while maintaining an

output power of 53 dBm. Projecting this into the schematic simulation, it was assumed that the

margin of acceptance of a given design is an efficiency greater than 30%, since the conversion

process lost approximately 20% of efficiency compared to the nominal case.

Since the output power does not differ significantly, one can directly plot the efficiency and

gain versus the output power with the conversion explained above.

Analyzing the dispersion graphs for the defined tolerances, one can say that the results present

variation, since the 1000 Monte Carlo iteration graphs could be more "compact". This problem

was even worst in the first Monte Carlo simulation, where each sub circuit of the network, namely

bias networks and matching networks, had independent definitions of the substrate. This was


5 10 15 20 25 30 35 400 45

10

20

30

40

50

0

60

Input Power (dBm)

Ou

tpu

tP

ow

er (

dB

m)

10 15 20 25 30 35 40 45 505 55

8

10

12

14

16

6

18

Output Power (dBm)

Tran

sdu

cer

Gai

n (

dB

)

10 15 20 25 30 35 40 45 505 55

10

20

30

40

0

50

Output Power (dBm)

PA

E (

%)

Figure 3.30: Monte Carlo analysis output power efficiency and power delivered with 1000 itera-tions

corrected to a single substrate width variation, which should represent reality more accurately, due

to the small dimensions of the board.

Furthermore, to quantify the reliability of the design, and since the main focus of this thesis’

PA is efficiency and power, a yield analysis was made, where it was counted the number of designs

with a peak PAE greater than 30% at an output power of 52 dBm (considering the 1 dB difference

of the schematic relative to the layout output power visible in figure 3.29).

With an uniform substrate variation for all the networks, the number of fails in 1000 tries was

183, translating to a success percentage of approximately 82%.

Figure 3.31: Monte Carlo analysis harmonic power relative to the carrier

To evaluate the linearity effects, a sweep of the harmonics’ power for the given conditions was

also done. As one can see, the device, which is considerably non linear, did not suffer too much.

Around 10 dB variations were detected, making it only useful for constant envelope applications

where linearity is not critical.

A statistical analysis on the S parameters of the device was also done, but the outcome was the

same as the above. The results were affected during the schematic conversion, and the dispersion

was relatively compact, as one can see in figure 3.32 the effect it had on the small signal gain.

With a perfect conversion of the layout behavior, one could calculate the stability factors from

the S parameters and evaluate the number of designs potentially unstable with a yield analysis,

however such was not possible for the reasons mentioned, making the stability analysis of non

representative S parameters unviable.

3.10 AM-PM distortion 75

Figure 3.32: Monte Carlo analysis S(2,1) variation relative to the nominal value

Although this statistical analysis step was not ideal, since one was not sweeping the actual

performance of the device, or at least what should be an accurate representation of the design, it

provided a good idea of how much the process variations could affect performance, for example,

examining figure 3.32, one can say that a 2dB variation at a given frequency is to be expected

from the projected value. Consequently, this is an important step that gives the designer some

perspective and confidence to advance into physical implementation.

3.10 AM-PM distortion

The design goal of this thesis’ PA is not to have the most linear amplifier possible, since it

was decided that the modulations to be used would be constant envelope. Considering complex

communication systems, like Wide-Band Code-Division Multiple Access (W-CDMA), where in-

formation is carried in the signal amplitude, that require an amplifier with good amplitude linearity

[31, Chapter 2], such is not needed when constant envelope modulations are used. This is even

worsened by the typical Peak to Average Ratio (PAR) of close to 10 dB, injuring the efficiency of

the system, or requiring efficiency techniques like envelope tracking [24, Chapter 1], increasing

the complexity of the circuit.

This way, constant envelope systems are usually easier to implement, and the best metric to

measure their linearity is by measuring AM-PM distortion, which quantifies how much a variation

in the input power affects the output signal phase.

Once more, using the "One Tone Harmonic Balance Simulation, swept frequency and power"

ADS template, the AM-PM distortion was obtained, as one can see in figure 3.33 The measured

value of distortion was done in a narrow band, since that is the application requirement.

3.11 Board generation

In order to have a ready to print Printed Circuit Board (PCB) there is still some important

details to be taken care off. Firstly, it is important to remember how the PA will be physically

mounted. Contrary to what is suggested by the circuit example of figure 3.2, it was decided that


Figure 3.33: AM-PM distortion for operation frequency and neighbours

the load and source sides of the circuit would be in separate boards with the transistor in the

middle, mounted directly onto a conductive heat sink that provides a homogeneous ground plane.

Another concern regarding the board layout was to make the circuit adjustable during the test-

ing phase. This way, if for example the maximum gain was shifted from the operation frequency

or was much lower than expected, by tweaking some critical parts of the circuit one could solve

these problems.

One of the aspects is the variation of the capacitors’ values and position, specially the first one,

as it determines the actual length of the quarter wavelength line, as one can see in figure 3.34a.

Another way of tweaking is varying the dimensions of the stubs of the matching networks. By

surrounding the more sensible areas, performance wise, with a mesh of small microstrip squares,

one could adjust the geometry of said zone by extending existing stubs or creating new ones, by

simply creating solder bridges between the dots. Furthermore, one can print the circuit with stubs

smaller than the nominal length, soldering to the normal length and removing the solder if shorter

stubs are required, which was the case for the width line leaving the combiner and the length

of open stubs in the OMN. This technique is commonly known amongst the RF community as

chicken dots [70].

(a) Gate decoupling capacitors with aground ruler

(b) Output Matching Network withchicken dots

Figure 3.34: Layout tuning techniques

On figure 3.34b the output matching network is surrounded by chicken dots and the stubs’

lengths are smaller than the projected ones, due to the reasons stated above.

3.11 Board generation 77

The dots are 0.2 mm by 0.2 mm with 0.2 mm of spacing between them, ensuring the better

granularity of customization, considering that the drill size of the JLPBC is 0.2 mm in this type of

boards [54]. After generating a footprint for every passive element according to their respective

datasheets, the hierarchical approach of the different circuits was converted into a single one with

the flatten tool, and then split into two. On each PCB a ground in the bottom copper layer and

holes for later fixation onto the heat sink from where the Gerber files were exported, were added.

(a) Input board (b) Output board

Figure 3.35: Boards ready to print layouts

Chapter 4

PA practical validation

In this chapter, the experimental validation of the PA design will be detailed. Firstly, the

implementation process will be described, exposing some difficulties that were felt and how they

would affect the PA’s performance.

After that, several measurements will be presented, being the obtained results contrasted with

the simulations. Primarily, the current consumption with no signal present is characterized.

A small signal analysis follows, where it is examined the small signal gain and stability, suc-

ceeded by large signal measurements made in short periods of time (pulsed operation mode), re-

sembling the effective application planned for this device in a moon bouncing system. Lastly, the

active device is replaced and the characterization of the PA is repeated, being its results discussed

here.

4.1 Implementation difficulties

To convert the printed boards into a working PA, the assembling process needed to be com-

pleted.

Firstly, all the components were soldered into their respective place. On this step, it was

noticed that during the generation of the input PCB (figure 3.35a) a misplacement of what should

be a low pass filter resistor at the left of the decoupling capacitors was now on the opposite side.

To make sure this incident did not injure the design, the stability effect was first analyzed in small

signal and large signal and it was concluded that stability was affected, but within reasonable

results, as one can see in figure 4.1.

Furthermore, the obtained PAE of 51.625% and power delivered of 53.250 dBm were only

marginally affected by the misplacement of the resistor, being the results 51.601% of PAE and

a power delivered of 53.237 dBm. The harmonics did not suffer too much, being the biggest

variation less than 0.3 dB, as one can see in figure 4.2.

It is important to mention that to include the effect of the misplaced resistor, an ideal resistor

in series with a microstrip line with the length of the physical length of the resistor was used, since

78

4.1 Implementation difficulties 79

Figure 4.1: Stability results of the miss placed resistor layout, stability factors on the left andoutput voltage on the right

Figure 4.2: Harmonic power difference, between previous design and the miss placed resistordesign

it is effectively making the quarter wavelength longer. Switching the order of the microstrip and

resistor produced essentially the same results.

Another task to be done was the normalization of the stubs’ dimensions, following the tech-

nique mentioned in section 3.11. The selected areas were the microstrip just after the combiner,

being printed narrower than the initial 3 mm, since it was converging into a narrower line in the

optimizations, creating a potential tuning zone, being the open stubs in the OMN the other two

tuning spots.

What should be an easy task, to revert the layout into the designed one, was not that easy,

due to the integrity of the board. When expanding the stubs using the chicken dots, bridging the

small intervals between them, the soldering iron temperature was not well handled, resulting in

the chicken dots being scraped off the PCB. To overcome their uselessness, copper tape was used

to take the layout back to the designed configuration.

With the boards ready, only the transistor is missing to finalize the assembly. Since the tran-

sistor had no fixation mechanism, a small copper plate proved to be an effective method, both for

fixation but also to help with heat dissipation.

With the transistor mounted and its pads soldered into the boards, after adding the SubMiniature

PA practical validation 80

Figure 4.3: Normalization of the layout using copper tape

version A (SMA) connectors and power cords into the bias pads, the PA (figure 4.4) was ready to

test.

Figure 4.4: Assembled design with 50 Ω terminations

One can notice that the heat sink had to be drilled because of the input SMA. This was one of

the many inconvenients that came with external printing of the PCBs.

Because the ordered boards had a relatively high production/delivery time, there was only

time to do one iteration of the design, not being possible to fix some issues, such as the problem in

the gate bias network’s resistor, as well as proper sizing the PCB and hole placement taking into

account the heat dissipator dimensions.

Assuming that the behavior of the PA follows the simulation, the testing must be be done

incrementally. This way, a malfunction in the circuit can be detected early in the test process,

sparing the active device from potential harmful regimes in large signal amplification tests.

4.2 DC characterization

The first test done was the DC characterization, where it is examined if the device consumption

follows what is expected from the simulations without a RF signal.

Two 50 Ω loads were placed in the terminations while measuring the drain consumption for

different bias points. While doing so, the voltages of both the drain and gate terminals were swept

4.2 DC characterization 81

up until the bias point. The measurements did not went past this point, since stability was only

guaranteed until that point, and the operation regime could become unstable with greater voltages.

The gate voltages went from 0 V to 2 V with increments of 0.05 V, and the drain voltages went

from 0 V to 28 V with increments of 2 V. The obtained results can be seen in figure 4.5, where the

brown line corresponds to the 2 V gate voltage and the successive lines are the lower voltages.

Figure 4.5: DC IV comparison between simulation and measured

As one can see, the measured values followed the predicted ones, excluding the biggest gate

voltage that displayed a larger drain current for higher drain voltages.

Although it was tried to maintain all the conditions uniform for every measurement with a

cool off interval between each set of measurements, a feedback loop was created for larger drain

currents, quickly rising the temperature of the device which causes an increase of the current

consumption. To test this theory a stress test was made, where the device was left in the specified

bias point with VGS = 2 V and VDS = 28 V being the drain current measured in 10 second intervals.

Unfortunately, there was no thermometer available that would make the extraction of the thermal

coefficient of the device possible.

Two trials were made being visible that, excluding the first measurements, the current in-

creased roughly 0.01 A for each 10 seconds that passed. In the second trial (orange line), the

current increases initially quicker and stays larger than the first trial, presumably because the de-

vice was not completely cool.

In order to obtain a steady state regime with no significant drain current, active heat dissipation

was added to the system in the form of an external fan. That had good results stopping the current

increase at 1.23 A for the given bias conditions. Furthermore, the test was left running for 10 more

minutes and no increase in the current was noticed, reaching a steady state regime.

The temperature feeling to touch of the system followed the current consumption tendency,

being increasingly warmer in the first two sets of measurements and feeling approximately the

same when active cooling was used, proving the proposed theory.

This way, to more accurately compare the performance results of the device with the simula-

tion, one should use the quiescent current instead of the gate voltage, removing the temperature

effect, which is beneficial since the device model does not have thermal influence in its behavior.

The available power sources had no fine adjustment, meaning that one could easily overshoot

the gate voltage into an unstable regime. To solve this problem, a resistive divider with a multi turn

potentiometer was implemented to more easily adjust the gate voltage, facilitating the sweeping


Figure 4.6: Stress test of current consumption, being blue and orange the first and second trialsrespectively without active cooling along with yellow the last trial with active cooling

process. The circuit was implemented with 10.44 V at his terminals, being capable of providing

an output from 1.3 V to 2 V.

Figure 4.7: Implemented resistive divider on protoboard

4.3 Small signal measurements

Once it was verified that the consumption of the device was within the expected levels, one

could advance for the next step, measuring the S parameters of the device.

The S parameters were measured using active cooling and locking the device operation point

at 1.23 A, as discussed earlier. To protect the measuring device, an additional 10 dB attenuator

was added to the output port, as one can see in figure 4.8.

The first VNA used was malfunctioning, adding an ondulatory behavior to what should be the

usual device measurements, as one can see in the small signal gain graphic presented in figure 4.9.

4.3 Small signal measurements 83

Figure 4.8: Small signal measurement setup, with the VNA (A), PA (B), attenuator (C), powersupply for the drain bias network (D), power supply for the resistive divider (E) and resistivedivider (F)

Figure 4.9: S21 Measured at malfunction VNA with nominal bias conditions

The second Vector Network Analyzer used produced promising results for the S11 and S21

parameters, however, it presented high measurement noise to the S22 and S12 parameters.

This behavior was investigated probing the VNAs with a Spectrum analyzer. The conclusion

reached was that port 2 of the device was seriously damaged, having a 30 dB difference when

compared to the first port, meaning that measurements where a stimulus signal from port 2 was

required, like S22 and S12, had major noise issues.

To bypass this problem, the amplifier was measured in reverse and the S11 and S21 of both

configurations were combined, obtaining an accurate representation of the device’s behavior. Be-

fore each measurement the frequency range was defined, as well as the power level, followed by a

Through, Open, Short, Match (TOSM), also known as SOLT, that would put the measuring point

at the device’s terminals, removing the effects of the connecting cables and adapters.

Analyzing the results in figure 4.11, a narrowing in the amplified band is notorious when


Figure 4.10: S Parameters measurement with nominal bias conditions

Figure 4.11: S Parameters measured at right and simulated at left with nominal bias conditions

comparing the S21 parameters, being the transconductance gain particularly affected in the middle

operation frequency band. The reflection coefficients of both the source and load have similar

values to the expected ones. The main difference is the absence of the S11 strong resonating

frequency, that would decrease the reflected energy of the input port, and a small peak in the

S22 parameter around 2.4 GHz, where the device’s analysis must be done carefully as instabilities

can appear. The isolation factor S12 stays within the expected values always below -20 dB, not

presenting a problem stability wise.

4.4 Large signal measurements

With the device characterized in small signal, what is left to effectively measure a Power

Amplifier’ performance is its large signal operation.

To characterize the PA, a sweeping input signal should be applied while measuring the output

power and power consumption. With this, one has every variable needed to calculate the efficiency

4.4 Large signal measurements 85

and amplifier gain.

The available signal generator was monotone and had a limit power level of 16 dBm, meaning

that only one frequency could be analyzed at a time and a driver amplifier was required to bring

the 16 dBm up to the simulated 38 dBm of maximum efficiency input power point. The available

driver amplifier was known to have around 20 dB of gain with a maximum input power of 20 dBm,

and with a single 28 V feed point. With this in mind, the driver was characterized so that one could

calculate the power at its output that would feed the PA for the sweeping signal generator values.

To test the driver, an attenuator was additionally added to the output of the driver, in order to

downgrade the signal level to be read in the spectrum analyzer without having the risk of damag-

ing it. The first attenuator that was considered to be used was a chain of attenuators by Tektronix

capable of providing an attenuation of 51.3 dB at 2.4 GHz, as one can see in figure 4.12. How-

ever, these attenuators were disregarded since the first one in the chain was only rated for 5 W of

dissipation.

Figure 4.12: Tektronix attenuation chain S parameters

The alternative used was a RG-58 coaxial cable with a length of 50 m. To better understand the

behavior of the new "attenuator" the S parameters were extracted. Although the attenuation value

(S21) is not particularly constant along the measured frequencies, having more quick variations and

a bigger drift in the value as the frequency changes comparatively with the previous attenuator,

has the advantage of a much smaller S11, making the system much less predisposed to become

unstable, which is particularly important in the early stages of testing. The attenuation variations

can be overcome by considering the respective attenuation for the given operation frequency.

The attenuation used for the first large signal test was 56.3 dB according to the selected fre-

quency of 2.464 GHz. This value of frequency was selected as a starting point for the measure-

ments, since it was the frequency with the small signal peak gain.

The outcome of the driver test can be seen in figure 4.14 where, as expected, the output power

went up to 37 dBm, being close to what the PA requires in its most efficient operation point.

The driver was fed with 28 V with a power consumption measured of less than 3 A, so a single

power source was enough to feed it.


Figure 4.13: 50 m RG-58 coaxial cable S parameters

Figure 4.14: Driver Gain and PAE

However, the PA required much more current, so parallel associations of the available power

sources were needed, since each one could only deliver up to 3 A. With this configuration, three

double power supplies were connected in parallel, providing a theoretic maximum current of 18 A.

Considering a 50% efficient system with 200 W of output power, a DC power consumption of

400 W is needed. With a 28 V voltage, one is left with a current consumption around 14 A, being

the power supply association enough for the case. This was done by carefully adjusting the output

voltage of all power supplies with a common ground bus and three 28 V connections, that were

successively connected to the PA drain port, while analyzing the current drifts between them to

see if the supply system was balanced.

With the setup of figure 4.15, large signal measurements were done, extracting the spectrum

analyzer power values and current consumption for each input power, and sweeping the input

power from -20 dBm up to the limit of 16 dBm.

Ideally, an isolator would be used between the driver and the PA, preventing any power re-

flected, caused by a mismatch, to travel back to the driver damaging it. However, at the time of

testing there was none available, so a simple coaxial cable was used. The use of an isolator would

have the inconvenient of attenuating some of the driver’s power (that ideally would be higher to

fully characterize the PA), since it’s scattering matrix is not unitary making it a lossy component.


Figure 4.15: Large signal measurements setup, with the signal generator (A), Driver (B), PA (C),RG-58 coaxial attenuation cable (D), spectrum analyzer (E), external cooling (F), power supplyfor the driver (G1), power supply for the resistive divider (G2), and power supplies for PA’s drainbias network (G3-G8)

[4, Chapter 9].

Output Power (dBm)Output Power (dBm)

Dri

ver

Gai

n (

dB

)P

A G

ain

(d

B)

Ch

ain

Gai

n (

dB

)

0

5

10

15

20

25

30

35

40

0 5 10 15 20 25 30 35 4045

0 5 10 15 20 25 30 35 40 45

0

5

10

15

20

25

30

35

40

Dri

ver

PA

E (

%)

PA

PA

E (

%)

Ch

ain

PA

E (

%)

0 5 10 15 20 25 30 35 40 45

0

2

4

6

8

10

12

14

Figure 4.16: Large signal measurements results with 2 V of gate voltage at 2.464 GHz

The PA’s gain was calculated from the chain gain subtracting the measured driver gain. It was

assumed that the driver amplified the same as in the previous trial and the input power of the PA

was the signal generator power plus the driver gain measured at that input power.

Remembering figure 3.26, one can see that the gain did not suffer too much, with a peak gain

value of 16 dB compared with the 18 dB from the simulated layout. Besides that, the implemented

PA was compressing at much lower power compared to the simulation, reaching only 42 dBm

instead of the minimal objective of 53 dBm.

The PAE was brutally hit in the implemented circuit reaching only a peak value of 12% at the

measured frequency. Measurements at surrounding frequencies revealed similar results with an

output power of 44.2 dBm. The PA contributed with 6.1 dB of gain while having a peak efficiency

of only 14.2% operating at 2.545 GHz. A suspicion from the author that could justify these poor


results is a malfunctioning transistor. It could have been damaged in the DC tests before the

resistive divider was built, where an overdrive of the gate voltage set the transistor in a momentary

unstable regime, or from a thermal shock during the soldering process.

Another cause is a common problem with the LDMOS technology (an ESD can create latch

up phenomenon effectively damaging the transistor), a problem so critical that various techniques

to tackle it have been investigated, being some examples available in [71] and [72]. This issu also

crippled the testing process in another way, as it is believed that it was responsible for damaging the

transistor (MHT1008NT1 [73]) of the first tested driver (figure 4.17), which was also a LDMOS

device.

Figure 4.17: First driver tested

Fortunately, a replacement for the Ampleon’s device arrived just in time for the tests to be re-

peated, since the previous design was pretty far from the thesis’ objective. To replace the transistor

extra care was taken when handling the replacement, being used a grounding bracelet to prevent

any ESD, and performing the soldering in small intervals to not let the transistor heat up too much.

Periodic probing was done with an ohmmeter to check if a high resistive path was maintained be-

tween every terminal, which was the device’s initial behavior, tested just after unpacking.

An initial test of the device’s DC consumption with 50 Ω loads revealed that the new PA had

become more efficient with a current consumption much more similar to the simulated one, as

one can see in figure 4.18. With the lower current consumption the device heated up a lot less,

stabilizing at 0.59 V without active cooling after 5 minutes.

The S parameters were extracted again with the current consumption, which can be see in

figure 4.19. The results did not differ too much from the ones in figure 4.11. In the new circuit

the transconductance gain stays relatively constant in a larger bandwidth, compared with the in-

dentation of the S21 around 2.4 GHz.The S12 was also slightly changed but still below the -20 dB

mark.

With the S parameters the first testing frequency chosen was 2.4 GHz, since at this frequency

the PA’s S11 is minimal whilst the S22 is relatively low. This has particular importance because

the test was done without an isolator, which would have been a preventive approach. The analysis

of the S22 value along the frequencies, although also critical for stability, is less important in this

case due to the low input reflection of the cable/attenuator.


Figure 4.18: DC IV comparison between simulation and measured with new transistor measuredat 2 V to 1.6 V with steps of 0.1 V

Figure 4.19: S Parameters measurement with nominal bias conditions using the new transistor

An initial measurement of the output power for 0 dBm, 10 dBm and 15dBm was made at

2.4 GHz and its neighbouring frequencies, resulting in a maximum output power of 50 dBm at

2.35 GHz. Follow up tests would be required to detail the PA’s, driver’s and chain’s PAE and gain,

while measuring the consumed current. However, one wanted to test the maximum input power at

the most promising frequency output power wise. When 16 dBm of input power were applied to

the system, the output DC blocker capacitor heated up very quickly. The user reaction time to turn

off the system was enough for it to burn.

The high currents meant that the joule effect on the ESR was too much for the capacitor to

handle. To address this question, two replacements of 6.8 pF (since they were the available ones

with resonance frequency near the operation frequency) were installed in parallel, creating two

paths for the current to flow, effectively cutting in half the ESR, without having too much effect

on the equivalent impedance since near 2.4 GHz the capacitors’ impedance is very close to zero.

With the capacitor replacement the DC consumption was the same as previously, so the S

parameters were measured to confirm the circuit’s behavior was maintained. The results, shown


Figure 4.20: Output power measurements versus frequency for 0 dBm (orange), 10 dBm (blue),and 15 dBm (red) of input power

in figure 4.21 reveal that changing the capacitor essentially had no effect.

Figure 4.21: S Parameters measurement with nominal bias conditions using the 2 DC block ca-pacitors at the output

Input power sweeps were done initially for 2.4 GHz and later for 2.35 GHz, revealing the

results of figure 4.22. The choice of the second frequency value was based in the performance

versus frequency tests presented in figure 4.23, at which the output power was maximum with a

50.9 dBm value.

Analyzing figures 4.22a to 4.22d, one can say that the driver contributed a lot for the gain of

the chain being essentially constant for the measured input powers. Furthermore, some signs of

the PA’s gain compression can be seen around 12 dBm of input power for 2.4 GHz, starting the

compression at 15 dBm when a 2.35 GHz signal is used. The mentioned values of input power are

relative to the system, in reality the input power of the PA at the compression points are the stated

values plus the driver gain. For instance, the PA at 2.4 GHz starts compressing at 37 dBm.

Concerning figures 4.22e and 4.22f, one can say that the system is most efficient at 2.35 GHz,


(a) (b)

(c) (d)

(e) (f)

Figure 4.22: Device’s performance curves (with a sweeping input power from -20 dBm to 15dBm) for 2.4 GHz at the left (a, c, e) and 2.35 GHz at the right (b, d, f), being the yellow tracesrelative to the chain, the blue traces relative to the Driver, and red relative to the PA

and it is notorious that the Power Amplifier’s PAE is the dominant factor in the global PAE, since

it is this stage that contributes the most for the total dissipation of the system. To analyze the

functioning of the system in the neighbouring bandwidth, sweeps in frequency were done for 13

dBm, 15 dBm and 16 dBm of input power, which can be seen in figure 4.23. Additionally, the

input power was fixed at 15 dBm (point where the system presented the peak PAE and peak output

power) for characterization of the driver, measuring its gain for each frequency and its efficiency.

This allowed to inspect the contribution of each part to the system’s global performance.

Figures 4.23a, 4.23c and 4.23e show that the gain/output power do not vary too much with the

selected values of input power, being required more dispersed values of input power to understand

its impact. The PAE of the chain was affected by it, revealing a peak value of 40% at 2.35 GHz in

the blue curve (15 dBm).

The graphics on the right column of figure 4.23 manifest that the driver amplifier was respon-

sible for most of the gain, while not having the best efficiency. The 50.9 dbm of output power


(a) (b)

(c) (d)

(e) (f)

Figure 4.23: Performance curves (with a sweeping frequency from 2.25 GHz to 2.65 GHz ) of thechain at the left (a, c, e) with 13 dBm (orange), 15 dBm (blue) and 16 dBm (red) of input power,as well as the system components’ performance at the right (b, d, f) for 15 dBm of input power,being the yellow traces relative to the complete chain, the blue traces relative to the driver, and redrelative to the PA

at 2.35 GHz resulted from a peak in the driver’s gain at that frequency combined with a decent

gain of the PA, and the 40% peak efficiency of the system at this frequency followed the 45%

peak efficiency of the PA. One can also state that the large signal gain resembles the simulated

transconductance gain of around 10 dB in a considerably large bandwidth having a small reduction

in the practical case at 2.5 GHz. Even with the new transistor the best measured result of 50.9 dBm

was short from the 53 dBm objective while having a PAE of around 45%. Comparing it with the

state of the art amplifiers presented in table 2.1, one can conclude that improvements to the current

implementation should be done. In fact, if the practical results were similar to the simulated ones,

the amplifier would have a competing performance with a PAE of 53% and an output power of

200 W.

The great discrepancies are most likely due to practical implementation problems, like the


irregularities in the conductor caused by irregular soldering, primarily in the regions where the

layout length was normalized with copper tape instead of using the chicken dots.

During testing, it was shown that if enough external cooling could be applied, the current con-

sumption would remain constant in the quiescent point. In a large signal regime shorter tests were

performed, since the dissipation is larger, meaning that the most likely operation regime would be

pulsed, but improving the dissipation method one could try to go for continuous wave operation

if needed. Anyway, to fully test the system’s performance in a non continuous operation, a pulsed

signal with a relatively low duty cycle should be used, since the moon bouncing application for

this amplifier would most likely be operated in a pulsed mode.

Chapter 5

Conclusions

In this chapter, an overview of the work done is made, focusing on the fulfilment of the initial

goals, the difficulties encountered in the process and the future tasks that needed to be completed

to better understand and solve the problem. Additionally, some final remarks are made.

5.1 Objectives accomplishment

Remembering the main goal of this thesis (design, simulation, manufacturing, and testing of a

high power amplifier (greater or equal than 200 W) capable of operating in S or L band), one can

say that the objective was not fulfilled being the maximum output power measured of 50.6 dBm at

2.35 GHz.

Due to time restrictions, the design of the driver was not possible to be accomplished either. A

good starting point would be to use the recommended driver device (BLM2425M9S20) mentioned

in the recommended lineup page for the BLP2425M10S250P [74]. The personal objective of

implementing the developed amplifier in a practical moon bouncing application was not possible,

since this would require the work of other colleagues, everyone with their respective part on the

puzzle. In the future, a collective effort is required to be implemented.

5.2 Difficulties encountered

During the development of this thesis several difficulties were encountered that slowed signif-

icantly the author’s progress. One of them being long printing and delivery times of the PCBs,

which was solved by having a flexible design, creating tuning spots if necessary.

Related to the last topic is the delayed shipping times of the components that proved to be a

major inconvenient, deferring the implementation and respective tests. This was worsened by the

fact that when the replacement transistor was needed it arrived just a couple of days before the

document’s delivery date. Only one piece was initially ordered, due to it being the most expensive

part of the project. This caused last minute testing and no opportunity to take advantage of the

tunable approach of the layout.

94

5.3 Future work 95

The malfunctioning of the available measuring devices was also another situation that injured

the workflow. Namely, the ondulatory response measured in the first VNA, as well as the volt-

age display of the power supply, initially used to bias the gate that was wrongly measuring the

outputted voltage, which may have helped in the damaging of the transistor.

The initial ADS workspace and circuits management was also challenging, being overcome

with a hierarchical approach using folders and sub networks.

5.3 Future work

Since the main objective of this thesis was not fully accomplished, the top priority for the

future tasks would be to tune the current layout for the minimal output power and the best possible

efficiency.

After an acceptable performance is obtained, a study of the device’s non linearity must be

made, mainly measuring AM-PM distortion following the measuring technique mentioned in [31,

Chapter 6].

To characterize the different parts of the circuit, like the OMN, small portions of the circuit

could have been printed to be characterized individually. With this, one could have simulated the

layout with the parts from which the S parameters were measured and compare that behavior to

the ideal one, understanding how each part was affecting the global performance, as done in [25].

Furthermore, the study of small structures like a simple 50 Ω line, or an open stub, would help to

characterize the substrate’s behavior and conclude if any adjustments in the parameters from the

manufacturer’s model were needed to be made.

Another important task would be to better understand the relation between schematic based

simulations and layout based ones. After the first design trial with only schematic, the author opted

for a conservative use of it. More time should have been spent in understanding the conditions

where the schematic model is valid, facilitating the development process instead of avoiding it.

This led to a great discrepancy in the results when a layout to schematic conversion was done

before the Monte Carlo Analysis.

Another good point would be to extract a non linear device model of the transistor, being nec-

essary a large number of DC IV measurements, as well as large and small signal ones. This would

allow one to include the temperature influence that was not possible to test with the manufacturer’s

device model.

Assuming that the same active device would be used, different bias points could be tried in

order to improve the PA’s performance. The datasheet numbers could be followed, with a drain

voltage of 32 V that, at the time, was limited to 28 V due to power supply restrictions that turned

out to not be valid. A greater number of power supplies with lower current and voltages up to 32 V

were the only available solution.

One could also experiment with different amplifier classes, trying to implement a class with

higher efficiency, namely switching classes, for instance class E, which makes good constant en-

velope amplifier solutions, as mentioned in [31, Chapter 2].

Conclusions 96

5.4 Final Remarks

Although the main goal was unattained, using the experience gained from the simulations,

allowed to make some important conclusions regarding the RF PA design.

The design process involved a balancing of 3/4 main factors: efficiency, output power, gain

and linearity. The favoring of efficiency and output power led to choices that injured the gain and

linearity. While doing this balancing, one also needed to worry not to drive the system into an

unstable region.

Other major conclusion is that the schematic simulation does a poor representation of the

actual device’s performance, at least at the operated frequency, meaning that usage should be only

applied in conditions where it is valid.

The creation of tuning zones with dimensions smaller than the nominal size looks good on

paper, but should only be created if one is sure that the resizing will be an easy process with little

to no impact on the circuit, otherwise, the tuning benefit’s become irrelevant.

When dealing with high power circuits, the high currents that may appear must always be

considered, as well as their effects on the components. A mindful analysis of the output current

would quickly reveal that the ESR of a single capacitor would be enough to create a dangerous

situation.

One last appreciation is that when handling with LDMOS, extra precautions must be taken to

prevent ESD onto the component. Additionally, when the success of the work is dependent on a

single part, multiple units should be ordered if there is enough budget.

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