Design of 3.67 GHz RF Power Amplifier Presenters: Akshay Iyer, Logan Woodcock Advisers: Dr. K. Koh,...
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Transcript of Design of 3.67 GHz RF Power Amplifier Presenters: Akshay Iyer, Logan Woodcock Advisers: Dr. K. Koh,...
![Page 1: Design of 3.67 GHz RF Power Amplifier Presenters: Akshay Iyer, Logan Woodcock Advisers: Dr. K. Koh, Yahya Mortazavi.](https://reader035.fdocuments.in/reader035/viewer/2022062802/56649e905503460f94b94426/html5/thumbnails/1.jpg)
Design of 3.67 GHz RF Power Amplifier
Presenters: Akshay Iyer, Logan WoodcockAdvisers: Dr. K. Koh, Yahya Mortazavi
![Page 2: Design of 3.67 GHz RF Power Amplifier Presenters: Akshay Iyer, Logan Woodcock Advisers: Dr. K. Koh, Yahya Mortazavi.](https://reader035.fdocuments.in/reader035/viewer/2022062802/56649e905503460f94b94426/html5/thumbnails/2.jpg)
Cognitive Radios
● Software defined radio● Programmed to run by maximizing utility of
radio frequency spectrum
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Project Goal
● Design and simulate an RF power amplifier that operates between 2 and 4 GHz
● Use ADS software for design and simulation
PADigital Baseband Processor Digital to Analog Converter Modulator
Frequency Synthesizer (Oscillator)
Antenna(Tx)
Receiver(Rx)
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RF Power Amplifier (PA)
● Tx side: Increases the signal amplitude to make it more easily detected
Input Matching Network Output Matching
Network
RF In
RF Out
Drain Source Voltage
MOSFET Transistor
Gate Source Voltage
Source
Load
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Metal-Oxide Semiconductor Field-Effect Transistor● Creates a channel underneath the gate that
connects the source and drain terminals● Channel is created when a large enough
voltage is supplied to the gate
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Smith ChartsUsed for Impedance Matching (Max Power Transfer)
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Transmission Line Theory
Input Impedance
Special Cases: Open/Short Circuit Stubs
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Amplifier Classes
● A, AB, B, C, Fo Phase angles
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“Load Line”
“Q - Point” - DC Operating Point
DC+AC conditions:Vds=Vdd+Vac (time average of Vds must be Vdd)Vac=VoutId=Iddc+IdacIdac=-Iload=-Vout/RL
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Final Schematic● Consists of two bias networks, two
impedance matching networks, and a MOSFET designed by Freescale.
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Transistor and Substrate
● Freescale Model MRF8S26060H● Rogers Substrate
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● Class ABo utilizes harmonics
● VDS of 50 V, VGS of 2 V
Load Line / FET Curves Results
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Power Results
● Max Power Added Efficiency (PAE) of 88%
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Bias Networks
● Necessary to bias the transistor to desired level
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Load-Pull
● Shows impedance values specific to schematic
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Impedance Matching Networks
1. Shunt2. SeriesElectrical Length (degrees)
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Harmonic Balance Simulation
● Shows the effects of harmonics on output powero Increases efficiency
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Scattering - Parameters
● Voltage reflection coefficientso Shows reflected voltage (return loss)
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Further Steps in the Process
- Layout - EM simulation- Foundry
mwrf.com
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ReferencesG. Saggio, Principles of analog electronics, Edition of book, Boca Raton: Taylor & Francis Group, 2014, p. .B. Razavi, RF microelectronics, 2nd ed., New Delhi: Dorling Kindersley India, 2012, p. 767-847.