Design Methodologies by Rabaey

7/31/2019 Design Methodologies by Rabaey

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Digital Integrated Circuits2nd Design Methodologies

Digital Integrated

CircuitsA Design Perspective

Design

Methodologies

Jan M. Rabaey

Anantha ChandrakasanBorivoje Nikolic

December 10, 2002


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The Design Productivity Challenge

Source: sematech97

A growing gap between design complexity and design productivity1981

Logic Transistors per Chip (K) Produ

19831985198719891991199319951997199920012003200520072009

58%/Yr. compoundComplexity growth rate

21%/Yr. compoundProductivity growth rate

1981

10LogicTransistorsperChip(K)

Productivity(Trans./

Staff-Month)

100

1,000

10,000

100,000

1,000,000

10,000,000

1

XX

X XX

X

x

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

10

2.5m

.35m

.10m

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

2007

2009

Transistor/Staff Month

Logic Transistors/Chip


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A Simple Processor

MEMORY

DATAPATH

CONTROL

INPUT-OUTPUT

INPUT/OUT

PUT


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A System-on-a-Chip: Example

Courtesy: Philips


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Impact of Implementation Choices

EnergyEfficiency(in

MOPS/mW)

Flexibility

(or application scope)

0.1-1

1-10

10-100

100-1000

None Fully

flexible

Somewhat

flexible

Hardwiredcustom

Configu

rable/Parameterizable

Domain-specificprocessor

(e

.g.

DSP)

Embeddedmic

roprocessor


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Design Methodology

Design process traverses iteratively between three abstractions:

behavior, structure, and geometry

More and more automation for each of these steps


7/60 Digital Integrated Circuits2nd Design Methodologies

Implementation Choices

Custom

Standard CellsCompiled Cells Macro Cells

Cell-based

Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Semicustom

Digital Circuit Implementation Approaches



The Custom Approach

Intel 4004

Courtesy Intel



Transition to Automation and Regular Structures

Intel 4004 (71)

Intel 8080Intel 8085

Intel 8286 Intel 8486

Courtesy Intel



Cell-based Design (or standard cells)

Routing channel

requirements are

reduced by presenceof more interconnect

layers


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Standard Cell Example

[Brodersen92]


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Standard Cell The New Generation

Cell-structurehidden under

interconnect layers


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Standard Cell - Example

3-input NAND cell

(from ST Microelectronics):C = Load capacitance

T = input rise/fall time


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Automatic Cell Generation

Courtesy Acadabra

Initial transistorgeometries

Placedtransistors

Routedcell

Compactedcell

Finishedcell


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A Historical Perspective: the PLA

x0 x1 x2

ANDplane

x0x1

x2

Product terms

ORplane

f0 f1


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Two-Level Logic

Inverting format (NOR-NOR) more effective

Every logic function can beexpressed in sum-of-products

format (AND-OR)

minterm


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PLA Layout Exploiting Regularity

f0

f1

x0

x0

x1

x1x2

x2

Pull-up devices Pull-up devices

VDD GNDfAnd-Plane Or-Plane


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Breathing Some New Life in PLAs

River PLAs

A cascade of multiple-outputPLAs.

Adjacent PLAs are connected via river routing.

PRE-CHARGE

PRE-

CHARGE

PRE-CHARGE

PRE-CHARGE

BUFFER

BUFFER

BUFFER

BUFFER

PRE-CHARGE

PRE-CHARGE

BUFFER

BUFFER

PRE-CHARGE

PRE-

CHARGE

BUFFER

BUFFER

No placement and routing needed.

Output buffers and the input buffersof the next stage are shared.

Courtesy B. Brayton

y


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Experimental Results

Layout of C2670

Network of PLAs,

4 layers OTC

River PLA,

2 layers no additional routing

Standard cell,

2 layers channel routing

Standard cell,

3 layers OTC

0.2

0.6

1

1.4

0 2 4 6ar ea

delay

SC NPLA RPLA

Area:RPLAs (2 layers) 1.23

SCs (3 layers) - 1.00,

NPLAs (4 layers) 1.31

DelayRPLAs 1.04

SCs 1.00

NPLAs 1.09

Synthesis time: for RPLA , synthesis time equals design time;SCs and NPLAs still need P&R.

Also: RPLAs are regular and predictable


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MacroModules

25632 (or 8192 bit) SRAM

Generated by hard-macro module generator


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Soft MacroModules

Synopsys DesignCompiler


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Intellectual Property

A Protocol Processor for Wireless


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Semicustom Design Flow

HDL

Logic Synthesis

Floorplanning

Placement

Routing

Tape-out

Circuit Extraction

Pre-Layout

Simulation

Post-Layout

Simulation

Structural

Physical

BehavioralDesign Capture

DesignIteration


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The Design Closure Problem

Courtesy Synopsys

Iterative Removal of Timing Violations (white lines)


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Integrating Synthesis with

Physical Design

Physical Synthesis

RTL (Timing) Constraints

Place-and-Route

Optimization

Artwork

Netlist with

Place-and-Route Info

Macromodules

Fixed netlists


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Pre-diffused(Gate Arrays)

Pre-wired(FPGA's)

Array-based

Late-Binding Implementation


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Gate Array Sea-of-gates

rows of

cells

routing

channel

uncommitted

VDD

GND

polysilicon

metal

possiblecontact

In1 In2 In3 In4

Out

Uncommited

Cell

Committed

Cell

(4-input NOR)


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Sea-of-gate Primitive Cells

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation


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Example: Base Cell of Gate-Isolated GA

From Smith97


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Example: Flip-Flop in Gate-Isolated GA

From Smith97


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Sea-of-gates

Random Logic

Memory

Subsystem

LSI Logic LEA300K

(0.6 mm CMOS)

Courtesy LSI Logic


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The return of gate arrays?

metal-5 metal-6

Via-programmable cross-point

programmable via

Via programmable gate array

(VPGA)

[Pileggi02]

Exploits regularity of interconnect


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Prewired Arrays

Classification of prewired arrays (or field-

programmable devices): Based on Programming Technique

Fuse-based (program-once)

Non-volatile EPROM based

RAM based

Programmable Logic Style

Array-Based

Look-up Table

Programmable Interconnect Style Channel-routing

Mesh networks


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Fuse-Based FPGA

antifuse polysilicon ONO dielectric

n+

antifuse diffusion

2l

From Smith97

Open by default, closed by applying current pulse


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Array-Based Programmable Logic

PLA PROM PAL

I5 I4

O0

I3 I2 I1 I0

O1O2O3

Programmable AND array

ProgrammableOR array I5 I4

O0

I3 I2 I1 I0

O1O2O3

Programmable AND array

Fixed OR array

Indicates programmable connection

Indicates fixed connection

O0

I3 I2 I1 I0

O1O2O3

Fixed AND array

ProgrammableOR array


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Programming a PROM

f0

1 X2 X1 X0

f1NANA

: programmed node


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More Complex PAL

From Smith97

i inputs, j minterms/macrocell, k macrocells

2 i t


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2-input mux

as programmable logic block

FA 0

B

S

1

Configuration

A B S F=

0 0 0 0

0 X 1 X

0 Y 1 Y0 Y X XY

X 0 Y

Y 0 X

Y 1 X X1 Y

1 0 X

1 0 Y

1 1 1 1

XY

XY

X

Y


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Logic Cell of Actel Fuse-Based FPGA

A

B

SA Y

1

C

D

SB

1

S0

S1

1


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Look-up Table Based Logic Cell

Out

ln1 ln2

Mem

ory

In Out

00 00

01 1

10 1

11 0


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LUT-Based Logic Cell

Courtesy Xilinx

D4

C1....C4

xxxxxx

D3

D2

D1

F4

F3

F2

F1

Logicfunction

ofxxx

Logicfunction

ofxxx

Logicfunction

ofxxx

xx

xx

4

xxxxxx

xxxxxxxx

xxx

xxxx xxxx xxxx

HP

Bitscontrol

Bitscontrol

Multiplexer Controlledby Configuration Program

x

xx

x

xx

xxxxx

xxxx

x

xx

xxxx

xx

x

xx

xxx

xx

Xilinx 4000 Series

Figure must beupdated


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Array-Based Programmable Wiring

Input/output pinProgrammed interconnection

InterconnectPoint

Horizontal

tracks

Vertical tracks

Cell

M

Mesh based Interconnect Network


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Mesh-based Interconnect Network

Switch Box

Connect Box

Interconnect

Point

Courtesy Dehon and Wawrzyniek


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Transistor Implementation of Mesh



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Hierarchical Mesh Network

Use overlayed meshto support longer connections

Reduced fanout and reducedresistance



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EPLD Block Diagram

MacrocellPrimary inputs

Courtesy Altera


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Altera MAX

From Smith97


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Altera MAX Interconnect Architecture

LAB2

PIA

LAB1

LAB6

tPIA

tPIA

row channelcolumn channel

LAB

Courtesy Altera

Array-based(MAX 3000-7000)

Mesh-based(MAX 9000)

Field Programmable Gate Arrays


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Field-Programmable Gate Arrays

Fuse-based

I/O Buffers

Program/Test/Diagnostics

I/O Buffers

I/O

Buffers

I/O

Buffers

Vertical routes

Rows of logic modules

Routing channels

Standard-cell likefloorplan


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Xilinx 4000 Interconnect Architecture

2

12

8

4

3

2

3

CLB

8 4 8 4

Quad

Single

Double

Long

DirectConnect

Direct

ConnectQuad Long Global

ClockLong Double Single Global

ClockCarry

Chain

Long

12 4 4

Courtesy Xilinx

RAM based FPGA


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RAM-based FPGA

Xilinx XC4000ex

Courtesy Xilinx


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A Low-Energy FPGA (UC Berkeley)

Array Size: 8x8 (2 x 4

LUT)

Power Supply: 1.5V &

0.8V

Configuration: Mapped as

RAM

Toggle Frequency:

125MHz

Area: 3mm x 3mm


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Larger Granularity FPGAs

1-mm 2-metalCMOS tech

1.2 x 1.2 mm2

600k transistors

208-pin PGA

fclock = 50 MHz

Pav = 3.6 W @ 5V

Basic Module: Datapath

PADDI-2 (UC Berkeley)

Design at a crossroad


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Design at a crossroad

System-on-a-Chip

RAM

500 k Gates FPGA

+ 1 Gbit DRAM

Preprocessing

Multi-

Spectral

Imager

C

system

+2 Gbit

DRAMRecog-

nition

A

nalog

64 SIMD Processor

Array + SRAM

Image Conditioning100 GOPS

Embedded applications

where cost,performance,

and energy are the realissues!

DSP and control intensive

Mixed-mode

Combines programmableand application-specific

modules

Software plays crucial role

Addressing the Design Complexity Issue


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Addressing the Design Complexity Issue

Architecture Reuse

Reuse comes in generations

Generation Reuse element Status

1st Standard cells Well established

2nd IP blocks Being introduced

3rd Architecture Emerging

4th IC Early research

Source: Theo Claasen (Philips)DAC 00

A hit t R U


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Architecture ReUse

Silicon System Platform Flexible architecture for hardware and software

Specific (programmable) components

Network architecture

Software modules

Rules and guidelines for design of HW and SW

Has been successful in PCs

Dominance of a few players who specify and control architecture

Application-domain specific (difference in constraints)

Speed (compute power)

Dissipation

Costs

Real / non-real time data

Platform Based Design


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Platform-Based Design

A platform is a restriction on the space of possible implementationchoices, providing a well-defined abstraction of the underlyingtechnology for the application developer

New platforms will be defined at the architecture-micro-architectureboundary

They will be component-based, and will provide a range of choices

from structured-custom to fully programmable implementations Key to such approaches is the representation of communication in

the platform model

Only the consumer gets freedom of choice;

designers need freedomfromchoice

(Orfali, et al, 1996, p.522)

Source:R.Newton


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Berkeley Pleiades Processor

0.25um 6-level metal CMOS

5.2mm x 6.7mm

1.2 Million transistors

40 MHz at 1V

2 extra supplies: 0.4V, 1.5V

1.5~2 mW power dissipation

Interface

Reconfigurable

Data-path

FPGA

ARM8 Core

H t P bl Pl tf


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Heterogeneous Programmable Platforms

Xilinx Vertex-II Pro

Courtesy Xilinx

High-speed I/O

Embedded PowerPc

Embedded memories

Hardwired multipliers

FPGA Fabric

S


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Summary

Digital CMOS Design is kicking and healthy Some major challenges down the road

caused by Deep Sub-micron Super GHz design

Power consumption!!!! Reliability making it work

Some new circuit solutions are bound to emerge

Who can afford design in the years to come?

Some major design methodology change inthe making!

Design Methodologies by Rabaey

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