DESIGN GUIDE Carrier Board -...

1.00-03072017-095000

DESIGN GUIDE

Carrier Board for QSM-8Q60 Qseven™ ARM module

Copyright

Copyright © 2017 VIA Technologies Incorporated. All rights reserved.

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Technologies assumes no responsibility for the use or misuse of the information (including use or connection of extra

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information and product specifications within this document are subject to change at any time, without notice and without obligation

to notify any person of such change.

VIA Technologies, Inc. reserves the right the make changes to the products described in this manual at any time without prior notice.

Regulatory Compliance

FCC-A Radio Frequency Interference Statement This equipment has been tested and found to comply with the limits for a class A digital device, pursuant to part 15 of the FCC rules.

These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a

commercial environment. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in

accordance with the instruction manual, may cause harmful interference to radio communications. Operation of this equipment in a

residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his

personal expense.

Notice 1 The changes or modifications not expressly approved by the party responsible for compliance could void the user's authority to

operate the equipment.

Notice 2 Shielded interface cables and A.C. power cord, if any, must be used in order to comply with the emission limits.

Notice 3

The product described in this document is designed for general use, VIA Technologies assumes no responsibility for the conflicts or

damages arising from incompatibility of the product. Check compatibility issue with your local sales representatives before placing

an order.

Carrier Board Design Guide for QSM-8Q60

iii

Revision History

Revision Date Description

1.00 03/07/2017 Initial release


iv

Table of Contents

1. Introduction ................................................................................................................................... 1

1.1. Document Overview ......................................................................................................................................... 1

1.2. Acronyms and Definitions ............................................................................................................................... 2

1.3. Illustrations and Schematics ............................................................................................................................ 3

2. General Carrier Board Recommendations ............................................................................... 4

2.1. PCB Stackup Example ....................................................................................................................................... 4

2.1.1. Microstrip Versus Stripline Designs ....................................................................................................... 4

2.2. General Layout and Routing Guidelines ...................................................................................................... 6

2.2.1. Routing Styles and Topology .................................................................................................................. 6

2.2.2. General Trace Attribute Recommendations ........................................................................................ 7

2.2.3. General Clock Routing Considerations ................................................................................................. 7

3. Qseven Specification Overview................................................................................................. 9

3.1. Qseven Module Placement ............................................................................................................................. 9

3.2. Qseven Mechanical Characteristics ............................................................................................................... 9

3.3. QSM-8Q60 Module and Carrier Board Dimensions ............................................................................... 10

3.4. MXM Connector ............................................................................................................................................. 11

3.4.1. MXM Connector Dimensions ................................................................................................................ 11

3.4.2. MXM Connector Footprint .................................................................................................................... 12

3.4.3. QSM-8Q60 Module and MXM Connector Footprint...................................................................... 12

3.5. MXM Connector Pinouts ............................................................................................................................... 13

4. Layout and Routing Recommendations .................................................................................. 17

4.1. PCI Express Interface ..................................................................................................................................... 17

4.1.1. MiniPCIe Slot ............................................................................................................................................ 17

4.1.2. PCI Express Layout and Routing Recommendations ....................................................................... 19

4.1.3. PCI Express Reference Schematics ...................................................................................................... 20

4.2. Ethernet Interface ........................................................................................................................................... 21

4.2.1. Ethernet Interface Topology ................................................................................................................. 22

4.2.2. Gigabit Ethernet Layout and Routing Recommendations ............................................................... 23

4.2.3. Gigabit Ethernet Reference Schematics ............................................................................................. 24

4.3. USB Interface ................................................................................................................................................... 25

4.3.1. USB Layout and Routing Recommendations ..................................................................................... 25

4.3.2. USB Reference Schematics .................................................................................................................... 28

4.4. LVDS Interface ................................................................................................................................................. 29

4.4.1. LVDS Layout and Routing Recommendations ................................................................................... 30

4.4.2. LVDS Reference Schematics ................................................................................................................. 32

4.5. HDMI Interface ................................................................................................................................................ 33

4.5.1. HDMI Layout and Routing Recommendations .................................................................................. 34

4.5.2. HDMI Reference Schematics ................................................................................................................. 35

4.6. Audio Interface ............................................................................................................................................... 36

4.6.1. Audio Layout and Routing Recommendations ................................................................................. 36

4.6.2. Audio Reference Schematics ................................................................................................................ 37

Appendix A. Carrier Board Reference Schematics ...................................................................... 38


v

List of Figures

Figure 1: Conventions pertaining to schematics ............................................................................................................3

Figure 2: Six-layer microstrip PCB stackup example ....................................................................................................4

Figure 3: Six-layer stripline PCB stackup example .......................................................................................................4

Figure 4: Point-to-point and multi-drop examples ......................................................................................................6

Figure 5: Daisy-chain example ..........................................................................................................................................6

Figure 6: Alternate multi-drop example .........................................................................................................................6

Figure 7: Suggested clock trace spacing .........................................................................................................................7

Figure 8: Clock trace layout in relation to the ground plane ....................................................................................8

Figure 9: Series termination for multiple clock loads .................................................................................................8

Figure 10: Qseven module placement on carrier board PCB ....................................................................................9

Figure 11: Carrier board with Qseven module installed ............................................................................................9

Figure 12: Qseven module and carrier board height distribution ............................................................................9

Figure 13: Dimensions of the QSM-8Q60 module (top view) ............................................................................... 10

Figure 14: Dimensions of the carrier board (top view) ............................................................................................ 10

Figure 15: Dimensions of the MXM connector (top view) ...................................................................................... 11

Figure 16: Dimensions of the MXM connector (side view) ..................................................................................... 11

Figure 17: Carrier board PCB footprint for the MXM connector ............................................................................ 12

Figure 18: PCB footprint for Qseven module inserted in the MXM connector on the carrier board ............ 12

Figure 19: MXM connector schematics ........................................................................................................................ 16

Figure 20: MiniPCIe card and slot diagram .................................................................................................................. 18

Figure 21: MiniPCI Express interface topology example ......................................................................................... 19

Figure 22: PCI Express trace spacing diagram ............................................................................................................ 19

Figure 23: MiniPCIe slot reference circuitry ................................................................................................................ 20

Figure 24: Gigabit Ethernet layout recommendations (integrated magnetic module) ..................................... 22

Figure 25: Gigabit Ethernet reference circuitry ........................................................................................................... 24

Figure 26: USB differential signal layout recommendations ................................................................................... 25

Figure 27: USB differential signal routing example ................................................................................................... 26

Figure 28: USB 2.0 trace spacing diagram ................................................................................................................... 26

Figure 29: USB host reference circuitry ........................................................................................................................ 28

Figure 30: USB client reference circuitry...................................................................................................................... 28

Figure 31: LVDS panel interface implementation ...................................................................................................... 30

Figure 32: LVDS connector example ............................................................................................................................ 32

Figure 33: LVDS panel power reference circuitry ...................................................................................................... 32

Figure 34: LVDS backlight reference circuitry ............................................................................................................. 32

Figure 35: HDMI interface connector diagram ........................................................................................................... 33

Figure 36: HDMI interface reference circuitry ............................................................................................................. 35

Figure 37: Onboard I2S audio codec implementation example ............................................................................ 36

Figure 38: I2S Audio Codec implementation example ............................................................................................. 37


vi

List of Tables

Table 1: Acronyms and definitions ..................................................................................................................................2

Table 2: General six-layer microstrip PCB stackup ......................................................................................................5

Table 3: PCB stack-up detail .............................................................................................................................................5

Table 4: Recommended trace width and spacing ........................................................................................................7

Table 5: MXM connector sample .................................................................................................................................. 11

Table 6: MXM connector pinout ................................................................................................................................... 15

Table 7: PCI Express signal group and definition ...................................................................................................... 17

Table 8: MiniPCIe slot pinout definition ...................................................................................................................... 18

Table 9: PCI Express interface routing guidelines ..................................................................................................... 20

Table 10: PCI Express interface layout guidelines .................................................................................................... 20

Table 11: PCI Express interface trace properties ....................................................................................................... 20

Table 12: Ethernet signal definition .............................................................................................................................. 21

Table 13: Gigabit Ethernet interface routing guidelines .......................................................................................... 23

Table 14: Gigabit Ethernet interface layout guidelines ............................................................................................ 23

Table 15: Gigabit Ethernet interface trace properties .............................................................................................. 24

Table 16: USB signal definition ...................................................................................................................................... 25

Table 17: USB interface routing guidelines ................................................................................................................. 26

Table 18: USB interface layout guidelines .................................................................................................................. 27

Table 19: USB interface trace properties..................................................................................................................... 27

Table 20: LVDS signal definition ................................................................................................................................... 29

Table 21: LVDS interface routing guidelines .............................................................................................................. 30

Table 22: LVDS interface layout guidelines ................................................................................................................ 31

Table 23: LVDS interface trace properties .................................................................................................................. 31

Table 24: HDMI interface signal definition ................................................................................................................. 33

Table 25: HDMI interface routing guidelines ............................................................................................................. 34

Table 26: HDMI interface layout guidelines ............................................................................................................... 34

Table 27: HDMI interface trace properties ................................................................................................................. 34

Table 28: Audio interface signal definition ................................................................................................................. 36

Table 29: Audio interface routing guidelines ............................................................................................................. 36

Table 30: Audio interface layout guidelines .............................................................................................................. 37

Table 31: Audio interface trace properties ................................................................................................................. 37


1

1. Introduction This document provides design guidelines to the developers of a custom Qseven compliant carrier board

that supports the features of VIA QSM-8Q60™ module. This document includes the layout and routing

guidelines for general board designs and major underlying interfaces such as PCI Express, Gigabit Ethernet,

USB, LVDS, HDMI and Audio. In addition, the document includes the mechanical information of the

ruggedized MXM connector that provides high speed interfaces between the carrier board and the

module.

Please note that this document is considered to be a reference guide only. This document is not intended

to be a specification. All information and examples listed below are considered to accurate as of the

publication date; however developers must be aware that this document is only a referencing guide.

1.1. Document Overview A brief description of each chapter is given below.

Chapter 1: Introduction Briefly introduces the structure of the design guide document.

Chapter 2: General Carrier Board Recommendations General design schemes and recommended layout rules are shown in this chapter.

Chapter 3: Qseven Specification Overview Detailed information about the MXM connector placement and dimensions are described.

Chapter 4: Layout and Routing Recommendations Detailed layout and routing guidelines for each major interface are described.

Appendix A: Carrier Board Reference Schematics Reference schematics of COMEDB2 evaluation carrier board.


2

1.2. Acronyms and Definitions Term Description

ASIC Application-Specific Integrated Circuit

EMI Electromagnetic Interference

GBE Gigabit Ethernet

HDMI High-Definition Multimedia Interface

IC Integrated Circuit

IEEE Institute of Electrical and Electronics Engineers

IO Input/Output

I2S Integrated Interchip Sound / Inter-IC Sound

LAN Local Area Network

LCD Liquid Crystal Display

LVDS Low-Voltage Differential Signaling

MiniPCIe Mini PCI Express

MXM Mobile PCI Express Module

NC Not Connected / No Connection

OTG On-The-Go

PCB Printed Circuit Board

PCIe Peripheral Component Interconnect Express

PCIe x1 PCI Express one lane

RJ-45 Registered Jack-45

USB Universal Serial Bus

Table 1: Acronyms and definitions


3

1.3. Illustrations and Schematics Illustrations and schematics depicted in this document may show the directional flow of signals.

Directional flow is indicated by the pointed ends of the arrow shapes. See Figure 1.

IC

input signal flow output signal flow

bidirectional signal flow

Figure 1: Conventions pertaining to schematics


4

2. General Carrier Board Recommendations This section contains general guidelines for the PCB stackup and the layout of traces. General guidelines

for routing style, topology, and trace attribute recommendations are also discussed.

2.1. PCB Stackup Example Figure 2 illustrates an example of a PCB with a six-layer stackup. The stackup consists of three signal layers

and three reference (power and ground) layers. The three signal layers are referred to as the component

layer, inner layer and solder layer. The example below also shows the PCB stackup in a microstrip design.

Microstrip stackup design

Solder layer

Ground layer

Power layer

Inner layer

Ground layer

Component layer

Reference layers

Signal layers

Figure 2: Six-layer microstrip PCB stackup example

2.1.1. Microstrip Versus Stripline Designs Carrier board designers can choose between two basic categories of PCB design: microstrip and stripline.

Microstrip designs have the outer signal layers exposed. Stripline designs have the outermost signal layers

shielded by reference layers.

Stripline stackup design

Ground layer

Solder layer

Power layer

Inner layer

Component layer

Ground layer

Reference layers

Signal layers

Figure 3: Six-layer stripline PCB stackup example

The choice of microstrip or stripline design depends on the application for which the carrier board is

being designed. If the carrier board is being designed for locations where sensitivity to EMI is an issue, a

stripline design is recommended for reducing EMI and noise coupling. For applications where the

tolerance for EMI levels is greater, a microstrip design is recommended to reduce costs. Due to the

inherent nature of stripline PCB stacks, broad-side coupling is possible.


5

Layer Description Thickness Value Spacing (mil)

Component Layer 0.5 oz. Copper + Planting

~62 mils

Prepeg 2.4 ~3.5 mils thickness

Ground Layer 1.0 oz. Copper


Inner Layer ~52.3 mils thickness


Power Layer 1.0 oz. Copper


Ground Layer 1.0 oz. Copper

Prepeg 2.4 ~ 3.5 mils thickness

Solder Layer 0.5 oz. Copper + Planting

Table 2: General six-layer microstrip PCB stackup

Description Value Notes

Dielectric constant (Ɛr) of Prepeg 3.6 ~ 4.2 @ 1GHz

Board Impedance 55Ω ± 10% For all signal layers

Table 3: PCB stack-up detail

Notes:

1. It is not recommended to have any signal routings on either power layer or the ground layer. If a signal must

be routed on the power layer, then it should be routed as short as possible.

2. Signal routing on the ground layer is not allowed.

3. Lower trace impedance providing better signal quality is preferred over higher trace impedance for clock

signals.


6

2.2. General Layout and Routing Guidelines This section provides general layout rules and routing guidelines for designing carrier boards for QSM-

8Q60 module.

2.2.1. Routing Styles and Topology Topology is the physical connectivity of a net or a group of nets. There are two types of topologies for a

motherboard layout: point-to-point and multi-drop. An example of these topologies is shown in Figure 4.

ASIC

Multi-Drop

Point-to-Point

ASIC

or

Connector

ASIC

ASIC

or

Connector

Figure 4: Point-to-point and multi-drop examples

High-speed bus signals are sensitive to transmission line stubs, which can result in ringing on the rising

edge caused by the high impedance of the output buffer in the high state. In order to maintain better

signal quality, transmission stubs should be kept as short as possible (less than 1.5”). Therefore, daisy

chain style routing is strongly recommended for these signals. Figure 5 below shows an example of daisy

chain routing.

trace segment

ASICASIC

short stub

ASIC

or

Connector

ASIC

or

Connector

Figure 5: Daisy-chain example

If daisy chain routing is not allowed in some circumstances, different routings may be considered. An

alternative topology is shown in Figure 6. In this case, the branch point is somewhere between both ends.

It may be near the source or near the loads. Being close to the load side is best. The separated traces

should be equal in length.

equal lengthASIC

somewhere

in the middle

ASIC

or

Connector

ASIC

or

Connector

Figure 6: Alternate multi-drop example


7

2.2.2. General Trace Attribute Recommendations A 5 mils trace width and 10 mils spacing are generally advised for most signal traces on a carrier board

layout. To reduce trace inductance the minimum power trace width is recommended to be 30 mils.

As a quick reference, the overall recommended trace width and spacing for different trace types are listed

in Table 4, and the recommended trace width and spacing for each signal group is shown in Chapter 4.

Trace Type Trace Width (mil) Spacing (mil)

Regular Signal 5 or wider 10 or wider

Interface or Bus Reference Voltage Signal 20 or wider 20 or wider

Power 30 or wider 20 or wider

Table 4: Recommended trace width and spacing

General rules for minimizing crosstalk in high-speed bus designs are listed below:

• Maximize the distance between traces. Maintain 10 mils minimum spaces between traces

wherever possible.

• Maximize the distance (30 mils minimum) between two adjacent routing areas of different signal

groups wherever possible.

• Avoid parallelism between traces on adjacent layers.

• Select a board stack-up that minimizes coupling between adjacent traces.

2.2.3. General Clock Routing Considerations

Clock routing guidelines are listed below:

• The recommended clock trace width is 5 mils.

• The minimum space between one clock trace and adjacent clock traces is 20 mils. The minimum

space from one segment of a clock trace to other segments of the same clock trace is at least

two times of the clock width. That is, more space is needed from one clock trace to others or its

own trace to avoid signal coupling (see Figure 7).

• Clock traces should be parallel to their reference ground planes. That is, a clock trace should be

right beneath or on top of its reference ground plane (see Figure 8).

• Series terminations (damping resistors) are needed for all clock signals (typically 0 to 47 ohm Ω).

When two loads are driven by one clock signal, the series termination layout is shown in Figure 9.

When multiple loads (more than two) are applied, a clock buffer solution is preferred.

• Isolating clock synthesizer power and ground planes through ferrite beads or narrow channels

(typically 20 mils to 50 mils wide) is preferred.

• No clock traces on the internal layer if a six-layer board is used.

clock

segment

clock

ssi

cc c

20 mils

at least two times

of the width of the

clock segment

Figure 7: Suggested clock trace spacing


8

a ae

clock a

ar a

R

a ae

clock a

ar a

N ommended

Figure 8: Clock trace layout in relation to the ground plane

in equal length

clock source

damping resistors

in equal length

clock load

clock load

Figure 9: Series termination for multiple clock loads


9

3. Qseven Specification Overview The carrier board for VIA QSM-8Q60 module must follow the placement defined in the Qseven

specification.

3.1. Qseven Module Placement Figure 10 shows a depiction of the top view of 3.5” SBC form factor carrier board PCB with appropriate

amount of space reserved for the Qseven module (QSM-8Q60).

7!""

7!""

2#$""

1%""

1&#$""

&""

&#3$""

Carrier Board PCB

Figure 10: Qseven module placement on carrier board PCB

3.2. Qseven Mechanical Characteristics

Heatsink

M'M ()**+(,)-Carrier Board PCB

Qseven module (QSM-8Q60)

Hex spacer

Screw

Figure 11: Carrier board with Qseven module installed

./044

./544

644 89:;<=>?@ A;=: eB;<:C

D/044

E44

E44

Figure 12: Qseven module and carrier board height distribution


10

3.3. QSM-8Q60 Module and Carrier Board Dimensions The mechanical dimensions of the QSM-Q860module and reference carrier board (QSMDB2) are shown

below.

FGHH

FGHH

5mm IJKHH

LOJPHH

KQHH

SJIHH

FGHH

THH

52mm

IOJITHm

TJPIHH

LSJKKHm

SJLPHH

Figure 13: Dimensions of the QSM-8Q60 module (top view)

QSMDB2

UVWXUYZZ

Y[X\]mm

VZZ

U^\ZZ

VX_`ZZ

U]_ZZ

5mm

Figure 14: Dimensions of the carrier board (top view)


11

3.4. MXM Connector The MXM connector can handle high-speed signals and comprises of 230-pins to connect the QSM-8Q60

module.

Table 5 shows the specification of MXM connector with 7.8mm height.

Part Number Resulting height between

Qseven module and carrier board Height Vendor

AS0B326-S78N-7F 5mm 7.8mm Foxconn

Table 5: MXM connector sample

3.4.1. MXM Connector Dimensions

bdfgg

fhgg

fdfgg

hdjkgg

kdblgg

mno opd kkq

tqgg

mno opd h mnuvw

mno opd 2

fdfgg

hdhtgg

kdxkgg

fhgg

mno opd kxb

bdhfgg

Figure 15: Dimensions of the MXM connector (top view)

5mm

yz

| ~ Module

Figure 16: Dimensions of the MXM connector (side view)


12

3.4.2. MXM Connector Footprint

51mm

2

mm

Figure 17: Carrier board PCB footprint for the MXM connector

3.4.3. QSM-8Q60 Module and MXM Connector Footprint

Carrier Board PCB

Figure 18: PCB footprint for Qseven module inserted in the MXM connector on the carrier board


13

3.5. MXM Connector Pinouts The MXM connector is used for connecting the QSM-8Q60 module to the Qseven carrier board. The

MXM connector is consists of 230-pins. The pinout of the MXM connector is shown below.

Pin# Pin Name Signal Pin# Pin Name Signal

1 GND GND 2 GND GND

3 GBE_MDI3- TXRXM_D 4 GBE_MDI2- TXRXM_C

5 GBE_MDI3+ TXRXP_D 6 GBE_MDI2+ TXRXP_C

7 GBE_LINK100- NC 8 GBE_LINK1000- NC

9 GBE_MDI1- TXRXM_B 10 GBE_MDI0- TXRXM_A

11 GBE_MDI1+ TXRXP_B 12 GBE_MDI0+ TXRXP_A

13 GBE_LINK# LED2_LINK- 14 GBE_ACT# LED1_ACT-

15 GBE_CTREF NC 16 SUS_S5# GPIO_19_PLED

17 WAKE- NC 18 SUS_S3- USB_OTG_PWR_EN

19 SUS_STAT- NC 20 PWRBTN- NC

21 SLP_BTN- NC 22 LID_BTN- NC

23 GND GND 24 GND GND

25 GND GND 26 PWGIN NC

27 BATLOW- NC 28 RSTBTN# RESET_N

29 SATA0_TX+ SATA0_TX+ 30 SATA1_TX+ UART3_RX

31 SATA0_TX- SATA0_TX- 32 SATA1_TX- UART3_TX

33 SATA_ACT- SATA_ACT- 34 GND GND

35 SATA0_RX+ SATA0_RX+ 36 SATA1_RX+ UART3_-CTS

37 SATA0_RX- SATA0_RX- 38 SATA1_RX- UART3_-RTS


41 BIOS_DISABLE-

/BOOT_ALT-

NC 42 SDIO_CLK- SD1_CLK

43 SDIO_CD- SD1_CD- 44 SDIO_LED SD1_LED

45 SDIO_CMD SD1_CMD 46 SDIO_WP SD1_WP

47 SDIO_PWR- SD1_PWR- 48 SDIO_DATA1 SD1_DATA1

49 SDIO_DATA0 SD1_DATA0 50 SDIO_DATA3 SD1_DATA3



55 SDIO_DATA6 SD1_DATA6 56 RSVD NC


59 HDA_SYNC

/I2S_WS

AUD4_TXFS 60 SMB_CLK

/GP1_I2C_CLK

UART2_RX

61 HDA_RST#

/I2S_RST#

GPIO_0_CLKO 62 SMB_DAT

/GP1_I2C_DAT

UART2_TX

63 HDA_BITCLK

/I2S_CLK

AUD4_TXC 64 SMB_ALERT- NC

65 HDA_SDI

/I2S_SDI

AUD4_TXD 66 GP0_I2C_CLK I2C3_SCL

67 HDA_SDO

/I2S_SDO

AUD4_RXD 68 GP0_I2C_DAT I2C3_SDA

69 THRM- NC 70 WDTRIG- NC

71 THRMTRIP- NC 72 WDOUT WDOG_B


75 USB_P7-

/USB_SSTX0-

NC 76 USB_P6-/USB_SSRX0- NC

77 USB_P7-

/USB_SSTX0+

NC 78 USB_P6-/USB_SSRX0+ NC

79 USB_6_7_OC- NC 80 USB_4_5_OC# USB_4_OC


14

81 USB_P5-

/USB_SSTX1-

NC 82

USB_P4-/USB_SSRX1- USBD_T4-

83 USB_P5-

/USB_SSTX1+

NC 84

USB_P4-/USB_SSRX1+ USBD_T4+

85 USB_2_3_OC# USB_2_3_OC 86 USB_0_1_OC# USB_0_OTG_OC

87 USB_P3- USBD_T3- 88 USB_P2- USBD_T2-

89 USB_P3+ USBD_T3+ 90 USB_P2+ USBD_T2+

91 USB_CC NC 92 USB_ID USBD_OTG_ID

93 USB_P1- OTG_USBD_T1- 94 USB_P0- USBD_T0-

95 USB_P1+ OTG_USBD_T1+ 96 USB_P0+ USBD_T0+


99 eDP0_TX0+

/LVDS_A0+

LVDS0_TX0_P 100 eDP1_TX0+

/LVDS_B0+

LVDS1_TX0_P

101 eDP0_TX0-

/LVDS_A0-

LVDS0_TX0_N 102 eDP1_TX0-

/LVDS_B0-

LVDS1_TX0_N

103 eDP0_TX1+

/LVDS_A1+


/LVDS_B1+

LVDS1_TX1_P

105 eDP0_TX1-

/LVDS_A1-


/LVDS_B1-

LVDS1_TX1_N

107 eDP0_TX2+

/LVDS_A2+


/LVDS_B2+

LVDS1_TX2_P

109 eDP0_TX2-

/LVDS_A2-


/LVDS_B2-

LVDS1_TX2_N

111 LVDS_PPEN LVDS_PPEN 112 LVDS_BLEN LVDS_BLEN

113 eDP0_TX3+

/LVDS_A3+


/LVDS_B3+

LVDS1_TX3_P

115 eDP0_TX3-

/LVDS_A3-


/LVDS_B3-

LVDS1_TX3_N


119 eDP0_AUX+

/LVDS_A_CLK+

LVDS0_CLK_P 120 eDP1_AUX+

/LVDS_B_CLK+

LVDS1_CLK_P

121 eDP0_AUX-

/LVDS_A_CLK-

LVDS0_CLK_N 122 eDP1_AUX-

/LVDS_B_CLK-

LVDS1_CLK_N

123 LVDS_BLT_CTRL

/GP_PWM_OUT0

LVDS_PWM2 124 GP_1-Wire_Bus NC

125 GP2_I2C_DAT

/LVDS_DID_DAT

I2C1_SDA 126 eDP0_HPD#

/LVDS_BLC_DAT

USB_0_2_3_4_EN

127 GP2_I2C_CLK

/LVDS_DID_CLK

I2C1_SCL 128 eDP1_HPD#

/LVDS_BLC_CLK

HDMI_CEC_IN

129 CAN0_TX CAN_TX1 130 CAN0_RX CAN_RX1

131 DP_LANE3+

/TMDS_CLK+

HDMI_CLKP 132 RSVD(Differential) TP_2

133 DP_LANE3-

/TMDS_CLK-

HDMI_CLKM 134 RSVD(Differential) TP_3


137 DP_LANE1+

/TMDS_LANE1+

HDMI_D1P 138 DP_AUX+ NC

139 DP_LANE1-

/TMDS_LANE1-

HDMI_D1M 140 DP_AUX- NC


143 DP_LANE2+

/TMDS_LANE0+

HDMI_D0P 144 RSVD(Differential) NC

145 DP_LANE2-

/TMDS_LANE0-

HDMI_D0M 146 RSVD(Differential) NC



15

149 DP_LANE0+

/TMDS_LANE2+

HDMI_D2P 150 HDMI_CTRL_DAT I2C2_SDA

151 DP_LANE0-

/TMDS_LANE2-

HDMI_D2M 152 HDMI_CTRL_CLK I2C2_SCL

153 DP_HDMI_HPD# HDMI_HPD 154 RSVD GND

155 PCIE_CLK_REF+ PCIe_CREFCLKP 156 PCIE_WAKE# PCIE_WAKE_B

157 PCIE_CLK_REF- PCIe_CREFCLKM 158 PCIE_RST# PCIE_RST_B


161 PCIE3_TX+ NC 162 PCIE3_RX+ NC

163 PCIE3_TX- NC 164 PCIE3_RX- NC


167 PCIE2_TX+ NC 168 PCIE2_RX+ NC

169 PCIE2_TX- NC 170 PCIE2_RX- NC

171 UART0_TX UART1_TX 172 UART_RTS- UART1_-RTS

173 PCIE1_TX+ NC 174 PCIE1_RX+ CAN_TX2

175 PCIE1_TX- NC 176 PCIE1_RX- CAN_RX2

177 UART0_RX UART1_RX 178 UART0_CTS UART1_CTS

179 PCIE0_TX+ PCIe_CTXP 180 PCIE0_RX+ PCIe_CRXP

181 PCIE0_TX- PCIe_CTXM 182 PCIE0_RX- PCIe_CRXM


185 LPC_AD0/GPIO0 GPIO6_IO11 186 LPC_AD1/GPIO1 TP_6

187 LPC_AD2/GPIO2 GPIO_2 188 LPC_AD3/GPIO3 TP_7

189 LPC_CLK/GPIO4 GPIO6_IO14 190 LPC_FRAME#/GPIO5 TP_8

191 SERIRQ/GPIO6 GPIO_5 192 LPC_LDRQ#/GPIO7 TP_9

193 VCC_RTC VDD_RTC_IN 194 SPKR/GP_PWM_OUT2 NC

195 FAN_TACHOIN

/GP_TIMER_IN

NC 196 FAN_PWM

/GP_PWM_OUT1

PWM_OUT1


199 SPI_MOSI CSPI3_MOSI 200 SPI_CS0# CSPI3_CS0

201 SPI_MISO CSPI3_MISO 202 SPI_CS1# CSPI3_CS1

203 SPI_SCK CSPI3_CLK 204 MFG_NC4 NC

205 VCC_5V_SB NC 206 VCC_5V_SB NC

207 MFG_NC0 NC 208 MFG_NC2 NC

209 MFG_NC1 NC 210 MFG_NC3 NC

211 VCC 5VIN 212 VCC 5VIN










Table 6: MXM connector pinout


16

UART2

UART3

99G26-05060L :BUTTON CELL BIN-CR2450W-J-CT-2PI-SL-P V-W-001 3V,550mAh,-40 ~+125

REV 2

CAN 2

GPIO6_IO11

USB_4_OC

GPIO_2

VDD_RTC_IN

5VIN5VIN

3P3V

HDMI_HPD3

LVDS_BLEN 5LVDS_PPEN5

LVDS_PWM25

CSPI3_CLK4

CSPI3_MOSI4CSPI3_MISO4

CSPI3_CS0 4

RESET_N 7

AUD4_RXD10AUD4_TXD10AUD4_TXC10

AUD4_TXFS10

LED1_ACT- 6LED2_LINK-6

PCIE_RST_B 7PCIE_WAKE_B 7

PCIe_CREFCLKM7PCIe_CREFCLKP7

PCIe_CRXM 7PCIe_CRXP 7

PCIe_CTXM7PCIe_CTXP7

USB_2_3_OC9

OTG_USBD_T1-12OTG_USBD_T1+12

USB_OTG_ID 12

USBD_T0+ 15

USBD_T2+ 9USBD_T2- 9

USBD_T3+9USBD_T3-9


USBD_T0- 15

I2C3_SDA 5,7,8,10I2C3_SCL 5,7,8,10

UART1_RX8

UART1_TX8

UART3_TX 8UART3_RX 8

GPIO_19_PLED 7

GPIO_0_CLKO10

TXRXP_D6TXRXM_D6

TXRXP_B6TXRXM_B6

TXRXP_C 6TXRXM_C 6

TXRXP_A 6TXRXM_A 6

I2C1_SDA4,11,15I2C1_SCL4,11,15

HDMI_D2P3HDMI_D2M3

HDMI_D1P3HDMI_D1M3

HDMI_D0P3HDMI_D0M3

HDMI_CLKP3HDMI_CLKM3

I2C2_SDA 3I2C2_SCL 3

HDMI_CEC_IN 3

LVDS0_TX0_N5LVDS0_TX0_P5



LVDS1_CLK_N 5LVDS1_CLK_P 5

LVDS1_TX3_N 5LVDS1_TX3_P 5




USB_0_2_3_4_EN 9

UART2_RX 8

UART2_TX 8

LVDS0_CLK_N5LVDS0_CLK_P5


PWM_OUT1 5

GPIO6_IO1415

I2C1_SDA 4,11,15I2C1_SCL 4,11,15

CAN_RX2 18CAN_TX2 18

CAN_RX1 18CAN_TX118

R179 0

R81 0/X

C5010uF C53

0.1uF

R82 0/X

R6194.7K

TP_71

TP_51

R80 0

R620

4.7K

C1640.1uF

TP_111

R79 0

J3

85204-0200L

12

G1

G2

TP_11

C5410uF

TP_41

R87 0

C5147uF

C5747uF

TP_61

R69 0

R85 0

TP_91

R77 0

C520.1uF

R75 0

R78 0/X

TP_13 1

C550.1uF

R84 0

R71 0

TP_21

TP_31

R86 0

R76 0

C560.1uF

TP_81

R178 0

TP_101

R72 0

R83 0

Machenical KEY

J2

AS0B326-S78N-7F

GND1

GBE_MDI3-3

GBE_MDI3+5

GBE_LINK100-7

GBE_MDI1-9

GBE_MDI1+11

GBE_LINK#13

GBE_CTREF15

WAKE-17

SUS_STAT-19

SLP_BTN-21

GND23

GND25

BATLOW-27

SATA0_TX+29

SATA0_TX-31

SATA_ACT-33

SATA0_RX+35

SATA0_RX-37

GND39

BIOS_DISABLE-/BOOT_ALT-41

SDIO_CD-43

SDIO_CMD45

SDIO_PWR-47

SDIO_DATA049

SDIO_DATA251

SDIO_DATA453

SDIO_DATA655

GND57

HDA_SYNC/I2S_WS59

HDA_RST#/I2S_RST#61

HDA_BITCLK/I2S_CLK63

HDA_SDI/I2S_SDI65

HDA_SDO/I2S_SDO67

THRM-69

THRMTRIP-71

GND73

USB_P7-/USB_SSTX0-75

USB_P7+/USB_SSTX0+77

USB_6_7_OC-79



USB_2_3_OC#85

USB_P3-87

USB_P3+89

USB_CC91

USB_P1-93

USB_P1+95

GND97

eDP0_TX0+/LVDS_A0+99

eDP0_TX0-/LVDS_A0-101





LVDS_PPEN111



GND117

eDP0_AUX+/LVDS_A_CLK+119

eDP0_AUX-/LVDS_A_CLK-121

LVDS_BLT_CTRL/GP_PWM_OUT0123

GP2_I2C_DAT/LVDS_DID_DAT125

GP2_I2C_CLK/LVDS_DID_CLK127

CAN0_TX129

DP_LANE3+/TMDS_CLK+131

DP_LANE3-/TMDS_CLK-133

GND135

DP_LANE1+/TMDS_LANE1+137

DP_LANE1-/TMDS_LANE1-139

GND141



GND147



DP_HDMI_HPD#153

PCIE_CLK_REF+155

PCIE_CLK_REF-157

GND159

PCIE3_TX+161

PCIE3_TX-163

GND165

PCIE2_TX+167

PCIE2_TX-169

UART0_TX171

PCIE1_TX+173

PCIE1_TX-175

UART0_RX177

PCIE0_TX+179

PCIE0_TX-181

GND183

LPC_AD0/GPIO0185

LPC_AD2/GPIO2187

LPC_CLK/GPIO4189

SERIRQ/GPIO6191

VCC_RTC193

FAN_TACHOIN/GP_TIMER_IN195

GND197

SPI_MOSI199

SPI_MISO201

SPI_SCK203

VCC_5V_SB205

MFG_NC0207

MFG_NC1209

VCC211

VCC213

VCC215

VCC217

VCC219

VCC221

VCC223

VCC225

VCC227

VCC229

GND2

GBE_MDI2-4

GBE_MDI2+6

GBE_LINK1000-8

GBE_MDI0-10

GBE_MDI0+12

GBE_ACT#14

SUS_S5#16

SUS_S3-18

PWRBTN-20

LID_BTN-22

GND24

PWGIN26

RSTBTN#28

SATA1_TX+30

SATA1_TX-32

GND34

SATA1_RX+36

SATA1_RX-38

GND40

SDIO_CLK-42

SDIO_LED44

SDIO_WP46

SDIO_DAT148

SDIO_DAT350

SDIO_DAT552

SDIO_DAT754

RSVD56

GND58

SMB_CLK/GP1_I2C_CLK60

SMB_DAT/GP1_I2C_DAT62

SMB_ALERT-64

GP0_I2C_CLK66

GP0_I2C_DAT68

WDTRIG-70

WDOUT72

GND74

USB_P6-/USB_SSRX0-76

USB_P6+/USB_SSRX0+78

USB_4_5_OC#80



USB_0_1_OC#86

USB_P2-88

USB_P2+90

USB_ID92

USB_P0-94

USB_P0+96

GND98

eDP1_TX0+/LVDS_B0+100

eDP1_TX0-/LVDS_B0-102





LVDS_BLEN112



GND118

eDP1_AUX+/LVDS_B_CLK+120

eDP1_AUX-/LVDS_B_CLK-122

GP_1-Wire_Bus124

eDP0_HPD#/LVDS_BLC_DAT126

eDP1_HPD#/LVDS_BLC_CLK128

CAN0_RX130

RSVD(Differential)134

GND136

DP_AUX+138

DP_AUX-140

GND142



GND148

HDMI_CTRL_DAT150

HDMI_CTRL_CLK152

RSVD154

PCIE_WAKE#156

PCIE_RST#158

GND160

PCIE3_RX+162

PCIE3_RX-164

GND166

PCIE2_RX+168

PCIE2_RX-170

UART0_RTS-172

PCIE1_RX+174

PCIE1_RX-176

UART0_CTS-178

PCIE0_RX+180

PCIE0_RX-182

GND184

LPC_AD1/GPIO1186

LPC_AD3/GPIO3188

LPC_FRAME#/GPIO5190

LPC_LDRQ#/GPIO7192

SPKR/GP_PWM_OUT2194

FAN_PWM/GP_PWM_OUT1196

GND198

SPI_CS0#200

SPI_CS1#202

MFG_NC4204

VCC_5V_SB206

MFG_NC2208

MFG_NC3210

VCC212

VCC216

VCC218

VCC220

VCC222

VCC224

VCC226

VCC228

VCC230

VCC214


G1G1

G2G2

G3G3

G4G4

G5

G5

G6

G6

Figure 19: MXM connector schematics


17

4. Layout and Routing Recommendations The information presented in this chapter includes the signal descriptions, reference schematic examples,

topology examples, and detailed layout and routing guidelines for each bus interface. The information

provided is intended for designing the Qseven compliant carrier boards to support the features of QSM-

8Q60 module.

4.1. PCI Express Interface This section will guide the developer to create a robust PCI Express interface design in the Qseven carrier

board. However, the carrier board designer should do an appropriate analysis and simulation to verify that

the design fulfills PCI Express specification requirements.

The PCI Express is a serial differential low-voltage, point-to-point interface. A PCI Express consists of two

differential signal pairs (for transmit data pair and receive data pair), and one pair for reference clock. The

bandwidth of a PCI Express link can be increased by adding signal pairs to form multiple lanes between

two devices.

The QSM-8Q60 module can support one PCI Express x1 through miniPCIe slot.

Signal Name Pin # I/O Description

PCIE0_RX+ 180 IO Receive input differential pair, PCIe channel 0.

PCIE0_RX- 182

PCIE0_TX+ 179 IO Transmit output differential pair, PCIe channel 0.

PCIE0_TX- 181

PCIE_CLK_REF+ 155 IO PCIe reference clock for Lane 0.

PCIE_CLK_REF- 157

PCIE_WAKE# 156 IO PCIe wake event up signal: Sideband wake signal

asserted by components requesting wakeup.

PCIE_RST# 158 IO Reset signal for external devices.

Table 7: PCI Express signal group and definition

4.1.1. MiniPCIe Slot The miniPCIe slot consists of a single PCI Express x1.The miniPCIe slot is a 52-pin connector designed for

add-in PCI Express Mini Cards. Applying the miniPCIe slot on the carrier board will provide the ability to

insert different removable and upgradeable miniPCIe cards without the additional expenditure to redesign

the carrier board.

Pin Signal Description

1 PCIE_WAKE_B Request to return to full operation and respond to PCIe

2 MPCIE_3V3 Primary source voltage, 3.3V

3 NC No Connection/Reserved

4 GND Ground


6 DDR_1_5V Secondary source voltage, 1.5V


8 USIM_VCC Power source for User Identity Modules

9 GND Ground

10 USIM_DATA Data signal for User Identity Module

11 PCIe_CREFCLKM Negative reference clock differential pair

12 USIM_CLK Clock signal for User Identity Module

13 PCIe_CREFCLKP Positive reference clock differential pair

14 USIM_RST Reset signal for User Identity Module

15 GND Ground

16 USIM_VCC Variable supply voltage for User Identity Module



18

18 GND Ground



21 GND Ground

22 PCIE_RST_B PCI Express reset

23 PCIe_CRXM Receiver differential pair negative signal, Lane 0

24 MPCIE_3V3 Auxiliary voltage source, 3.3V

25 PCIe_CRXP Receiver differential pair positive signal, Lane 0

26 GND Ground

27 GND Ground


29 GND Ground

30 PCIe_SMB_CLK System Management Bus clock

31 PCIe_CTXM Transmit differential pair negative signal, Lane 0

32 PCIe_SMB_DATA System Management Bus data

33 PCIe_CTXP Transmit differential pair positive signal, Lane 0

34 GND Ground

35 GND Ground

36 PCIE_USB_DM USB data interface differential pair, negative signal

37 GND Ground

38 PCIE_USB_DP USB data interface differential pair, positive signal


40 GND Ground


42 LED_WWAN_B LED status indicator signal

43 GND Ground

44 LED_WLAN_B LED status indicator signal


46 LED_WPAN_B LED status indicator signal




50 GND Ground



Table 8: MiniPCIe slot pinout definition

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¥¡¤¤

¦§¢¨¡¤m

¥¡¤¤ ©ª«¬¬

®¯¯

7mmFull-length size Half-length size

Figure 20: MiniPCIe card and slot diagram


19

The PCI Express signal has a point-to-point topology. The figure below shows the PCI Express x1 point-

to-point bus connection from MXM connector to MiniPCI Express slot/device.

°±²³´±µ¶°

°±²³´±µ¶·

¸ ¹º»

¸ ¹º»

¼½¾¿À ÁÂÃÃÀÄÀÅ¿ÂÆÇÇÈPCIe_±ÉÊ°

PCIe_±ÉÊ·

ËÌÍÎÍÏ ÐÑÒÒÓÍÒ ÔÕÑÒÖ

¸×ØÙÚ

ÛÜ×Ü ¹º» ØÝ ÛÜ×Ü ¹º» ØÝ

ËÞßàáËâã

ßÕÖäåÍ

æçèéêëìèéíî

¼½¾¿À ÁÂÃÃÀÄÀÅ¿ÂÆÇÇÈPCIe_±ïÊ°

PCIe_±ïÊ·

¸ ¹º»

¸ ¹º»

¸×ØÙÚ

°±²ð´ñò¶ð´ó

°±²ð´Éôï´ó

õö÷øùúûüý

õö÷øùúûüþ

õö÷øùúÿüý

õö÷øùúÿüþ

õö÷øúÿPû

õö÷øúAø

õö÷øúöúÿø_ý

õö÷øúöúÿø_þ

ßMß ÐÕÏÏÍÕÒ

s

õøûù

õøûù

õøÿù

õøÿù

ÿø_öý

ÿø_öþ

ýAø

(

õøÿPû

Figure 21: MiniPCI Express interface topology example

4.1.2. PCI Express Layout and Routing Recommendations • All the PCI Express signals should be referenced to the ground plane at all times.

• Each trace of differential pairs should route to parallel to each other with the same trace length.

• Each trace of differential pairs should not have more than two via holes.

• Place the AC coupling capacitors as close as possible to the PCI Express slot/device.

• The spacing between differential pairs must be equal at all times (in parallel), even during trace

bending and serpentine topology.

• Differential pairs must be routed on the same layer with maximum of one signal layer change

allowed. The differential pairs must always move to the same layer with the same reference plane.

• Transmit differential pairs are recommended to be routed on the top layer and receive differential

pairs are recommended to be routed on the bottom layer.

• Do not route PCI Express traces under magnetic devices or IC’s, oscillators and clock synthesizers.

• To minimize signal crosstalk, wider spacing is recommended wherever possible between traces.

• It is always best to reduce the line mismatch to add to the timing margin. In other words, a

balanced topology can match the trace lengths within the groups to minimize skew.

Figure 22: PCI Express trace spacing diagram


20

Routing, layout, and trace properties for implementing PCI Express interface in the carrier board are listed

in the following tables.

Signal Group Signal Name AC Coupling

Capacitors

Routing

Topology Signal Type

1-Lane

PCI Express

Transmit PCIE0_TX+ None

Point to Point

Paired Differential

Transmit/Receive

Signals

PCIE0_TX- None

Receive PCIE0_RX+ 0.1uF

PCIE0_RX- 0.1uF

Table 9: PCI Express interface routing guidelines

Signal Group Signal Name Routing Layer Accumulated

Trace Length Note

1-Lane

PCI Express

Transmit PCIE0_TX+

Top or Bottom < 2.6” Do not cross

power plane

division line

PCIE0_TX-

Receive PCIE0_RX+

Top or Bottom < 2.6” PCIE0_RX-

Table 10: PCI Express interface layout guidelines

Signal Name Trace & Spacing (mil)

(S : W : S1 : W : S)

Differential

Trace Impedance

Pair to Pair

Length Mismatch

Spacing to

Other Groups

PCIE0_TX+

20 : 5 : 5 : 5 : 20 85Ω ± 15% 5 mils 20 mils PCIE0_TX-

PCIE0_RX+

PCIE0_RX-

Table 11: PCI Express interface trace properties

4.1.3. PCI Express Reference Schematics The figure below show an example on how a miniPCIe slot can be connected to a Qseven carrier board.

PCIe_CLKP

PCIe_RXP

PCIe_TXMPCIe_TXP

PCIe_SMB_CLKPCIe_SMB_DATA

PCIE_USB_DMPCIE_USB_DP

PCIe_CLKM

LED_WLAN_BLED_WPAN_B

PCIe_RXM

LED_WLANLED_WPAN

LED_WWANLED_WWAN_B

USIM_DATAUSIM_CLKUSIM_RST

GNDGND

GNDGNDGND GND GND

GND

3P3V MPCIE_3V3VCC15

GND

GND

3P3V

USIM_VCC

GND GND

USIM_VCC

3P3V

PCIE_WAKE_B11

PCIE_RST_B 11

I2C3_SDA 5,8,10,11I2C3_SCL 5,8,10,11


PCIe_CRXM11PCIe_CRXP11


USBD_T4+ 11

USBD_T4- 11

Place near CON

R46 0R46 0R45 0R45 0

R49

49.9_1%

R49

49.9_1%

R59 330R59 330R52 330R52 330R51 330R51 330

C2010uFC2010uF

MINICARDCONN

MINIPCIE1

0710A0BA68B

MINICARDCONN

MINIPCIE1

0710A0BA68B

+3.3V52

GND50

+1.5V48

LED_WPAN#46

LED_WLAN#44

LED_WWAN#42

GND40

USB_D+38

USB_D-36

GND34

SMB_DATA32

SMB_CLK30

+1.5V28

GND26

+3.3VAUX24

PERST#22

Reserved20

GND18

UIM_VPP16

UIM_RESET14

UIM_CLK12

UIM_DATA10

UIM_PWR8

+1.5V6

GND4

+3.3V2

-WAKE1

Reserved51

Reserved49

Reserved47

Reserved45

Reserved43

Reserved41

Reserved39

Reserved37

GND35

PETp033

PETn031

GND29

GND27

PERp025

PERn023

GND21

Reserved(UIM_C4)19

Reserved(UIM_C8)17

GND15

REFCLK+13

REFCLK-11

GND9

CLKREQ#7

Reserved5

Reserved3

G1

G2

M1

M2

C27 0.1uFC27 0.1uF

R53 100KR53 100K

C230.1uFC230.1uF

C28 0.1uFC28 0.1uF

C22

4.7uF

C22

4.7uF

R43 0R43 0

C170.1uFC170.1uF

R50 330R50 330

R41 0R41 0

L5

ACM2012E-900-2P-T00

L5

ACM2012E-900-2P-T00

1 4

32

D7BAT54AT-7-F

D7BAT54AT-7-F

3

1

2

R48

49.9_1%

R48

49.9_1%

R40 0R40 0

C1410uFC1410uF C21

10uFC2110uF

R38 0R38 0

U4

SN74LVC1G08DBVR

U4

SN74LVC1G08DBVR

12

43

5

C1910uFC1910uF

R47 0R47 0

R42 0/XR42 0/X

LED2B

VA 25678

LED2B

VA 25678

34

C180.1uFC180.1uF

Figure 23: MiniPCIe slot reference circuitry


21

4.2. Ethernet Interface The QSM-8Q60 module provides one Gigabit Ethernet (LAN) port that complies with the IEEE standard

for 10BASE-T, 100BASE-T, 1000BASE-T, TX and T4 Ethernet interfaces.

The Gigabit Ethernet (LAN) interface of the QSM-8Q60 module consists of four differential signals and

control signals for activity link indicators. These signals can be used to connect to the RJ-45 port with

integrated or external isolation magnetic (transformer) to the carrier board.


GBE_MDI0+ 12 IO

Media Dependent Interface differential pair 0. The TXRX can

operate in 1000, 100, and 10Mbps modes. This signal pair is used

for all modes. GBE_MDI0- 10

GBE_MDI1+ 11 IO


operate in 1000, 100, and 10Mbps modes. This signal pair is used

for all modes. GBE_MDI1- 9

GBE_MDI2+ 6 IO


operate in 1000, 100, and 10Mbps modes. This signal pair is only

used 1000Mbps Gigabit Ethernet mode. GBE_MDI2- 4

GBE_MDI3+ 5 IO


operate in 1000, 100, and 10Mbps modes. This signal pair is only

used 1000Mbps Gigabit Ethernet mode. GBE_MDI3- 3

GBE_LINK# 13 IO Ethernet controller link indicator, active low

GBE_ACT# 14 IO Ethernet controller 0 activity indicator

Table 12: Ethernet signal definition


22

4.2.1. Ethernet Interface Topology This section shows the layout recommendations of both transmit and receive differential data pairs and

single-ended control signal between the QSM-8Q60 module and RJ-45 port with integrated magnetic

module.

Qseven Carrier Board

0.1uF

0.1uF

3P3V

3P3V

Route Differentially

TXRXP_A

TXRXM_A


TXRXP_B

TXRXM_B


TXRXP_D

TXRXM_D


TXRXP_C

TXRXM_C

LED1_ACT-

LED2_LINK-

330 ohm

330 ohm

0 ohm

RJ-45 + LED

1

2

3

6

4

5

7

8

GBE_MDI0-

GBE_MDI0+

GBE_LINK#

GBE_ACT#

MXM Connector

GBE_MDI1-

GBE_MDI1+

GBE_MDI2-

GBE_MDI2+

GBE_MDI3-

GBE_MDI3+

QSM-8Q60

Module

Ed

ge F

ingers

TX+

TX-

RX+

RX-

TX+

TX-

RX+

RX-

T+

T-

R+

R-

T+

T-

R+

R-

Figure 24: Gigabit Ethernet layout recommendations (integrated magnetic module)

Notes:

1. If the Gigabit Ethernet implementation is not being use, the pins GBE_MDI2+, GBE_MDI2-, GBE_MDI3+ and

GBE_MDI3- should not be connected.

2. It is recommended to use termination circuits for the unused pin at the RJ-45 connector and for wire-side

center-taps of the magnetic module. Improper usage (or lack of usage) of the termination circuits for those

unused pins at the RJ-45 connector wire-side center taps of the transformer will cause emissions and long

cable noise problems related to other IEEE conformance issues.

3. If using an external LAN magnetic module, the magnetic module has to be placed as close as possible to

the RJ-45 port. The distance must be <1”.


23

4.2.2. Gigabit Ethernet Layout and Routing Recommendations • Route differential pairs close together and away from other signals.

• Route any other trace parallel to one of the differential trace.

• Keep trace length within each differential pair equal.

• Keep proper impedance between two traces within a differential pair.


• Each differential pair of signals is required to be paralleled to each other with the same trace

length (Tolerance ±50 mils) on the component (top) layer and to be paralleled to a respective

ground plane. The length difference between the shortest and longest pairs should be less than

200 mils.

• The accumulated trace length of differential signals pair between the MXM connector and

magnetic module should be less than 1”.

• The accumulated trace length of differential signals pair between the external magnetic module

and RJ-45 connector should be less than 1″. Isolate ground plane and connect to chassis earth.

• Keep each differential pair on the same plane.

• To prevent any noise from injecting into the differential pairs, be sure to keep digital signals or

other signals away from the differential signals.

• The external magnetic module should be placed close to the RJ-45 connector to limit EMI

emissions.

Routing, layout, and trace properties for implementing Gigabit Ethernet interface in the carrier board are

listed in the following tables.

Signal Group Signal Name Topology Signal Type Note

Differential Pair

GBE_MDI0+

Point to Point Differential

Data I/O Pairs

Route traces as

short as possible

GBE_MDI0-

GBE_MDI1+

GBE_MDI1-

GBE_MDI2+

GBE_MDI2-

GBE_MDI3+

GBE_MDI3-

Control GBE_LINK#

Point to Point Single-Ended Route traces as

short as possible GBE_ACT#

Table 13: Gigabit Ethernet interface routing guidelines


Trace Length Note

Differential Pair

GBE_MDI0+

Top Layer < 1.2” Do not cross power

plane division line

GBE_MDI0-

GBE_MDI1+

GBE_MDI1-

GBE_MDI2+

GBE_MDI2-

GBE_MDI3+

GBE_MDI3-

Control GBE_LINK#

Top Layer < 1.2” Do not cross power

plane division line GBE_ACT#

Table 14: Gigabit Ethernet interface layout guidelines


24

Signal Name Trace & Spacing (mil)

(S : W : S1 : W : S) Trace Impedance

Pair to Pair

Length Mismatch

Spacing to

Other Group

GBE_MDI0+

20 : 5 : 8 : 5 : 20 100Ω ± 15%

differential 5 mils 20 mils

GBE_MDI0-

GBE_MDI1+

GBE_MDI1-

GBE_MDI2+

GBE_MDI2-

GBE_MDI3+

GBE_MDI3-

GBE_LINK# 5 : 8 55Ω ± 10% - 20 mils

GBE_ACT#

Table 15: Gigabit Ethernet interface trace properties

4.2.3. Gigabit Ethernet Reference Schematics

Figure 25: Gigabit Ethernet reference circuitry


25

4.3. USB Interface The Universal Serial Bus (USB) provides a bi-directional, isochronous, hot-attachable Plug and Play serial

interface for adding external peripheral devices (e.g., game controllers, communication devices, and input

devices) on a single bus. The USB interface of the QSM-8Q60 module is compliant to USB 2.0

specification.

The QSM-8Q60 module can support up to four USB 2.0 host and one USB 2.0 client port.


USB_P0+ 96 IO Universal Serial Bus port 0, data+

USB_P0- 94 IO Universal Serial Bus port 0, data-

USB_P1+ 95 IO OTG Universal Serial Bus port 1, data+

USB_P1- 93 IO OTG Universal Serial Bus port 1, data-







USB_2_3_OC# 85 I Universal Serial Bus over-current sense, USB ports 2 and 3

USB_4_5_OC# 80 I Universal Serial Bus over-current sense, USB port 4

USB_ID 92 I Universal Serial Bus I.D. pin. Configures the mode of USB port 1

Table 16: USB signal definition

4.3.1. USB Layout and Routing Recommendations • The layout guidelines for the USB data lines are listed below. And a routing example for two

pairs of USB data buses is shown in Figure 27.

• The differential pair signals should be all referenced to ground.


• Differential pair route in parallel and in equal length.

• The amount of vias and corners used for the USB 2.0 signal layout should be minimized; this is to

prevent the occurrence of reflection and impedance changes.

• Each pair of USB data lines is required to be parallel to each other with the same trace length

(see Figure 27), and not parallel with other signals to minimize crosstalk.

• Separate the signal traces into similar groups and route similar signal traces together. In addition,

it is recommended to have differential pairs routed together on the motherboard.

• Control trace signals (USB_2_3_OC#, USB_4_5_OC# and USB_ID) impedance should maintain

55Ω ± 10%.

• For the USB traces, do not route them under oscillators, crystals, clock synthesizers, magnetic

devices or IC’s which could be using duplicate clocks.

Route to Minimum

45

45

USBD_T+

USB

Receptacle

USB

Receptacle

Cable Ground

Cable Power

USB Twisted Pair Cable

USB

DeviceUSBD_T-

QSM-8Q60

Module

MXM

Connector


Ed

ge F

ingers

90

Figure 26: USB differential signal layout recommendations


26

R!"#$$!%&!&

N#' )!"#mmended*+*

C,--./0,1

QSM-8Q60

Module

Ed

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ingers

USB port

USB port


Figure 27: USB differential signal routing example

Figure 28: USB 2.0 trace spacing diagram

Routing, layout, and trace properties for implementing USB interface in the carrier board are listed in the

following tables.

Signal Group Signal Name Termination Option Topology Signal Type

Differential

Data Pair

Port 0 USB_P0+

None Point-to-Point Differential

Data I/O Pairs

USB_P0-

Port 1 USB_P1+

USB_P1-

Port 2 USB_P2+

USB_P2-

Port 3 USB_P3+

USB_P3-

Port 4 USB_P4+

USB_P4-

Control

USB_2_3_OC#

None Point-to-Point Single-ended USB_4_5_OC#

USB _ID

Table 17: USB interface routing guidelines


27

Signal Group Signal Name Routing Layer Termination

Stub Length

Accumulated

Trace Length Note

Differential

Data Pair

Port 0 USB_P0+

Top or Bottom < 1″ < 4″

USB_P0-

Port 1 USB_P1+

USB_P1-

Port 2 USB_P2+

USB_P2-

Port 3 USB_P3+

USB_P3-

Port 4 USB_P4+

USB_P4-

Control

USB_2_3_OC#

Top or Bottom < 1″ Route to

minimum USB_4_5_OC#

USB_ID

Table 18: USB interface layout guidelines

Signal Name Trace Impedance Trace & Spacing (mil)

(S : W : S1 : W : S)

Pair to Pair

Length Mismatch

Spacing to

Other Group

USB_P0+

90Ω ± 15% 20 : 5 : 5 : 5 : 20 5 mils < 0.03″

USB_P0-

USB_P1+

USB_P1-

USB_P2+

USB_P2-

USB_P3+

USB_P3-

USB_P4+

USB_P4-

USB_2_3_OC#

55Ω ± 10 5 : 10 - < 0.02″ USB_4_5_OC#

USB_ID

Table 19: USB interface trace properties


28

4.3.2. USB Reference Schematics

Figure 29: USB host reference circuitry

The USB port mode can be controlled by the signal USB_ID. In the reference circuitry example below, the

USB_ID signal is referenced to ground that makes the USB port 1 mode as Client USB (or USB OTG port).

Figure 30: USB client reference circuitry


29

4.4. LVDS Interface The LVDS interface in the VIA QSM-8Q60 module enables displaying graphics on LVDS flat panel. The

LVDS is a dual-channel that supports 18-bit and 24-bit interfaces.

The LVDS signal interface consists of four differential data pairs and one differential clock pair for each

channel, and five single-ended control signals. The five single-ended control signals are used for LVDS

power enable, backlight control, enable lines and I2C interface.

The LVDS interface signals are implemented in MXM connector.


LVDS_A0+ 99 O LVDS channel A differential signal pair 0

LVDS_A0- 101


LVDS_A1- 105


LVDS_A2- 109


LVDS_A3- 115

LVDS_A_CLK+ 119 O LVDS channel A differential clock pair

LVDS_A_CLK- 121

LVDS_B0+ 100 O LVDS channel B differential signal pair 0

LVDS_B0- 102


LVDS_B1- 106


LVDS_B2- 110


LVDS_B3- 116

LVDS_B_CLK+ 120 O LVDS channel B differential clock pair

LVDS_B_CLK- 122

LVDS_PPEN 111 O LVDS flat panel power enable

LVDS_BLEN 112 O LVDS flat panel backlight enable

LVDS_BLT_CTRL 123 O LVDS flat panel backlight brightness control via

pulse width modulation.

LVDS_BLC_DAT/eDP0_HPD# 126 IO Control data signal for external SSC clock chip

LVDS_BLC_CLK/eDP1_HPD# 128 IO Control clock signal for external SSC clock chip

LVDS_DID_DAT/GP2_I2C_DAT 125 IO General Purpose I2C bus data line / DisplayID DDC

data line used for LVDS flat panel detection

LVDS_DID_CLK/GP2_I2C_CLK 127 IO General Purpose I2C bus clock line / DisplayID DDC

clock line used for LVDS flat panel detection

Table 20: LVDS signal definition


30

LVDS1_CLK_P23

L456789L:8;/N


S<=>?@ BDEcontroller

Power

control

F?GH@>IJKcontrol

F?GH@>IJK ?OQ TUV<=W<@<GK XYZ[<=

\O]<=K<=GUOO<GKU=

^^T`DE

a UJZLVDS0_TX[3:0]P

LVDS0_TX[3:0]N

LVDS1_TX[3:0]P

LVDS1_TX[3:0]N

LVDS_BLEN

LVDS_PWM2

LVDS_PPEN

I2C1_SDA

I2C1_SCL

LCD Panel LVDS

Connector

Ed

ge F

ingers

LVDS_A[3:0]+

LVDS_BLT_CTRL

LVDS_DID_DAT

LVDS_B_CLK+/-

LVDS_A_CLK+/-

LVDS_A[3:0]-

LVDS_B[3:0]+

LVDS_B[3:0]-

LVDS_DID_CLK

LVDS_PPEN

LVDS_BLEN

MXM Connector

QSM-8Q60

Module

Figure 31: LVDS panel interface implementation

4.4.1. LVDS Layout and Routing Recommendations The layout and routing recommendations for the LVDS interface in carrier board are listed below:

• Differential pairs should all be referenced to ground.


• Each differential pair signal (LVDS_A[3:0]±, LVDS_B[3:0]±) and clock differential pair

(LVDS_A_CLK±, LVDS_B_CLK±) should be routed parallel to each other with the same trace

length.

• Clock differential pair signals (LVDS_A_CLK±, LVDS_B_CLK±) should be length matched <20 mils.

• Route the LVDS pairs on a single layer adjacent to a ground plane.

Routing, layout, and trace properties for implementing LVDS interface in the carrier board are listed in the

following tables.

Signal Group Signal Name Signal Reference Topology Signal Type

Data

LVDS_A[3:0]+

Ground or Power Point to Point Differential

Data I/O Pairs

LVDS_A[3:0]-

LVDS_B[3:0]+

LVDS_B[3:0]-

Clock

LVDS_A_CLK+

Ground or Power Point to Point Differential

Data I/O Pairs

LVDS_A_CLK-

LVDS_B_CLK+

LVDS_B_CLK-

Control

LVDS_PPEN

Ground or Power Point to Point Single-ended LVDS_BLEN

LVDS_BLT_CTRL

LVDS_BLC_DAT Ground or Power Point to Point Single-ended

LVDS_BLC_CLK

LVDS_DID_DAT Ground or Power Point to Point Single-ended

LVDS_DID_CLK

Table 21: LVDS interface routing guidelines


31


Trace Length Note

Data

LVDS_A[3:0]+

Top or Bottom <1.8″ Route each pair of

wires in parallel

LVDS_A[3:0]-

LVDS_B[3:0]+

LVDS_B[3:0]-

Clock

LVDS_A_CLK+

Top or Bottom <1.8″ Route each pair of

wires in parallel

LVDS_A_CLK-

LVDS_B_CLK+

LVDS_B_CLK-

Control

LVDS_PPEN

Top or Bottom <1.8″ LVDS_BLEN

LVDS_BLT_CTRL

LVDS_BLC_DAT Top or Bottom <1.8″

LVDS_BLC_CLK

LVDS_DID_DAT Top or Bottom <1.8″

LVDS_DID_CLK

Table 22: LVDS interface layout guidelines


(S : W : S1 : W : S)

Pair to Pair

Length Mismatch Spacing to

Other Groups

LVDS_A[3:0]+

100Ω ± 15% 20 : 5 : 8 : 5 : 20 5 mils 20 mils LVDS_A[3:0]-

LVDS_B[3:0]+

LVDS_B[3:0]-

LVDS_A_CLK+

100Ω ± 15% 20 : 5 : 8 : 5 : 20 5 mils 20 mils LVDS_A_CLK-

LVDS_B_CLK+

LVDS_B_CLK-

LVDS_PPEN

55Ω 5 : 8 - 8 mils LVDS_BLEN

LVDS_BLT_CTRL

LVDS_BLC_DAT 55Ω 5 : 8 - 8 mils

LVDS_BLC_CLK

LVDS_DID_DAT 55Ω 5 : 8 - 8 mils

LVDS_DID_CLK

Table 23: LVDS interface trace properties


32

4.4.2. LVDS Reference Schematics The following reference circuitry is an example of how to implement the LVDS interface on the carrier

board.

LVDS0_TX1_NCLVDS0_TX1_PC


LVDS0_CLK_NCLVDS0_CLK_PC




LVDS0_TX3_NLVDS0_TX3_P







LVDS0_CLK_NLVDS0_CLK_P

















RN6 0RN6 0

1 23 4

RN7 0RN7 0

1 23 4

RN2 0RN2 0

1 23 4

RN5 0RN5 0

1 23 4

RN1 0RN1 0

1 23 4

RN3 0RN3 0

1 23 4

IVDD PVDD_PWR

3P3V

5VIN5VIN

+12V_VIN **

J1(1-3)

MINI-JUMPER

J1(1-3)

MINI-JUMPER

J1(2-4)

MINI-JUMPER

J1(2-4)

MINI-JUMPERJ1

2208SM-06G-CP

J1

2208SM-06G-CP

13 4

2

5 6

RN4 0RN4 0

1 23 4

RN8 0RN8 0

1 23 4

RN9 0RN9 0

1 23 4

RN10 0RN10 0

1 23 4

LVDS0_EDID_SCLLVDS0_EDID_SDA

PVDD


LVDS0_TX2_NC

LVDS0_TX1_PCLVDS0_TX1_NC


LVDS0_CLK_PCLVDS0_CLK_NC

LVDS0_TX2_PC






3P3V

3P3V

5VIN

I2C3_SDA7,8,10,11I2C3_SCL7,8,10,11

PDD_ 2A= 80mils

R14100_1%/X R14100_1%/X

R22

4.7K

R22

4.7K

R24 0R24 0

R16 100_1%/XR16 100_1%/X

C410uFC410uF

R17100_1%/X R17100_1%/X

LVDS1

87209-4040-06

LVDS1

87209-4040-06

22

11

44

33

66

55

88

77

1010

99

1212

1111

1414

1313

1616

1515

1818

1717

2020

1919

2222

2121

2424

2323

2626

2525

2828

2727

3030

2929

3232

3131

3434

3333

3636

3535

3838

3737

4040

3939

G1

G1

G2

G2

M1

M1

M2

M2

R19100_1%/X R19100_1%/X

R23 100_1%/XR23 100_1%/X

R13 100_1%/XR13 100_1%/X

C50.1uFC50.1uF

R18 100_1%/XR18 100_1%/X

C3

0.1uF

C3

0.1uF

R214.7KR214.7K

R25 0R25 0

R20 100_1%/XR20 100_1%/X

R12100_1%/X R12100_1%/X

R15100_1%/X R15100_1%/X

Figure 32: LVDS connector example

PVDD

5VIN

PVDD_PWR

LVDS_PPEN11

R26

374K_1%

R26

374K_1%

C60.1uFC60.1uF

C822uFC822uF

R2833R2833

FB2CBF-2012ES-121U/XFB2CBF-2012ES-121U/X

C70.1uFC70.1uF

R33 4.7KR33 4.7K

R30 140K_1%R30 140K_1%

FB3CBF-2012ES-121U

FB3CBF-2012ES-121U

C10

0.1uF

C10

0.1uF

Q3

Si3443CDV-T1-GE3

b3

Si3443CDV-T1-GE3

1234 5 6

C9

0.1uF/X

C9

0.1uF/X

b4

NX7002AK

b4

NX7002AK

1

32

b5

NX7002AK

b5

NX7002AK

1

32

Figure 33: LVDS panel power reference circuitry

IVDD

BLT_EN

3P3V

LVDS_PWM211LVDS_BLEN11

PWM_cUT111

IVDD_ 2A= 80mils

R27220_1%/XR27220_1%/X Fd4

eT2012RL600fC2ALF

Fd4

eT2012RL600fC2ALF

R31 0R31 0R29 0R29 0

R32 0/XR32 0/X

Fd5Fd5

C110.1uFC110.1uF

C1210uFC1210uF

R34

33K_1%

R34

33K_1%

INVERTER1

85205-0800N

INVERTER1

85205-0800N

11

22

33

44

55

66

88

77

G1G1

G2G2

Figure 34: LVDS backlight reference circuitry


33

4.5. HDMI Interface The VIA QSM-8Q60 supports one HDMI interface. The HDMI is used to connect high definition video and

digital audio using a single cable. It allows connecting the digital video devices to utilize a high definition

video signal.

HDMI interface uses four differential data pair signals that carries video and audio signals.

Signal Name Shared with Pin # I/O Description

TMDS_CLK+ DP_LANE3+ 131 O TMDS differential pair clock lines

TMDS_CLK- DP_LANE3- 133

TMDS_LANE0+ DP_LANE2+ 143 O TMDS differential pair lines lane 0

TMDS_LANE0- DP_LANE2- 145





HDMI_CTRL_DAT - 150 IO DDC based control signal (data) for HDMI device

HDMI_CTRL_CLK - 152 IO DDC based control signal (clock) for HDMI device

DP_HDMI_HPD# - 153 I Hot plug detection signal that serves as an

interrupt request

Table 24: HDMI interface signal definition

1

2

g4

5

6

7

8

h

10

11

12

jg

jh

18

17

16

15

klmnopqr

jtqu vwxjtqu vwxy vwx

1 4

2 3

1 4

2 3

1 4

2 3

1 4

2 3

zmn |~

10K

620 o

3P3V

y vwx

3P3V

6

q10K vwx

2

1

38

gh

36

gq

33

32

16

jq

12

13

h

10

18

jh

3 8 20 21 26 31

10K vwx10K vwx

10K vwx

0.1uF

y vwx

y vwx

er

|¡ x¢ n¡

10K vwx

10K vwx

q 3P3V

l£ ¤¥¡w ¦¦Digital FET

23

22

y vwxy vwx

3P3V

§t¨u vwx

10K vwx

10K vwx

¨3P3V

30

§tgu vwx j©

ª 8 11 «¬ ª ¬ ®ª ª¯

0.1uF 0.1uF

3P3V

QSM-8Q60Module

Ed

ge F

ingers

TMDS_LANE0+

TMDS_CLK-

TMDS_LANE2-

TMDS_LANE2+

TMDS_LANE0-

TMDS_LANE1+

TMDS_LANE1-

°±²³°´µ²³±°¶

TMDS_CLK+

·¸¹º¹»¼½¼¾¿»»¹ÀÁ¿Â

eDP1_³±°¶

³°´µ²ÃÄÅÆ²ÃÆÇ

³°´µ²ÃÄÅÆ²°ÈÄ 28

h

2 3

1

ÉÊËÌËÍ ÎÏÐÐÑËÐ ÒÓÏÐÔ

3P3V

y vwx

jtÕqu vwx j©

Figure 35: HDMI interface connector diagram


34

4.5.1. HDMI Layout and Routing Recommendations

• Differential pair should be all referenced to ground.


• Each differential pairs signal should route to parallel to each other with the same trace length.

• Route the differential pairs on a single layer adjacent to a ground plane.

Routing, layout and trace properties for implementing HDMI interface in the carrier board are listed in the

following tables.

Signal Group Signal Name Signal Reference Routing Topology Signal Type

Data

TMDS_LANE0+

Ground Point to Point Differential

Data I/O Pairs

TMDS_LANE0-

TMDS_LANE1+

TMDS_LANE1-

TMDS_LANE2+

TMDS_LANE2-

Clock TMDS_CLK+

Ground Point to Point Differential Pairs TMDS_CLK-

Control

HDMI_CTRL_DAT

Ground Point to Point Single-ended HDMI_CTRL_CLK

DP_HDMI_HPD#

Table 25: HDMI interface routing guidelines


Trace Length Note

Data

TMDS_LANE0+

Top or Bottom < 3.3”

TMDS_LANE0-

TMDS_LANE1+

TMDS_LANE1-

TMDS_LANE2+

TMDS_LANE2-

Clock TMDS_CLK+

Top or Bottom <3.3” TMDS_CLK-

Control

HDMI_CTRL_DAT

Top or Bottom HDMI_CTRL_CLK

DP_HDMI_HPD#

Table 26: HDMI interface layout guidelines


(S : W : S1 : W : S)

Spacing to

Other Signal

Pair to Pair

Length Mismatch

TMDS_LANE0+

100Ω ± 15% 15 : 5 : 6 : 5 : 15 15 mils < 100 mils

TMDS_LANE0-

TMDS_LANE1+

TMDS_LANE1-

TMDS_LANE2+

TMDS_LANE2-

TMDS_CLK+ 100Ω ± 15% 5 : 6 15 mils < 100 mils

TMDS_CLK-

HDMI_CTRL_DAT

55Ω ± 15% 5 : 6 6 mils - HDMI_CTRL_CLK

DP_HDMI_HPD#

Table 27: HDMI interface trace properties


35

4.5.2. HDMI Reference Schematics

ÖDMI_TX0_PC

DP1TX1-

DP1TX0×DP1TX0-

DP1TX1×

ÖDMI_TX2_NC

ÖDMI_TX1_NC

ÖDMI_TXC_PCÖDMI_TXC_NC

ÖDMI_TX2_PC

ÖDMI_TX0_NC

ÖDMI_TX1_PC

DP1TX2×

DP1TX3-

DP1TX2-

ÖDMI_DSDA

ÖDMI_TX1_NC


ÖDMI_TX2_PC

ÖDMI_DSCL

ÖDMI_ÖPD

ÖDMI_TX0_NCÖDMI_TX0_PC


ÖDMI_CEC_IN

DP1TX3×

GND GND

ÖDMI_×5V

GND

HDMIL3 DLØ2012Ù-900NPL3 DLØ2012Ù-900NP

1 4

32

R602 10K/XR602 10K/X

L1 DLØ2012Ù-900NPL1 DLØ2012Ù-900NP

1 4

32

C10.1uFC10.1uF

R1

0

R1

0


1 4

32


1 4

32

ÖDMI1

51U19S-323N-A4-ÙD

ÖDMI1

51U19S-323N-A4-ÙD

12345678910111213141516171819

G1

G2

G4

G3

ÖDMI_TX1_NC

ÖDMI_TX2_PCÖDMI_TX2_NCÖDMI_TX1_PC

ÖDMI_DSDAÖDMI_DSCL

ÖDMI_ÖPDÖDMI_DSDA

ÖDMI_CEC_INÖDMI_DSCL

ÖDMI_ÖPD



ÖDMI_TX1_NC

ÖDMI_TX2_PCÖDMI_TX2_NCÖDMI_TX1_PC



ÖDMI_CEC_INÖDMI_CEC_IN11

ÖDMI_ÖPD11

D2

RCÚÛÜÝ0544T.TCT/X

D2


2

G1

34

1

56

78

D4


D4


2

G1

34

1

56

78

D1


D1


2

G1

34

1

56

78

ÖDMI_DSDAÖDMI_DSCL

ÖDMI_DDC_CLK_INÖDMI_DDC_CLK_IN

DDI_CTRL_DATA ÖDMI_DDC_DAT_INÖDMI_DDC_DAT_IN

DDI_CTRL_CLK

ÖDMI_DDC_DAT_INÖDMI_DDC_DAT_IN

ÖDMI_DDC_CLK_INÖDMI_DDC_CLK_IN

ÖDMI_×5V

3P3V

3P3V

I2C2_SDA11

I2C2_SCL11

R8 1.5KR8 1.5KR7 1.5KR7 1.5K

Þ1FDC6301N

Þ1FDC6301N

G1

1

S2

2

G2

3D2

4

S1

5

D1

6

R44 0/XR44 0/X

R4 0R4 0

R6 0R6 0

R24.7KR24.7K

R70 0/XR70 0/X

R5 0R5 0

R9 0R9 0

R34.7KR34.7K

ÖDMI_×5V

×12V VIN

5VIN

ÖDMI_×5V

R11 0/XR11 0/X

C2

1uF

C2

1uF

PS1

SMD1206P150TFT

PS1

SMD1206P150TFT

1 2

D3Ù320A-13-F/X

D3Ù320A-13-F/XA K

Þ2

SM2306NSAC-TRG

Þ2

SM2306NSAC-TRG

G

DS

R1010K/XR1010K/X

FÙ1ÞT2012RL600ÖC2ALF

FÙ1ÞT2012RL600ÖC2ALF

DP1TX2-

DP1TX1×

DP1TX1-

DP1TX2×

DP1TX0×

DP1TX3×

DP1TX3-

DP1TX0-

For HDMI; close to TMDS141

C192 0.1uF/XC192 0.1uF/X

C191 0.1uF/XC191 0.1uF/X

C193 0.1uF/XC193 0.1uF/XR495 300_1%/XR495 300_1%/X

R493 300_1%/XR493 300_1%/X

R494 300_1%/XR494 300_1%/X

R500 300_1%/XR500 300_1%/XC194 0.1uF/XC194 0.1uF/X

TMDS_RX2-

TMDS_RXC-

TMDS_RX1×

TMDS_RXC×

TMDS_RX0-

TMDS_RX2×TMDS_RX1-

TMDS_RX0×

3P3V

Note: Please place close to U33 TMDS141.

R596 620_1%/XR596 620_1%/X

R601 620_1%/XR601 620_1%/X

R594 620_1%/XR594 620_1%/X

R597 620_1%/XR597 620_1%/X

R599 620_1%/XR599 620_1%/XR600 620_1%/XR600 620_1%/X

R593 10K/XR593 10K/X

R595 620_1%/XR595 620_1%/X

R598 620_1%/XR598 620_1%/X

Þ43

NX7002AK/X

Þ43

NX7002AK/X

1

32

ÖDMI_D2P

ÖDMI_D1P

ÖDMI_CLKP

TMDS_RX0×ÖDMI_D2M

PRE

TMDS_RX0-

TMDS_RX1×

DDI_CTRL_DATA

TMDS_RX1-

ßVS

TMDS_RX2×TMDS_RX2-

DP1TX0×

TMDS_RXC×TMDS_RXC-

ÖDMI_D1M

DP1TX0-

DP1TX1×

ÖDMI_D0PDP1TX1-

DP1TX2×ÖDMI_D0M DP1TX2-

DP1TX3×

VSADJ

ÖDMI_CLKM DP1TX3-

-ßEÙ

DDI_CTRL_CLK

3P3V

3P3V

3P3V

3P3V

ÖDMI_D2P11ÖDMI_D2M11



ÖDMI_CLKP11ÖDMI_CLKM11

I2C2_SDA11I2C2_SCL11

U33

TMDS141RÖAR

U33

TMDS141RÖAR

TX1à 13

GND

14

RX2à1

I2CEN5

VCC

11

VCC

27

VCC

24

RX22

ßEà6PRE

7

TX29

TX2à 10

GND

20

TXCà 19

GND

3

RSDA28

VCC

4

TXC18

TSDA23

TSCL22

GND

8

GND

21

ßVS25

TX112

TX0à 16TX0

15

VCC

17

GND

26

RSCL29

VSADJ30

GND

31

RXC33

RXCà32

VCC

34

RX036

RX0à35

GND

37

RX139

RX1à38

VCC

40

G1

G1

C1600.01uFC1600.01uF

R171 0R171 0

R176 0R176 0

C1610.01uFC1610.01uF

R177 0R177 0

C1620.01uFC1620.01uF

C1560.01uFC1560.01uF

R170 0R170 0

C1570.01uFC1570.01uF

R585 10KR585 10K

C1580.01uFC1580.01uF

R172 0R172 0

C1590.01uFC1590.01uF

R173 0R173 0

R73 0/XR73 0/X

R588 4.3K_1%R588 4.3K_1%R589 10KR589 10KR590 10K/XR590 10K/X

R587 10KR587 10KR584 10K/XR584 10K/X

R74 0/XR74 0/X

R586 10K/XR586 10K/X

R175 0R175 0

R583 10KR583 10K

R174 0R174 0

3P3V

I2C2_SDA11

I2C2_SCL11R591 1.65K_1%/XR591 1.65K_1%/X

R592 1.65K_1%/XR592 1.65K_1%/X

Figure 36: HDMI interface reference circuitry


36

4.6. Audio Interface The Audio interface is a link between the QSM-8Q60 module and Audio Codec that supports the I2S bus

in the carrier board. This section contains I2S layout and routing information.

The corresponding audio interface signals are defined in the table below.


HDA_RST#/I2S_RST# 61 O Codec reset

HDA_SYNC/I2S_WS 59 O Serial Sample Rate Synchronization

HDA_BITCLK/I2S_CLK 63 O Bit clock for Codec

HDA_SDO/I2S_SDO 67 O Serial Data Output to Codec

HDA_SDI/I2S_SDI 65 I Serial Data Input Stream from Codec

Table 28: Audio interface signal definition

QSM-8Q60

Module

Ed

ge F

ingers


á âãäåæçèéêëìíîïéèðé

åæçèéæñíîïéèéæñ

åæçèòéóíîïéèòéóô

åæçèõîTCLK/I2S_CLK

åæçèéæîíîïéèéæî

MXM Connector

I2S_LRCLK

îïéèæñöó

SYS_MCLK

I2S_SCLK

I2S_DIN

I C Audio Codec2

22 oãä

Route to minimum

Figure 37: Onboard I2S audio codec implementation example

4.6.1. Audio Layout and Routing Recommendations

• Route the analog and digital trace signals as far as possible from each other to prevent noise.

• Route the clock trace away from any analog input and voltage reference pins.

• Isolate the codec or put away from any major current path or ground bounce.

• Fill with copper the regions between the analog traces and attached it to the analog ground.

• Fill with copper the regions between the digital traces and attached it to the digital ground.

Note:

For optimizing timing and signal quality issues, the values of the series resistors are design dependent and

should be verified.

Routing, layout and trace properties for implementing audio interface in the carrier board are listed in the

following tables.

Signal Name Signal Reference Topology Signal Type

HDA_RST#/I2S_RST# Ground or Power Point to Point Single-ended

HDA_SYNC/I2S_WS

HDA_BITCLK/I2S_CLK Ground or Power Point to Point Single-ended

HDA_SDO/I2S_SDO Ground or Power Point to Point Single-ended

HDA_SDI/I2S_SDI Ground or Power Point to Point Single-ended

Table 29: Audio interface routing guidelines


37

Signal Name Routing Layer Accumulated Trace Length Note

HDA_RST#/I2S_RST# Top or Bottom

Route traces as

short as possible

HDA_SYNC/I2S_WS

HDA_BITCLK/I2S_CLK Top or Bottom

HDA_SDO/I2S_SDO Top or Bottom

HDA_SDI/I2S_SDI

Table 30: Audio interface layout guidelines

Signal Name Trace Impedance Trace Width

and Spacing (mil)

Spacing to

Other Signal

HDA_RST#/I2S_RST# 55Ω ± 10% 5 : 10

HDA_SYNC/I2S_WS

HDA_BITCLK/I2S_CLK 55Ω ± 10% 5 : 20

HDA_SDO/I2S_SDO 55Ω ± 10% 5 : 10

HDA_SDI/I2S_SDI

Table 31: Audio interface trace properties

4.6.2. Audio Reference Schematics

LINE÷UT_LLINEIN_L

LINEIN_R

AUDI÷_CLK

LINE÷UT_R

LINE_IN_L

LINE_IN_R

øP_R øEAD_RIGøT

øEAD_LEFT

C÷DEC_I2C_DAT

C÷DEC_I2C_CLK

MICùIAS

MIC_IN

VDDD

GND_ANAL÷G

3P3V

3P3V

VCC15

AUD4_TXD11

AUD4_RXD11

AUD4_TXC11

AUD4_TXFS11

I2C3_SDA5,7,8,11

I2C3_SCL5,7,8,11

GPI÷_0_CLK÷11R67 22R67 22

C400.1uFC400.1uF

TP3TP31

C47 1uFC47 1uF

C46 0.1uFC46 0.1uF

C420.1uFC420.1uF

TP1TP1

1

LINE_IN_R LINE_IN_LøEAD_RIGøT øEAD_LEFT

MIC_IN MIC_IN

GND_ANAL÷G GND_ANAL÷G

AUDI÷1

1600S-08-SM-TR

AUDI÷1

1600S-08-SM-TR

13 4

2

5 68109

R68 0R68 0

Fù7úT1608RL060øC3A-LFFù7úT1608RL060øC3A-LF

R66 0R66 0

TP4TP41

CE3220uF

CE3220uF

C49 0.1uFC49 0.1uF

C45 4.7uFC45 4.7uF

C48 0.1uFC48 0.1uF

CE2220uF

CE2220uF

Fù11CùF-2012ES-121U/XFù11CùF-2012ES-121U/X

R65 0R65 0

TP2TP21

C41

0.1uF

C41

0.1uF

U8

SGTL5000XNAA3/R2

U8

SGTL5000XNAA3/R2

I2S_SCLK24

NC522

LINEIN_L14

CPFILT18

VDDIû

20

NC419

SüS_MCLK21

I2S_D÷UT25

I2S_DIN26

øP_L 6

CTRL_DATA27

NC628

CTRL_CLK29

GND1

1

NC18

øP_R 2

GND2

3

VDDA

5

LINE÷UT_L 12

LINE÷UT_R 11

MIC15

NC317

LINEIN_R13

AGND

7

I2S_LRCLK23

VDDD

30

CTRL_ADR0_CS

31

CTRL_M

û

DE

32

øP_VGND 4

NC29

VAG10

MIC_ùIAS16

GND3-PAD

G1

R64 2.2KR64 2.2K

C44 4.7uFC44 4.7uF

C43

4.7uF

C43

4.7uF

Figure 38: I2S Audio Codec implementation example


38

Appendix A. Carrier Board Reference

Schematics

The VIA QSMDB2 is the evaluation carrier board for QSM-8Q60 module. The schematics of QSMDB2

carrier board can be used as an example on how to design a carrier board that provides optimal

performance when used with VIA QSM-8Q60 module. The reference designs are only for referencing and

not to be copied.

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

15-24V DC IN

17

7

13

12

5

9

1

18

16

TITLE

10

4

15

19

14

HDMI_Redriver TMDS141RHAR

6

Block Diagram

8

QSMDB2

SHEET

F7511_GPIO_I2C1

3

20

2

11

Cover Sheet

VIA Confidential

RJ45 CON

mPCIe CONN,RST,POWER LED

LVDS

COM1,2,3

USB2,3

Audio SGTL5000

Q7 rev 2.0 CON , touch_C

USB to LAN_AX88772BLI

+12V,VCC5 , VCC3

USB-TO-COM XR21V1414

COM4/COM5_RS232/RS422/RS485

COM6/COM7_RS232/RS422/RS485

Title

Size Document Number Rev

Date: Sheet o f

VIA TECHNOLOGIES INC.

QSMDB2

COVER SHEET

1 18Thursday, March 02, 2017

ACustom

Title


Date: Sheet o f


QSMDB2

COVER SHEET


ACustom

Title


Date: Sheet o f


QSMDB2

COVER SHEET


ACustom

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USB TYPE AUSB PORT2,3

QSMDB2

15-24VOLTSDC-IN

SWITCHING REGULATORS

Q7_CONGBE_MD

I2C1 TOUCH CON

UART1,3,I2C3

USB1AX88772BLI

LVDSLVDS(D)

F7511

RedriverHDMI

SGTL5000 LINE-OUT

XR21V1414

LINE-IN,MIC-IN

AUD4

COM1,3,I2C3

COM2(TX/RX_debug)COM2

DB9

PIN HEADER_2X5

I2C1

Mini-PCIEPCIEx1

RJ45_GLAN

CR-2032 CON3V battery

VIA Confidential

RSTRESET

USB PORT4

USB0

5VVCC5

GPPIOX32RJ45_10/100M

COMX4

RS232/485/422

TMDS141RHARHDMI_CON

1*10 1.00mm CON CAN BUS

CAN1,CAN2

Title

Size Document Number R ev

Date: Sheet o f


QSMDB2

BLOCK DIAGRAM

2 18Friday, February 10, 2017

AC

Title


Date: Sheet o f


QSMDB2

BLOCK DIAGRAM


AC

Title


Date: Sheet o f


QSMDB2

BLOCK DIAGRAM


AC

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

HDMI

VIA Confidential

OVS TSCL/TSDA Output voltage select

I2CEN I2C Repeater enableLow: High-ZHigh: Active

OE TMDS Output enableLow: ActiveHigh: High-Z

PRE TMDS Output de-emphasis adjustmentLow: 0 dBHigh: 3.5 dB

NC, VOL is typically 0.5 VGND, VOL is typically 0.65 VVCC, VOL is typically 0.8 V

HDMI_TX0_PC

DP1TX1-

DP1TX0+

DP1TX0-

DP1TX1+

HDMI_TX2_NC

HDMI_TX1_NC

HDMI_TXC_PC

HDMI_TXC_NC

HDMI_TX2_PC

HDMI_TX0_NC

HDMI_TX1_PC

DP1TX2+

DP1TX3-

DP1TX2-

HDMI_DSDAHDMI_DSCL

HDMI_DDC_CLK_INHDMI_DDC_CLK_IN

DDI_CTRL_DATA HDMI_DDC_DAT_INHDMI_DDC_DAT_IN

HDMI_DSDA

HDMI_TX1_NC

HDMI_TXC_PC

HDMI_TXC_NC

HDMI_TX2_PC

HDMI_DSCL

HDMI_HPD

HDMI_TX0_NC

HDMI_TX0_PC

HDMI_TX2_NCHDMI_TX1_PC

HDMI_TX1_NC

HDMI_TX2_PCHDMI_TX2_NC

HDMI_TX1_PC

HDMI_DSDA

HDMI_DSCL

HDMI_HPDHDMI_DSDA

HDMI_CEC_INHDMI_DSCL

HDMI_HPD

HDMI_TXC_PCHDMI_TXC_NC


HDMI_TX1_NC

HDMI_TX2_PCHDMI_TX2_NC

HDMI_TX1_PC

HDMI_TXC_PCHDMI_TXC_NC


HDMI_CEC_IN

HDMI_+5V

HDMI_CEC_IN

HDMI_D2P

HDMI_D1P

HDMI_CLKP

HDMI_D2M

PRE

DDI_CTRL_DATA

OVS

DP1TX0+

HDMI_D1M

DP1TX0-

DP1TX1+

HDMI_D0P

DP1TX1-

DP1TX2+HDMI_D0M DP1TX2-

DP1TX3+

VSADJ

HDMI_CLKM DP1TX3-

-OEB

DDI_CTRL_CLK

DDI_CTRL_CLK

DP1TX3+

HDMI_DDC_DAT_INHDMI_DDC_DAT_IN

HDMI_DDC_CLK_INHDMI_DDC_CLK_IN

HDMI_+5V

3P3V

3P3V

GND GND

HDMI_+5V

GND

+12V_VIN

5VIN

HDMI_+5V

3P3V

3P3V

3P3V

3P3V

3P3V

HDMI_D2P11HDMI_D2M11




HDMI_CEC_IN11

HDMI_HPD11

I2C2_SDA3,11

I2C2_SCL3,11

I2C2_SDA3,11

I2C2_SCL3,11

I2C2_SDA3,11I2C2_SCL3,11

Title


Date: Sheet o f


QSMDB2

HDMI


ACustom

Title


Date: Sheet o f


QSMDB2

HDMI


ACustom

Title


Date: Sheet o f


QSMDB2

HDMI


ACustom

C1600.01uF

U33

TMDS141RHAR

TX1#13

GN

D14

RX2#1

I2CEN5

VC

C11

VC

C27

VC

C24

RX22

OE#6

PRE7

TX29

TX2#10

GN

D20

TXC#19

GN

D3

RSDA28

VC

C4

TXC18

TSDA23TSCL22

GN

D8

GN

D21

OVS25

TX112

TX0#16TX015

VC

C17

GN

D26

RSCL29

VSADJ30

GN

D31

RXC33

RXC#32

VC

C34

RX036

RX0#35

GN

D37

RX139

RX1#38

VC

C40

G1

G1

D2

RClamp0544T.TCT/X

2

G1

34

1

56

78

R602 10K/X

C1610.01uF

C1560.01uF

D4

RClamp0544T.TCT/X

2

G1

34

1

56

78

C1620.01uF

C1570.01uF

R8 1.5K

R585 10K

D1

RClamp0544T.TCT/X

2

G1

34

1

56

78

L4ACM2012E-900-2P-T011 4

32

C1580.01uF

R7 1.5K

R11 0/X

C1590.01uF

C10.1uF

Q1

FDC6301N

G1

1

S2

2

G2

3D

24

S1

5

D1

6

L2ACM2012E-900-2P-T011 4

32

R588 4.3K_1%

R73 0/X

R1

0

R589 10K

R44 0/X

C21uF

R590 10K/X

PS1

SMD1206P150TFT

1 2

R4 0

R587 10K

R591 1.65K_1%/X

D3B320A-13-F/XA K

R6 0

R584 10K/X

Q2

SM2306NSAC-TRG

G

DS

R74 0/X

R24.7K

R1010K/X

L1ACM2012E-900-2P-T011 4

32

R70 0/X

R586 10K/X

L3ACM2012E-900-2P-T011 4

32

R5 0

HDMI1

51U19S-323N-A4-BD

123456789

10111213141516171819

G1

G2

G4

G3

FB1

QT2012RL600HC2ALF

R34.7K

R583 10K

R9 0

R592 1.65K_1%/X

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VIA Confidential

GPIO10GPIO11GPIO12

GPIO14GPIO15GPIO16GPIO17GPIO30GPIO31GPIO32GPIO33

GPIO1GPIO2GPIO3

GPIO13

GPIO0

CLKCS0-

GPIO7

GPIO27GPIO26GPIO25

GPIO23GPIO22GPIO21GPIO20GPIO37GPIO36GPIO35GPIO34

GPIO6GPIO5GPIO4

GPIO24

MISOLAD1LAD2

MOSIMOSI

GPIO0

GPIO10GPIO11GPIO12

GPIO14GPIO15GPIO16GPIO17

GPIO1GPIO2GPIO3

GPIO13

GPIO7


GPIO6GPIO5GPIO4

GPIO27

GPIO25GPIO26

GPIO24

GPIO37GPIO36GPIO35GPIO34GPIO30

GPIO31GPIO32GPIO33

MODE2_1MODE1_1

MODE2_2MODE1_2

MODE2_3MODE1_3

MODE2_4MODE1_4


MODE1_1

MODE2_2

MODE2_1MODE1_2

GPIO47

GPIO45GPIO44

GPIO46MODE1_3

MODE2_4

MODE2_3MODE1_4

CLK

MOSIMISO

CS0-

MODE2_1MODE1_1

MODE2_2MODE1_2

MODE2_3MODE1_3

MODE2_4MODE1_4

3P3V

3P3V

3P3V

3P3V

3P3V

3P3V

I2C1_SCLI2C1_SDA

CSPI3_CS0

CSPI3_CLK

CSPI3_MOSICSPI3_MISO

Title


Date: Sheet o f


QSMDB2

F7511_GPIO


AA

Title


Date: Sheet o f


QSMDB2

F7511_GPIO


AA

Title


Date: Sheet o f


QSMDB2

F7511_GPIO


AA

U1

F75113U

LAD0/SPI_MISO1

LAD12

LAD23

LAD3/GPIO474

SERIRO/GPIO465

GPIO456

GPIO447

VDD8

GPIO27/LED279

GPIO26/LED2610

GPIO25/LED2511

GPIO24/LED2412

GPIO23/LED2313

GPIO22/LED2214

GPIO21/LED2115

GPIO20/LED2016

GPIO3717

GPIO3618

GPIO3519

GPIO3420

GPIO07/LED07/SMI/RSTOUT221




GPIO03/LED03/SMI/RSTOUT125GPIO02/LED02/SMI/RSTOUT126GPIO01/LED01/SMI/RSTOUT127GPIO00/LED00/SMI/RSTOUT128GPIO3329GPIO3230GPIO3131GPIO3032GPIO17/LED1733GPIO16/LED1634GPIO15/LED1535GPIO14/LED1436GPIO13/LED1337GPIO12/LED1238GPIO11/LED1139GPIO10/LED1040VSS41GPIO4342GPIO4243GPIO4144GPIO4045LCLK/SMBCLK/SPI_CLK46LFRAME#/SMBDATA/SPI_CS#47LRESET#/SPI_MOSI48

RN20 10K12345678

R162 0R148 0

RN18 10K12345678

RN11 10K1 23 45 67 8

R605 10K

R164 0

R603 10K

R159 0/X

GPIO

222-97-20GBB2

13 4

2

5 67 89

111012

13 141615

17 1819

22242628303234

21232527293133

36384039

3735

R1650

R160 0/X

R1660

R1670

C1650.1uF

RN19 10K12345678

R1680

R606 10K

RN13 10K1 23 45 67 8

RN14 10K1 23 45 67 8

R604 10K

RN17 10K12345678

RN15 10K1 23 45 67 8

RN12 10K1 23 45 67 8

R149 0/X

R161 0

R158 0/X

R163 0

R147 0

RN16 10K12345678

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

LVDS**

IVDD_ 2A= 80mils

VIA Confidential

PDD_ 2A= 80mils

LVDS0_EDID_SCLLVDS0_EDID_SDA

PVDD


LVDS0_TX2_NC



LVDS0_CLK_PCLVDS0_CLK_NC

LVDS0_TX2_PC






IVDD PVDD_PWR

IVDD





















BLT_EN

3P3V

3P3V

3P3V

3P3V

5VIN

5VIN5VIN

+12V_VIN

PVDD

5VIN

PVDD_PWR

I2C3_SDA7,8,10,11I2C3_SCL7,8,10,11

LVDS_PPEN11

LVDS_PWM211LVDS_BLEN11











PWM_OUT111

Title


Date: Sheet o f


QSMDB2

LVDS


AB

Title


Date: Sheet o f


QSMDB2

LVDS


AB

Title


Date: Sheet o f


QSMDB2

LVDS


AB

R27220_1%/X

RN6 0

1 23 4

R26374K_1%

J1(1-3)

MINI-JUMPER

C60.1uF

R14100_1%/X

R22

4.7K

RN7 0

1 23 4

R24 0

C822uF

R2833

RN2 01 23 4

FB2CBF-2012ES-121U/X

C70.1uF

RN5 01 23 4

R16 100_1%/X

C410uF

RN1 01 23 4

R17100_1%/X

R33 4.7K

LVDS1

87209-4040-06

22

11

44

33

66

55

88

77

1010

99

1212

1111

1414

1313

1616

1515

1818

1717

2020

1919

2222

2121

2424

2323

2626

2525

2828

2727

3030

2929

3232

3131

3434

3333

3636

3535

3838

3737

4040

3939

G1

G1

G2

G2

M1

M1

M2

M2

R30 140K_1%

R19100_1%/X

R23 100_1%/X

J1(2-4)

MINI-JUMPER

FB3CBF-2012ES-121U

C100.1uF

FB4

QT2012RL600HC2ALF

R31 0

RN3 01 23 4

J1

2208SM-06G-CP

13 4

2

5 6

RN4 01 23 4

C90.1uF/X

Q3

Si3443CDV-T1-GE3

1234 5 6

R13 100_1%/X

R29 0

C50.1uF

R18 100_1%/X

R32 0/X

RN8 0

1 23 4

R214.7K

C30.1uF

FB5

R20 100_1%/XRN9 0

1 23 4

C110.1uF

R25 0

R3433K_1%

C1210uF

Q4

NX7002AK

1

32

INVERTER1

85205-0800N

11

22

33

44

55

66

88 77

G1G1

G2G2

R12100_1%/X

R15100_1%/X

RN10 0

1 23 4

Q5

NX7002AK

1

32

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RJ45

VIA Confidential

LAN1_TD2+LAN1_TD2-

LAN1_TD3-LAN1_TD3+

LAN1_TD0-LAN1_TD0+

LAN1_TD1-LAN1_TD1+

LAN1_TD2+LAN1_TD2-

LAN1_TD3-LAN1_TD3+

LAN1_TD0-LAN1_TD0+

LAN1_TD1-LAN1_TD1+

LAN1_TD2+LAN1_TD2-

LAN1_TD3-LAN1_TD3+

LAN1_TD0-LAN1_TD0+

LAN1_TD1-LAN1_TD1+

3P3V

3P3V

3P3V

TXRXP_D 11TXRXM_D 11

TXRXP_B 11TXRXM_B 11TXRXP_C 11TXRXM_C 11

TXRXP_A 11TXRXM_A 11

LED1_ACT- 11

LED2_LINK- 11

Title


Date: Sheet o f


QSMDB2

RJ-45


AA

Title


Date: Sheet o f


QSMDB2

RJ-45


AA

Title


Date: Sheet o f


QSMDB2

RJ-45


AA

R37 330

R35 0/X

D5

RClamp0544T.TCT

2

G1

34

1

56

78

D6

RClamp0544T.TCT

2

G1

34

1

56

78

R36 330C13 0.1uF

C168 0.1uF

1:1

YELLOW

GREEN

75ohm1:1

2kV 1000pF

RJ45_PIN2RJ45_PIN1

75ohm

RJ45_PIN7

RJ45_PIN4 1:1

RJ45_PIN3

75ohm

RJ45_PIN5

ORANGE

RJ45_PIN8

RJ45_PIN6

1:175ohm

LAN1

RT7-164ATAMA

R6R10R9R8R7R4R3R2R1R5

L1L2

L4L3

G1

G2

M1

M2

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

Layout: 85 Ohm differential pairs

Mini-PCIE

Place near CON

VIA Confidential

Support half-size card Support full-size card

Mini_PCIe Socket

Top View

B_NUT_N0204525A-B

T_NUT_071CAAAZ68B

PCIe_CLKP

PCIe_RXP

PCIe_TXMPCIe_TXP

PCIe_SMB_CLKPCIe_SMB_DATA

PCIE_USB_DMPCIE_USB_DP

PCIe_CLKM

LED_WLAN_BLED_WPAN_B

PCIe_RXM

LED_WLANLED_WPAN

LED_WWANLED_WWAN_B

P_LED

USIM_DATAUSIM_CLKUSIM_RST

USIM_DATAUSIM_CLK

USIM_RST

GNDGND

GNDGNDGND GND GND

GND

3P3V MPCIE_3V3VCC15

GND

GND

3P3V

3P3V3P3V

3P3V

USIM_VCC

USIM_VCC

GND GND

USIM_VCC

VCC153P3V

3P3V

PCIE_WAKE_B11

PCIE_RST_B 11

I2C3_SDA 5,8,10,11I2C3_SCL 5,8,10,11

GPIO_19_PLED11


PCIe_CRXM11PCIe_CRXP11


RESET_N11

USBD_T4+ 11

USBD_T4- 11

Title


Date: Sheet o f


QSMDB2



ACustom

Title


Date: Sheet o f


QSMDB2



ACustom

Title


Date: Sheet o f


QSMDB2



ACustom

R46 0

C1610uF

R57 0

U5AME8818AEET150Z

V_INI

GN

DG

V_OUTO

R45 0

R4949.9_1%

C150.1uF

R59 330

SIM1

7111S2015X02LF

VCCC1

RSTC2

CLKC3

GNDC5

VPPC6

I/OC7

FB14CBF-2012ES-121U

R54330

R51 330R52 330

R581M_1%

LED2A

L-7104EB/1G1YD-TW

12

C2010uF

R554.7K

U2

N0204525A-B1

C291uF

MINICARD CONN

MINIPCIE1

0710A0BA68B

+3.3V52GND50+1.5V48LED_WPAN#46LED_WLAN#44LED_WWAN#42GND40USB_D+38USB_D-36GND34SMB_DATA32SMB_CLK30+1.5V28GND26+3.3VAUX24PERST#22Reserved20GND18

UIM_VPP16UIM_RESET14UIM_CLK12UIM_DATA10UIM_PWR8+1.5V6GND4+3.3V2

-WAKE1

Reserved51 Reserved49 Reserved47 Reserved45 Reserved43 Reserved41 Reserved39 Reserved37 GND35 PETp033 PETn031 GND29 GND27 PERp025 PERn023 GND21 Reserved(UIM_C4)19 Reserved(UIM_C8)17

GND15 REFCLK+13 REFCLK-11 GND9 CLKREQ#7 Reserved5 Reserved3

G1

G2

M1

M2

Q6

NX7002AK

1

32

C27 0.1uF

LED2B

L-7104EB/1G1YD-TW

34

TP_VCC15

1

R56 330

R53 100K

C301uF

C230.1uF

C28 0.1uF

C224.7uF

R43 0

C170.1uF

R50 330

R41 0

R3910K

L5

ACM2012E-900-2P-T00

1 4

32

D7BAT54AT-7-F

3

1

2

R4849.9_1%

R40 0

C2433pF

C1410uF

U3

071CAAAZ68B1

C2110uF

C2533pF

U4

SN74LVC1G08DBVR

12

43

5

C1910uF

R47 0

R42 0/X

C2633pF

RST1

DTSA-63N-V

4

21

3

C180.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A AVIA Confidential

COM_TXD3

COM_RXD2

COM_TXD2

COM_RXD3

COM_RXD1

COM_TXD1

COM_RXD2

COM_TXD2

COM_TXD1COM_RXD3COM_RXD1COM_TXD3

UART3_RX

UART2_TXUART1_TX

UART3_TX

UART2_RXUART1_RX

COM_TXD1

COM_RXD2

COM_TXD2

COM_RXD3

COM_RXD1COM_TXD3

5VIN

5VIN

UART3_RX11UART2_RX11UART1_RX11

UART3_TX11UART2_TX11UART1_TX11

I2C3_SDA 5,7,10,11I2C3_SCL 5,7,10,11

Title


Date: Sheet o f


QSMDB2

COM1,2,3,CAN1,2


AB

Title


Date: Sheet o f


QSMDB2

COM1,2,3,CAN1,2


AB

Title


Date: Sheet o f


QSMDB2

COM1,2,3,CAN1,2


AB

R265 0/X

C34 0.1uF

R266 0/X

C320.1uF

C31 0.1uF COM2

DT10121-M5W3-4F

162738495

G1

G2

C350.1uF

CN1220pF

12

34

56

78

CN2220pF

12

34

56

78

R261 0/X

U6 MAX3243EIDBR

V-3

VC

C26

FORCEOFF#22

C1+28

V+27

C1-24

C2+1

C2-2

FORCEON23

GND25

TOUT19

TOUT210

TOUT311

RIN14

RIN25

RIN36

RIN47

RIN58

TIN114

TIN213

TIN312

ROUT119

ROUT218

ROUT317

ROUT416

ROUT515

ROUTB220

INVLD#21

R262 0/XR263 0/X COM1_3

2208SM-10G-E9-BK-CR

13 4

2

5 67

108

R264 0/X

C33 0.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

USBDN_DP2

USBDN_DM2

USBDN_DM3USBDN_DP3

USBDN_DP3

USBDN_DM3

USBDN_DM3USBDN_DP3

USBDN_DP3USBDN_DM3

USBDN_DP2USBDN_DM2

USBDN_DP2USBDN_DM2

USBDN_DP2USBDN_DM2

5VIN3P3V3P3V

USB_2_3_VBUS

USB_2_3_VBUS

3P3V

USBD_T2+11

USBD_T2-11

USBD_T3+11

USBD_T3-11

USB_0_2_3_4_EN11USB_2_3_OC11

Title


Date: Sheet o f


QSMDB2

USB0,2,3,USBOTG


AB

Title


Date: Sheet o f


QSMDB2

USB0,2,3,USBOTG


AB

Title


Date: Sheet o f


QSMDB2

USB0,2,3,USBOTG


AB

C360.1uF

R6110K

R6310K/X

CE1100uF

L7

ACM2012E-900-2P-T00

1 4

32

R6010K

U7

MIC2026-2YM

EN_A1

OC_A2

OC_B3

EN_B4

OUT_B5GND6IN7OUT_A8

D8 RClamp0544T.TCT

2G

1

34

1

56

78

FB6

CBF-2012ES-121U

C380.1uF

C390.1uF

L6

ACM2012E-900-2P-T00

1 4

32

R6210K

USB_0/1

UB1112C-8FDE-4F

U1U2U3U4

U5U6U7U8

G1 G3

G2 G4

C370.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A AVIA Confidential

LINEOUT_LLINEIN_L

LINEIN_R

AUDIO_CLK

LINEOUT_R

LINE_IN_L

LINE_IN_R

HP_R HEAD_RIGHT

HEAD_LEFTLINE_IN_R LINE_IN_L

HEAD_RIGHT HEAD_LEFT

MIC_IN MIC_IN

CODEC_I2C_DAT

CODEC_I2C_CLK

MICBIAS

MIC_IN

VDDD

GND_ANALOG

GND_ANALOG GND_ANALOG

3P3V

3P3V

VCC15

AUD4_TXD11

AUD4_RXD11

AUD4_TXC11

AUD4_TXFS11

I2C3_SDA5,7,8,11

I2C3_SCL5,7,8,11

GPIO_0_CLKO11

Title


Date: Sheet o f


QSMDB2

Audio SGTL5000


AB

Title


Date: Sheet o f


QSMDB2

Audio SGTL5000


AB

Title


Date: Sheet o f


QSMDB2

Audio SGTL5000


AB

C400.1uF

R67 22

TP31

C47 1uF

C46 0.1uF

C420.1uF

TP1

1

AUDIO1

1600S-08-SM-TR

13 4

2

5 68109

R68 0

FB7QT1608RL060HC3A-LF

R66 0

TP41

CE3220uF

C49 0.1uF

C45 4.7uF

C48 0.1uF

CE2220uF

FB11CBF-2012ES-121U/X

TP21

R65 0

C41

0.1uF

U8

SGTL5000XNAA3/R2

I2S_SCLK24

NC522

LINEIN_L14

CPFILT18

VD

DIO

20

NC419

SYS_MCLK21

I2S_DOUT25

I2S_DIN26

HP_L6

CTRL_DATA27

NC628

CTRL_CLK29

GN

D1

1

NC18

HP_R2

GN

D2

3

VD

DA

5

LINEOUT_L12

LINEOUT_R11

MIC15

NC317

LINEIN_R13

AG

ND

7

I2S_LRCLK23

VD

DD

30

CT

RL_

AD

R0_

CS

31

CT

RL_

MO

DE

32

HP_VGND4

NC29

VAG10

MIC_BIAS16G

ND

3-P

AD

G1

R64 2.2K

C44 4.7uF

C434.7uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

VIA Confidential

UART2

UART3

PCB Footprint :7-AS0B326-S78N-7F

ADD G5 , G6 pin

99G26-05060L :BUTTON CELL BIN-CR2450W-J-CT-2PI-SL-PV-W-001 3V,550mAh,-40 ~+125

REV 2

CAN 2

GPIO6_IO11

USB_4_OC

GPIO_2

GPIO_2GPIO6_IO11

VDD_RTC_IN

5VIN5VIN

3P3V

5VIN

3P3V

HDMI_HPD3

LVDS_BLEN 5LVDS_PPEN5

LVDS_PWM25

CSPI3_CLK4

CSPI3_MOSI4CSPI3_MISO4

CSPI3_CS0 4

RESET_N 7

AUD4_RXD10AUD4_TXD10AUD4_TXC10

AUD4_TXFS10

LED1_ACT- 6LED2_LINK-6

PCIE_RST_B 7PCIE_WAKE_B 7


PCIe_CRXM 7PCIe_CRXP 7


USB_2_3_OC9

OTG_USBD_T1-12OTG_USBD_T1+12

USB_OTG_ID 12

USBD_T0+ 15


USBD_T3+9USBD_T3-9


USBD_T0- 15

I2C3_SDA 5,7,8,10I2C3_SCL 5,7,8,10

UART1_RX8

UART1_TX8

UART3_TX 8UART3_RX 8

GPIO_19_PLED 7

GPIO_0_CLKO10

TXRXP_D6TXRXM_D6

TXRXP_B6TXRXM_B6

TXRXP_C 6TXRXM_C 6

TXRXP_A 6TXRXM_A 6

I2C1_SDA4,11,15I2C1_SCL4,11,15

HDMI_D2P3HDMI_D2M3

HDMI_D1P3HDMI_D1M3

HDMI_D0P3HDMI_D0M3


I2C2_SDA 3I2C2_SCL 3

HDMI_CEC_IN 3




LVDS1_CLK_N 5LVDS1_CLK_P 5





USB_0_2_3_4_EN 9

UART2_RX 8UART2_TX 8



PWM_OUT1 5

GPIO6_IO1415

I2C1_SCL 4,11,15I2C1_SDA 4,11,15

I2C1_SDA 4,11,15I2C1_SCL 4,11,15

CAN_RX2 18CAN_TX2 18

CAN_RX1 18CAN_TX118

Title


Date: Sheet o f


QSMDB2

Q7_CON


AC

Title


Date: Sheet o f


QSMDB2

Q7_CON


AC

Title


Date: Sheet o f


QSMDB2

Q7_CON


AC

MH5

MTH6_3.5N

1234 5

678

9

MH2

MTH6_3.5N

1234 5

678

9

R179 0

FID3

FIDUCIAL

1

R81 0/X

C5010uF C53

0.1uF

R82 0/X

R6194.7K

TP_71

FID5

FIDUCIAL

1

MH4

MTH6_3.5N

1234 5

678

9

TP_51

R80 0

FID6

FIDUCIAL

1

R6204.7K

C1640.1uF

TP_111

FID4

FIDUCIAL

1

R79 0

MH3

MTH6_3.5N

1234 5

678

9

J3

85204-0200L

12

G1

G2

TP_11

MH1

MTH6_3.5N

1234 5

678

9

C5410uF

FID2

FIDUCIAL

1

TP_41

R87 0

C5147uF

C5747uF

TP_61

R69 0

R85 0

TP_91

R77 0

C520.1uF

R75 0

R78 0/X

TP_13 1

C550.1uF

FID1

FIDUCIAL

1

R84 0

R71 0

C1310.1uF

TP_21

C1630.1uF

TP_31

R86 0

R76 0

C560.1uF

TP_81

R178 0

TP_101

R72 0

TOUCH_C1

85204-0700L

12

G1

G2

34567

R83 0

Machenical KEY

J2

AS0B326-S78N-7F

GND1

GBE_MDI3-3

GBE_MDI3+5

GBE_LINK100-7

GBE_MDI1-9

GBE_MDI1+11

GBE_LINK#13

GBE_CTREF15

WAKE-17

SUS_STAT-19

SLP_BTN-21

GND23

GND25

BATLOW-27

SATA0_TX+29

SATA0_TX-31

SATA_ACT-33

SATA0_RX+35

SATA0_RX-37

GND39

BIOS_DISABLE-/BOOT_ALT-41

SDIO_CD-43

SDIO_CMD45

SDIO_PWR-47

SDIO_DATA049

SDIO_DATA251

SDIO_DATA453

SDIO_DATA655

GND57

HDA_SYNC/I2S_WS59

HDA_RST#/I2S_RST#61

HDA_BITCLK/I2S_CLK63

HDA_SDI/I2S_SDI65

HDA_SDO/I2S_SDO67

THRM-69

THRMTRIP-71

GND73



USB_6_7_OC-79



USB_2_3_OC#85

USB_P3-87

USB_P3+89

USB_CC91

USB_P1-93

USB_P1+95

GND97







LVDS_PPEN111



GND117

eDP0_AUX+/LVDS_A_CLK+119

eDP0_AUX-/LVDS_A_CLK-121

LVDS_BLT_CTRL/GP_PWM_OUT0123

GP2_I2C_DAT/LVDS_DID_DAT125

GP2_I2C_CLK/LVDS_DID_CLK127

CAN0_TX129

DP_LANE3+/TMDS_CLK+131

DP_LANE3-/TMDS_CLK-133

GND135



GND141



GND147



DP_HDMI_HPD#153

PCIE_CLK_REF+155

PCIE_CLK_REF-157

GND159

PCIE3_TX+161

PCIE3_TX-163

GND165

PCIE2_TX+167

PCIE2_TX-169

UART0_TX171

PCIE1_TX+173

PCIE1_TX-175

UART0_RX177

PCIE0_TX+179

PCIE0_TX-181

GND183

LPC_AD0/GPIO0185

LPC_AD2/GPIO2187

LPC_CLK/GPIO4189

SERIRQ/GPIO6191

VCC_RTC193

FAN_TACHOIN/GP_TIMER_IN195

GND197

SPI_MOSI199

SPI_MISO201

SPI_SCK203

VCC_5V_SB205

MFG_NC0207

MFG_NC1209

VCC211

VCC213

VCC215

VCC217

VCC219

VCC221

VCC223

VCC225

VCC227

VCC229

GND2

GBE_MDI2-4

GBE_MDI2+6

GBE_LINK1000-8

GBE_MDI0-10

GBE_MDI0+12

GBE_ACT#14

SUS_S5#16

SUS_S3-18

PWRBTN-20

LID_BTN-22

GND24

PWGIN26

RSTBTN#28

SATA1_TX+30

SATA1_TX-32

GND34

SATA1_RX+36

SATA1_RX-38

GND40

SDIO_CLK-42

SDIO_LED44

SDIO_WP46

SDIO_DAT148

SDIO_DAT350

SDIO_DAT552

SDIO_DAT754

RSVD56

GND58

SMB_CLK/GP1_I2C_CLK60

SMB_DAT/GP1_I2C_DAT62

SMB_ALERT-64

GP0_I2C_CLK66

GP0_I2C_DAT68

WDTRIG-70

WDOUT72

GND74



USB_4_5_OC#80



USB_0_1_OC#86

USB_P2-88

USB_P2+90

USB_ID92

USB_P0-94

USB_P0+96

GND98







LVDS_BLEN112



GND118

eDP1_AUX+/LVDS_B_CLK+120

eDP1_AUX-/LVDS_B_CLK-122

GP_1-Wire_Bus124

eDP0_HPD#/LVDS_BLC_DAT126

eDP1_HPD#/LVDS_BLC_CLK128

CAN0_RX130


GND136

DP_AUX+138

DP_AUX-140

GND142



GND148

HDMI_CTRL_DAT150

HDMI_CTRL_CLK152

RSVD154

PCIE_WAKE#156

PCIE_RST#158

GND160

PCIE3_RX+162

PCIE3_RX-164

GND166

PCIE2_RX+168

PCIE2_RX-170

UART0_RTS-172

PCIE1_RX+174

PCIE1_RX-176

UART0_CTS-178

PCIE0_RX+180

PCIE0_RX-182

GND184

LPC_AD1/GPIO1186

LPC_AD3/GPIO3188

LPC_FRAME#/GPIO5190

LPC_LDRQ#/GPIO7192

SPKR/GP_PWM_OUT2194

FAN_PWM/GP_PWM_OUT1196

GND198

SPI_CS0#200

SPI_CS1#202

MFG_NC4204

VCC_5V_SB206

MFG_NC2208

MFG_NC3210

VCC212

VCC216

VCC218

VCC220

VCC222

VCC224

VCC226

VCC228

VCC230

VCC214


G1G1

G2G2

G3G3

G4G4

G5

G5

G6

G6

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RC : for option

EEPROM

0->100MHz1->10MHz

VIA Confidential

RXPRXN

TXPTXN

XTAL25MN

USBDM

USB_WAKE

EECLK/PWR_SEL

EECS

USBDP

EEDO/AUTOMDIX_EN

XTAL25MP

EECS

EEDO/AUTOMDIX_EN

EECLK/PWR_SEL

RXPRXN

TXNTXP

V_BUS

-USB_RST

USB_ACT

-SP100_3

ACT_3

TXNTXP

RXPRXN

RXN

TXPTXNRXP

-SP100_3

ACT_3

RXP

TXPTXN

RXN

AVCC3.3LAN33

VCC1.8AVCC1.8

VCC1.8

LAN33

LAN33

LAN33LAN33

LAN33

AVCC1.8

VCC1.8AVCC3.3

LAN33

LAN33

LAN33

3P3V

LAN33

LAN33

LAN33

LAN33

OTG_USBD_T1-11

OTG_USBD_T1+11

USB_OTG_ID11

Title


Date: Sheet o f


QSMDB2

USB to LAN_AX88772CLF

<OrgAddr1>


A

Title


Date: Sheet o f


QSMDB2


<OrgAddr1>


A

Title


Date: Sheet o f


QSMDB2


<OrgAddr1>


A

R92 0

TP81

C834.7uF

C850.1uF

C840.1uF

C880.1uF

R180

49.9_1%

C860.1uF

C694.7uF

C580.1uF

C670.1uF

R181

49.9_1%


TP6

1

C59 33pFU9

AX88772BLI

VC

C3A

36

VC

C3R

352

VC

C33

A_P

LL59

VC

C33

A_H

60

VC

C3I

O16

VC

C3I

O44

V18

F51

VC

C18

A1

VC

C18

A11

VC

C18

A_P

LL64

VC

CK

20

VC

CK

24

VC

CK

36

VC

CK

49

RXIP9RXIN10

TXOP12TXON13

MFB_7 / RXD028MFB_6 / RXD129MFB_5 / REF50M30

MFB_4 / TXD031MFB_3 / TXD132

MFB_2 / TXEN33

MFB_1 / CRSDV34

MFB_035

GPIO_225GPIO_126

GPIO_0 / PME27

XTL25P2

XTL25N3

EXTWAKEUP_N23

MFA_0 / MDC17

MFA_1 / MDIO18

MFA_2 / RMII_N19

MFA_3 / PHY_N21

SD7

RSET_BG5

EECK38

EECS39

EEDIO40

V_BUS50

DP56 DM57

GN

D18

A14

GN

D18

A8

GN

D18

A4

GN

D48

GN

D37

GN

D22

GN

D15

GN

D3R

353

GN

D33

A_P

LL54

GN

D33

A_H

55

RREF58

RESET_N45

TEST146

TEST047

TCLK_EN43

TCLK_042

TCLK_141

GN

D18

A_P

LL63

X261

X162

R97 309_1%/X

R182

49.9_1%

R104 22

R106 4.7K

C720.1uF

TP71

R183

49.9_1%

R9339K

R101 12.1K_1%

MFA_11

R91 0

C820.1uF

C610.1uF

C741uF

R105 22

R961M_1%

R102 12.1K_1%

R100100_1%

R950

C62 33pF

C970.1uF

C810.1uF

C874.7uF

C680.1uF

C630.1uF

R1034.7K

C10010uF

D9

RClamp0544T.TCT

2

G1

34

1

56

78

R169 0/X

C660.1uF

C1660.1uF

C603.3pF

R94 4.7K

C980.1uF

YG

LAN2RT7-113AT8KD

G1

G2

R1R2R3R4R5R6R7R8

L4 L3 L2 L1

C710.1uF

U10

AT93C66B-XHM-T

DI3

SK2

CS1

DO4

VCC8

GND5

ORG6

NC7

C770.1uF

C7622uF

C800.1uF

R99100_1%

C790.1uF

C700.1uF

R98 0

C644.7uF

C650.1uF


X1 25MHz

GND4

11

33

GND2

LED3 LT8AB3-54-URC3-TE-Z/X

L8

ACM2012E-900-2P-T00

1 4

32

TP51


C780.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A AVIA Confidential

3.3VImax=3A

AVIN

5V_VFB

AVIN

AVINPOK

POK

5V_VFB

5VIN

+12V_VIN

+12V_VIN

5VIN

5VIN

3P3V

A_GND

A_GND

A_GND

A_GND

A_GND

A_GND

A_GNDA_GND

A_GND

Title


Date: Sheet o f


QSMDB2

SYS POWER


AB

Title


Date: Sheet o f


QSMDB2

SYS POWER


AB

Title


Date: Sheet o f


QSMDB2

SYS POWER


AB

R120 10K/X

R11875K_1%

C90100uF

C1040.01uF

R114 0RES0805

R1164.99K_1%

C10122uF

C751uF

R119 100K

A G N D

U11

EN2342QI

NC11

NC22

NC33

NC44

NC55

NC66

NC77

NC88

NC99

NC1010

NC1111

NC1212

NC1313

NC1414

AVINO42PG43BTMP44VDDB45BGND46S_IN47S_OUT48

PO

K49

EN

AB

LE50

AV

IN51

AG

ND

52A

GN

D53

VF

B54

EA

OU

T55

VO

UT

24

NC

2525

NC

2626

PG

ND

32

PG

ND

33

PVIN38

PVIN36PVIN37

PVIN39PVIN40PVIN41

NC

1515

VO

UT

16

VO

UT

17

VO

UT

18

VO

UT

19

VO

UT

20

VO

UT

21

VO

UT

22

VO

UT

23

NC

(SW

)27

27

NC

(SW

)28

28

PG

ND

29

PG

ND

31P

GN

D30

PG

ND

34

PVIN35

SS

56R

CLX

57F

QA

DJ

58

PG

ND

G1

NC

5959

EN

_PB

60N

C(S

W)6

161

NC

(SW

)62

62N

C(S

W)6

363

NC

6464

NC

6565

NC

6666

NC

6767

NC

6868

R111 0/X

R636 0

R11745.3K_1%

R113560

C16710uF

R10868K_1%

TP_5VIN1

1

R637 0/X

TP_3P3V1

1

R1091.5K

R10710K_1%

C105560pF

C96100pF

R110 30K_1%

D10SMA6L5.0A

AK

R1124.75K_1%

R624 0 RES0805

C9422uF16V/X5R

C9347uF/XX5R

C890.068uF

C1031uF

R625 100K

C1020.1uF

C731uF

U12

RT8070ZSP

VIN4

PGOOD8

RT6

SS2GNDG1COMP1

LX5

EN3

FB7

R122 10K

C91 0.22uF

C990.1uF

R121 33K_1%

L9 WSRPG0402-2R2M-AG

R12323.7K_1%

R115255K_1%

C92 0.022uF

C9522uF16V/X5R

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VIA ConfidentialJDCIN

DC-IN

DC-IN

+12V_VIN

PGNDPGND

PGND

PGND

DC-IN

DC-IN

Title


Date: Sheet o f


QSMDB214 18Friday, February 10, 2017

AA

15-24V DC INTitle


Date: Sheet o f



AA

15-24V DC INTitle


Date: Sheet o f



AA

15-24V DC IN

R13522K /X

R128 2.2

C1072.2uF

DP1

SD103AW-TP

A K

L13 QT2012RL060HC6A-LFJ6

2317SJ-02-F4

12

C11815pF

C111 0.1uF

C12210uF

R1250

C12110pF50V

CE6270uF

C1090.47uF

D111SR154-400

AK

C1102.2uF

Q8AO4480

S1

1S

22

S3

3G

4D

45

D3

6

D2

7

D1

8C1230.47uF

C1191000pF

C108 1uF

C1124.7uF

Q7AO4480

S1

1S

22

S3

3G

4D

45

D3

6

D2

7

D1

8

C1141000pF/X

R131 3.3K_1%R13210K_1%

C1150.1uF

R1331

TP_12VIN1

1

R127 0

TP_DC-IN

1

R13622K /X

PS20451007.MRL7A

1 2

CE4220uF

R134715_1%

R129100K

L10 BCIHP0735-100M

C1200.1uF

C1160.1uF

R1261.65K_1%/X

C1134.7uF

CE7220uF

U13

MIC2101YML

VDD1

PVDD2

ILIM3

DL4

PGND5

FREQ6

DH7

SW8

NC9

BST10

NC11

AGND12

FB13

PG14

EN15

VIN16

EPG1

CE5270uF

C1174700pF

L11 QT2012RL060HC6A-LF

C1062.2uF

R13091K_1%

R1241

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

20121228

VIA Confidential

COM4

COM5

COM6

COM7

TXD1RXD1-RTS1-CTS1-DTR1-DSR1-DCD1-RI1




SDASCL

SDASCL

-SUSPEND

USBDN_DP0

USBDN_DM0

3P3V 3P3V 3P3V 3P3V

3P3V

3P3V

TXD1 16RXD1 16-RTS1 16

TXD2 16RXD2 16-RTS2 16-CTS2 16-DTR2 16-DSR2 16-DCD2 16

-RI2 16

-CTS1 16


-RI3 17


-RI4 17

-DTR1 16-DSR1 16-DCD1 16

-RI1 16

USBD_T0+11

USBD_T0-11

I2C1_SCL4,11I2C1_SDA4,11

GPIO6_IO1411

Title


Date: Sheet o f


QSMDB2 A

XR21V1414A


Title


Date: Sheet o f


QSMDB2 A

XR21V1414A


Title


Date: Sheet o f


QSMDB2 A

XR21V1414A


C12910uF

C130 0.1uF

R146 0/X

U15

AT24C02B-10TU-1.8/X

A01

A12

A23

GND4

SDA5SCL6WP7VCC8

C1250.1uF

C1240.1uF

L12

ACM2012E-900-2P-T00

1 4

32


R143 4.7K/X

U14

XR21V1414IM48TR-F

GND_11

LOWPOWER2

GPIOD2/DSRD#3

GND_44

VCC_55

GPIOA5/RTSA#6

GPIOA4/CTSA#7

TXB8

RXB9

GPIOB5/RTSB#10

GPIOB4/CTSB#11

GPIOB3/DTRB#12

GPIOB2/DSRB#13

GPIOB1/CDB#14

GPIOB0/RIB#15

GPIOA3/DTRA#16

GPIOA2/DSRA#17

VCC_1818

GND_1919

GPIOA1/CDA#20

GPIOA0/RIA#21

TXC22

RXC23

GPIOC5/RTSC#24

GPIOC4/CTSC#25

GPIOC3/DTRC#26

GPIOC2/DSRC#27

GPIOC1/CDC#28

GPIOC0/RIC#29

TXA30

RXA31

GND_3232

VCC_3333

GPIOD1/CDD#34

SDA35 SCL36

GPIOD0/RID#37

TXD38

RXD39

GND_4040

GND_4141

USBD_m42

USBD_p43

VCC_4444

VCC_4545

GPIOD5/RTSD#46

GPIOD4/CTSD#47

GPIOD3/DTRD#48

C12710uF

R1374.7K

R1424.7K/X

R144 0

R1394.7K/X

C12610uF

R145 0

C12810uF

R1414.7K/X

R1384.7K/X

R140 4.7K

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VIA Confidential

RS232/RS422/RS485select

*1MODE1_1

RS422RS232

RS485

SLEW10

00

MODE2_1

0 0 *

= 0-->250Kbps; 1-->1Mbps*

1 1 *0

RS232

RS422/485 = 0-->250Kbps; 1-->10Mbps*RS232

RS422/485 = 0-->250Kbps; 1-->10Mbps*= 0-->250Kbps; 1-->1Mbps*


0 0 *1

*1MODE1_2

RS422RS232

RS485

SLEW20

00

1

MODE2_2

*0

MODE1_1MODE1_1

-RTS1TXD1-DTR1-DSR1-RI1-CTS1

-DCD1 IC_DCD1RXD1

SLEW1SLEW1

MODE2_1MODE2_1 MODE2_2MODE2_2

MODE1_2


-DCD2

IC_TXD2IC_DTR2

RXD2

SLEW2SLEW2

IC_TXD1

COM_RI1IC_CTS1

COM_RI2IC_DSR2

IC_DCD2

IC_DSR1

IC_RXD1

IC_DTR1

IC_RTS1

IC_CTS2IC_RXD2

IC_RTS2

IC_DCD2

IC_DSR2IC_RTS2 IC_CTS2

COM_RI2

IC_RXD2IC_TXD2 IC_DTR2

IC_DCD1 IC_RXD1IC_DTR1

IC_RTS1

IC_TXD1IC_DSR1IC_CTS1

COM_RI1


-DCD2RXD2


-DCD1RXD1

IC_DSR1COM_RI1

IC_RXD1IC_CTS1

IC_DTR1

IC_RTS1IC_TXD1

IC_DCD1

IC_RTS2

COM_RI2

IC_TXD2IC_DTR2

IC_CTS2

IC_DSR2

IC_RXD2IC_DCD2

-RTS115TXD115-DTR115

-RI115-CTS115

-DCD115

-DSR115

RXD115

MODE2_14,17

MODE1_14,17

MODE2_24,17

MODE1_24,17

-RTS215TXD215-DTR215

-RI215-CTS215

-DCD215

-DSR215

RXD215

5VIN5VIN

5VIN 5VIN

Title


Date: Sheet o f


QSMDB2

COM1/COM2_RS232 / RS422 / RS485


ACustom

Title


Date: Sheet o f


QSMDB2

COM1/COM2_RS232 / RS422 / RS485


ACustom

Title


Date: Sheet o f


QSMDB2

COM1/COM2_RS232 / RS422 / RS485


ACustom

R255 0/X

R152 0

C141 0.1uF

R256 0/X

R245 0/X

R151 4.7K/X

C143 0.1uF

R153 4.7K/X

R257 0/X

U17

F81438G

V-14

VC

C5

MODE_223

C1+9

V+10

C1-12

C2+11

C2-13

MODE_12

GND8

T1_OUT7

T2_OUT17

T3_OUT18

R1_IN6

R2_IN15

R3_IN16

R4_IN4

R5_IN3

T1_IN1

T2_IN28

T3_IN27

R1_OUT26

R2_OUT19

R3_OUT20

R4_OUT21

R5_OUT22

SLEW25

SD24

R246 0/X

R258 0/X

C1341uF

R150 0

R247 0/X

C1421uF

R259 0/X

R248 0/X

CN6220pF

12

34

56

78

R260 0/X

R249 0/XR250 0/X

CN5220pF

12

34

56

78

COM513 4

2

5 67 89

R251 0/XR252 0/X

C137 0.1uFC1360.1uF

U16

F81438G

V-14

VC

C5

MODE_223

C1+9

V+10

C1-12

C2+11

C2-13

MODE_12

GND8

T1_OUT7

T2_OUT17

T3_OUT18

R1_IN6

R2_IN15

R3_IN16

R4_IN4

R5_IN3

T1_IN1

T2_IN28

T3_IN27

R1_OUT26

R2_OUT19

R3_OUT20

R4_OUT21

R5_OUT22

SLEW25

SD24

C133 0.1uF

R253 0/X

C139 0.1uF

C1380.1uF

R254 0/X

C1320.1uF

CN4220pF

12

34

56

78

COM413 4

2

5 67 89

CN3220pF

12

34

56

78

C1350.1uF

C140 0.1uF

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

VIA Confidential

0 0 *1

*1MODE1_3

RS422RS232

RS485

SLEW30

00

1

MODE2_3

*0

RS232



0 0 *1

*1MODE1_4

RS422RS232

RS485

SLEW40

00

1

MODE2_4

*0

RS232



RXD3

MODE2_3MODE2_3

MODE1_3

IC_RXD3IC_TXD3 IC_DTR3

SLEW3SLEW3

-DTR3-DSR3-RI3-CTS3

-DCD3 IC_DCD3

IC_RTS3COM_RI3

IC_DCD3

IC_TXD4

MODE2_4MODE2_4

MODE1_4

-DTR4-DSR4-RI4-CTS4

-DCD4

IC_TXD4IC_DTR4

IC_DCD4

IC_DSR4IC_RTS4

IC_DTR4IC_DCD4

SLEW4SLEW4

RXD4

IC_RXD4COM_RI3IC_CTS3

COM_RI4IC_DSR4

IC_TXD3

IC_DSR3

IC_RXD3

IC_DTR3

IC_RTS3

IC_CTS4IC_RXD4

IC_RTS4-RTS3TXD3 TXD4

-RTS4

IC_DSR3IC_CTS3

IC_CTS4COM_RI4

MODE2_3MODE2_3MODE1_3

MODE2_4MODE2_4MODE1_4

-RTS3TXD3

RXD3

-DTR3-DSR3-RI3-CTS3

-DCD3

IC_TXD3

IC_DSR3

IC_RXD3

IC_DTR3

COM_RI3IC_CTS3

IC_DCD3

IC_RTS3

-DTR4-DSR4-RI4-CTS4

-DCD4RXD4

TXD4-RTS4

IC_TXD4IC_DTR4

IC_DCD4

IC_RTS4

COM_RI4IC_DSR4

IC_CTS4IC_RXD4

RXD315

MODE2_34

MODE1_34

-DTR315

-RI315-CTS315

-DCD315

-DSR315

MODE2_44

MODE1_44

-DTR415

-RI415-CTS415

-DCD415

-DSR415

RXD415

TXD315-RTS315

TXD415-RTS415

MODE2_14,16MODE1_14,16

MODE2_24,16MODE1_24,16

5VIN 5VIN

5VIN 5VIN

Title


Date: Sheet o f


QSMDB2

COM3/COM4_RS232 / RS422 / RS485


ACustom

Title


Date: Sheet o f


QSMDB2

COM3/COM4_RS232 / RS422 / RS485


ACustom

Title


Date: Sheet o f


QSMDB2

COM3/COM4_RS232 / RS422 / RS485


ACustom

R156 0

R235 0/X

C1441uF

R236 0/X

C154 0.1uF

J8

2208SM-16G-BK-CR/X

13 4

2

5 67 89 10

11 1213 1415 16

R157 4.7K/X

R237 0/X

C1450.1uF

COM613 4

2

5 67 89

CN7220pF

12

34

56

78

R238 0/XR239 0/XR240 0/X

C149 0.1uF

CN9220pF

12

34

56

78

C146 0.1uF

C1480.1uF

R241 0/XR234 0/X

C152 0.1uF

COM713 4

2

5 67 89

C1471uF

R242 0/X

R154 0

R229 0/X

CN8220pF

12

34

56

78

R243 0/X

C1550.1uF

R230 0/X

R155 4.7K/X

C151 0.1uF

R244 0/X

R231 0/X

U19

F81438G

V-14

VC

C5

MODE_223

C1+9

V+10

C1-12

C2+11

C2-13

MODE_12

GND8

T1_OUT7

T2_OUT17

T3_OUT18

R1_IN6

R2_IN15

R3_IN16

R4_IN4

R5_IN3

T1_IN1

T2_IN28

T3_IN27

R1_OUT26

R2_OUT19

R3_OUT20

R4_OUT21

R5_OUT22

SLEW25

SD24

C153 0.1uF

R232 0/X

U18

F81438G

V-14

VC

C5

MODE_223

C1+9

V+10

C1-12

C2+11

C2-13

MODE_12

GND8

T1_OUT7

T2_OUT17

T3_OUT18

R1_IN6

R2_IN15

R3_IN16

R4_IN4

R5_IN3

T1_IN1

T2_IN28

T3_IN27

R1_OUT26

R2_OUT19

R3_OUT20

R4_OUT21

R5_OUT22

SLEW25

SD24

R233 0/X

CN10220pF

12

34

56

78

C1500.1uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CANH2CAN_TX2

CAN_RX-2

CAN_TX1

CAN_RX-1

CANH1

CANL1

CANH2

CANL2

CAN_RX1CAN_RX-1

CAN_RX2CAN_RX-2

CAN_RX2

CAN_TX2

CANH1

CANL1

CANH2

CANL2CAN_TX1

CAN_RX1

CANL2

3P3V

3P3V5VIN

3P3V

3P3V

5VIN

5VIN

5VIN

5VIN

5VIN

5VIN

CAN_RX211

CAN_TX211

CAN_RX111

CAN_TX111

Title


Date: Sheet o f


QSMDB2

CAN1,CAN2

<OrgAddr1>


AB

Title


Date: Sheet o f


QSMDB2

CAN1,CAN2

<OrgAddr1>


AB

Title


Date: Sheet o f


QSMDB2

CAN1,CAN2

<OrgAddr1>


AB

J9

2208SM-06G-CP

13 4

2

5 6

R612 0/X

R607 0/X

R611 0

R608 0

R6144.7K/X

R610 0/X

C198

0.1uF

U34

SN74LVC1T45DBVR

VCCA1

GND2A3

B4

DIR5

VCCB6

J9(2-4)

MINI-JUMPER

R609 0/X

FB13 BLM15PX121SN1D

C2100.1uF

U36

SN65HVD1050DR

TXD1

GND2

VCC3

RXD4

Vref5

CANL6

CANH7

S8

J9(1-3)

MINI-JUMPER

C195

0.1uF

R6154.7K

R617 120

CANBUS

87212-10G0

11

22

33

44

G1

G1

G2

G2

55

66

77

88

99

1010

R6164.7K

C1960.1uF

C1990.1uF

U35

SN74LVC1T45DBVR

VCCA1

GND2A3

B4

DIR5

VCCB6

C2000.1uF

U37

SN65HVD1050DR

TXD1

GND2

VCC3

RXD4

Vref5

CANL6

CANH7

S8

C1970.1uF

R6134.7K/X

R618 120

DESIGN GUIDE Carrier Board -...

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