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Design GoalDesign GoalDesign an Analog-to-Digital Conversion chip Design an Analog-to-Digital Conversion chip to meet demands of high quality voice to meet demands of high quality voice applications such as: Digital Telephony, applications such as: Digital Telephony, Digital Hearing Aids and VOIP.Digital Hearing Aids and VOIP.

TEAM W3:TEAM W3:Digital Voice Processor 525Digital Voice Processor 525

Jarrett Avery (W3-1)Jarrett Avery (W3-1)Sean Baker (W3-2)Sean Baker (W3-2) Huiyi Lim (W3-3)Huiyi Lim (W3-3)

Sherif Morcos (W3-4) Sherif Morcos (W3-4) Amar Sharma (W3-5)Amar Sharma (W3-5)

Date: 3/29/2006

Functional Blocks II and

Simulation

Design Manager: Abhishek Design Manager: Abhishek JajooJajoo

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StatusStatus Project chosen: 16 bit Delta-Sigma ADC - Basic specs Project chosen: 16 bit Delta-Sigma ADC - Basic specs

defineddefined ArchitectureArchitecture SchematicSchematic Floor PlanningFloor Planning

Revised Layout DimensionsRevised Layout Dimensions Layout ProgressLayout Progress

Top Level AnalogTop Level Analog Delta/Sigma Modulator Delta/Sigma Modulator Low Pass Filter – DRC, LVS, SimulatedLow Pass Filter – DRC, LVS, Simulated

Top Level DigitalTop Level Digital PII – DRC, LVS, SimulatedPII – DRC, LVS, Simulated Sinc Filter – DRC, LVS, SimulatedSinc Filter – DRC, LVS, Simulated Clock Divider – DRC, LVS, SimulatedClock Divider – DRC, LVS, Simulated

Simulation / VerificationSimulation / Verification All Digital Modules VerifiedAll Digital Modules Verified All Analog Modules VerifiedAll Analog Modules Verified Overall/Top VerifiedOverall/Top Verified

Optimized LayoutOptimized Layout Analog Components Analog Components PII Function – Started Basic OptimizationPII Function – Started Basic Optimization Sinc FilterSinc Filter

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Analog ProgressAnalog Progress

Delta/Sigma ModulatorDelta/Sigma Modulator Transistor Level Verified with BehavioralTransistor Level Verified with Behavioral Layouts and Extracted Views of the Layouts and Extracted Views of the

Operational Amplifiers Operational Amplifiers Integrator - Verified Integrator - Verified Comparator – VerifiedComparator – Verified

Completed DRC/LVS of ModuleCompleted DRC/LVS of Module Common Centriod and MisMatch AnalysisCommon Centriod and MisMatch Analysis

……Working on Analog Top Level Working on Analog Top Level LayoutLayout

……Begin Schematic/Layout VerificationBegin Schematic/Layout Verification ……Begin Optimizing Module LayoutBegin Optimizing Module Layout

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Delta/Sigma Modulator Delta/Sigma Modulator Transistor Level SimulationTransistor Level Simulation

Wave InputWave InputModulator Modulator OutputOutput

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Delta/Sigma Modulator Delta/Sigma Modulator Behavorial Level SimulationBehavorial Level Simulation

Wave InputWave Input

Modulator Modulator OutputOutput

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ΔΣΔΣ Modulator Transistor - Modulator Transistor - LayoutLayout

17 Analog Transistors17 Analog Transistors

Differential Op AmpDifferential Op Amp ComparatorComparator

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Common Centroid (CC)Common Centroid (CC)

Transistor Matching in Analog DesignTransistor Matching in Analog Design Concept – Want matched pairs of Concept – Want matched pairs of

transistorstransistors (Voltage Matched) Differential Pairs(Voltage Matched) Differential Pairs (Current Matched) Current Mirrors(Current Matched) Current Mirrors

Common Centroid LayoutCommon Centroid Layout Minimize effect of process gradients (ie Minimize effect of process gradients (ie

etching)etching) Layout style with common center pointLayout style with common center point Use of “fingers” method most commonUse of “fingers” method most common Can be used for Matched Can be used for Matched

Resistors/CapacitorsResistors/Capacitors

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Common Centroid RulesCommon Centroid Rules

Coincidence : Centroids of matched devices should Coincidence : Centroids of matched devices should coincidecoincide

Symmetry : Symmetry should arise from the placement of Symmetry : Symmetry should arise from the placement of segments in the array around both the X and Y-axessegments in the array around both the X and Y-axes

Dispersion : Segments of each device should be Dispersion : Segments of each device should be distributed throughout the array in a uniform mannerdistributed throughout the array in a uniform manner

Compactness : Array should be as compact as possible Compactness : Array should be as compact as possible and should be nearly squareand should be nearly square

Orientation : Each matched device should consist of an Orientation : Each matched device should consist of an equal number of segments oriented in either directionequal number of segments oriented in either direction

(Source: The Art of Analog Layout by Alan Hastings)(Source: The Art of Analog Layout by Alan Hastings)

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Effects of Mismatch on Effects of Mismatch on ΔΣΔΣ

Matched RC and Diff Pair TransistorsMatched RC and Diff Pair Transistors Increased 10% Diff Pair SizeIncreased 10% Diff Pair Size

Decreased 10% Diff Pair SizeDecreased 10% Diff Pair Size Only 10% RC MismatchOnly 10% RC Mismatch

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Comparator - LayoutComparator - Layout

LL RR

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Sample CC Comparator Sample CC Comparator - Layout- Layout

R L L RR L L R

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Digital ProgressDigital Progress Decimator ModulesDecimator Modules

PII Function - Transistor Level and Layout PII Function - Transistor Level and Layout Verified & LVSVerified & LVS

Sinc Filter – Transistor Level and Layout Verified Sinc Filter – Transistor Level and Layout Verified & LVS& LVS

Analysis - Power ConsumptionAnalysis - Power Consumption Decimator Global RoutingDecimator Global Routing

Wired PII, Sinc Filter, and Clock DividerWired PII, Sinc Filter, and Clock Divider LVS/DRC of the Decimator LayoutLVS/DRC of the Decimator Layout

……Decimator to be SimulatedDecimator to be Simulated ……Some OptimizationSome Optimization

Minimize Component (And/Or/Adder) LayoutsMinimize Component (And/Or/Adder) Layouts Add additional contactsAdd additional contacts Connect Nwells, Bigger-Better Vdd, Gnd LinesConnect Nwells, Bigger-Better Vdd, Gnd Lines Plan Vdd and Gnd Source Grids for Current Plan Vdd and Gnd Source Grids for Current

DistributionDistribution Create Gnd Isolation RingsCreate Gnd Isolation Rings

……Continue to Optimize PII and SincContinue to Optimize PII and Sinc

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Sinc Filter - LayoutSinc Filter - Layout

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Sinc Filter Zoom - Sinc Filter Zoom - LayoutLayout

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Sinc (Schematic vs Sinc (Schematic vs Layout)Layout)

Schematic Simulation Schematic Simulation Layout Simulation Layout Simulation

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PII Function - LayoutPII Function - Layout

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PII Zoom - Layout PII Zoom - Layout

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PII (Schematic vs PII (Schematic vs Layout)Layout)

Schematic Simulation Schematic Simulation Layout Simulation Layout Simulation

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Decimator – LayoutDecimator – Layout

Sinc2 FilterSinc2 Filter

PII FunctionPII Function256 Clock Divider256 Clock Divider

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Preliminary Top Level - Preliminary Top Level - LayoutLayout

Min/Max/Out Min/Max/Out

Wait Period Wait Period

Low Pass Low Pass

1-Bit Stream 1-Bit Stream

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Old FloorplanOld Floorplan

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Updated FloorplanUpdated Floorplan

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Layout Power/TimingLayout Power/Timing

Module Power Area T-Count

Clock Divider 4.812uW 1,740um^2 334

2nd Order Sinc Filter 227.1uW 17,967um^2 3296

PII Function 115.9uW 17,955um^2 2782

Decimator (Top Digital) 347.8uW (Estimate) 45,474um^2 6412

Analog Op-Amps/Modulator

~162uW (Op Amp Power)

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Low Pass Filter Max ~ 327.6uW 59,899um^2 0

Modulator (Top Analog) Max ~ 837.4uW ~137,764um^2 6,432

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Problems and QuestionsProblems and Questions

Isolation RingsIsolation Rings How Thick?How Thick? Around Analog Modulator?Around Analog Modulator? Around Decimator?Around Decimator?

Current Distribution Issues?Current Distribution Issues?

Any Comments or Suggestions?Any Comments or Suggestions?