Design GoalDesign GoalDesign an Analog-to-Digital Conversion chip Design an Analog-to-Digital Conversion chip to meet demands of high quality voice to meet demands of high quality voice applications such as: Digital Telephony, applications such as: Digital Telephony, Digital Hearing Aids and VOIP.Digital Hearing Aids and VOIP.

TEAM W3:TEAM W3:Digital Voice Processor 525Digital Voice Processor 525

Jarrett Avery (W3-1)Jarrett Avery (W3-1)Sean Baker (W3-2)Sean Baker (W3-2) Huiyi Lim (W3-3)Huiyi Lim (W3-3)

Sherif Morcos (W3-4)Sherif Morcos (W3-4) Amar Sharma (W3-5)Amar Sharma (W3-5)

Date: 2/8/2006

Size Estimates/ Floorplan

Design Manager: Abhishek Design Manager: Abhishek JajooJajoo

StatusStatus Design ProposalDesign Proposal

Project chosen: 16 bit Delta-Sigma ADCProject chosen: 16 bit Delta-Sigma ADC Basic specs definedBasic specs defined

ArchitectureArchitecture Matlab SimulatedMatlab Simulated Behavioral Verilog SimulatedBehavioral Verilog Simulated Structural Verilog – Done, but not simulatedStructural Verilog – Done, but not simulated

SchematicSchematic Analog components created & simulated with digital Analog components created & simulated with digital

behavioral Verilog modelsbehavioral Verilog models

FloorplanFloorplan Initial floorplan created based on estimates of component Initial floorplan created based on estimates of component

areasareas

LayoutLayout Simulation / VerificationSimulation / Verification

In Case You Forgot…In Case You Forgot…(A Summary of Last Week)(A Summary of Last Week)

Applications of the DVP-525Applications of the DVP-525 VoIP, Digital Telephony, Encrypted VoIP, Digital Telephony, Encrypted

CommunicationsCommunications Digital Hearing AidsDigital Hearing Aids

How the DVP-525 works:How the DVP-525 works: Uses Delta-Sigma modulation of Uses Delta-Sigma modulation of

input signal and decimation to input signal and decimation to convert an analog signal into 16 convert an analog signal into 16 bit binary numbersbit binary numbers

Algorithm DetailAlgorithm Detail

Decimation (Sinc Filter,

Downsample)

Measure PeakAmplitude

(Peak Input Indicator)

DigitalOutput

DigitalPeakIndicator

AnalogInput Lowpass Filter

Analog to DigitalConversion

(Delta-SigmaModulator)

Hardware That Makes it Hardware That Makes it HappenHappen

(Modulator)(Modulator)Integrators

Comparator

Modulator SchematicModulator Schematic

Algorithm DetailAlgorithm Detail

Decimation (Sinc Filter,

Downsample)

Measure PeakAmplitude

(Peak Input Indicator)

DigitalOutput

DigitalPeakIndicator

AnalogInput Lowpass Filter

Analog to DigitalConversion

(Delta-SigmaModulator)

Hardware That Makes it Hardware That Makes it HappenHappen

(Decimator)(Decimator)

Sinc Filter Behavioral Sinc Filter Behavioral VerilogVerilog

Sinc Filter Structural Sinc Filter Structural VerilogVerilog

Algorithm DetailAlgorithm Detail

Decimation (Sinc Filter,

Downsample)

Measure PeakAmplitude

(Peak Input Indicator)

DigitalOutput

DigitalPeakIndicator

AnalogInput Lowpass Filter

Analog to DigitalConversion

(Delta-SigmaModulator)

Hardware That Makes it Hardware That Makes it HappenHappen

(Peak Input Indicator)(Peak Input Indicator)

PII Function Behavioral PII Function Behavioral VerilogVerilog

PII Function Structural PII Function Structural VerilogVerilog

Clock DividerClock Divider New component added to digital portion of New component added to digital portion of

designdesign Takes as input the oversampled clock and Takes as input the oversampled clock and

outputs the Nyquist clockoutputs the Nyquist clock We are using an oversampling factor of 256We are using an oversampling factor of 256

So, need to divide oversampled clock by 256So, need to divide oversampled clock by 256 Implemented with a 7-bit counter and a T Implemented with a 7-bit counter and a T

(toggle) flip-flop(toggle) flip-flop Every time counter overflows (reaches 128), Every time counter overflows (reaches 128),

flip-flop toggles (Cout connected to flip-flop’s flip-flop toggles (Cout connected to flip-flop’s clock)clock)

This produces a clock with 1/256 the input This produces a clock with 1/256 the input frequencyfrequency

Hardware That Makes it Hardware That Makes it HappenHappen

(Clock Divider)(Clock Divider)

Clock DividerClock Divider Behavioral Behavioral VerilogVerilog

Clock Divider Structural Clock Divider Structural VerilogVerilog

Simulation – MatLabSimulation – MatLab

First modeled the modulator in First modeled the modulator in the time domain, and fed it the time domain, and fed it simple sine wave input:simple sine wave input:

Simulation – MatLab Simulation – MatLab (cont’d)(cont’d)

Then fed the bitstream created Then fed the bitstream created by the modulator into the by the modulator into the decimator:decimator:

Simulation (cont’d)Simulation (cont’d)

Now, we have simulated entire Now, we have simulated entire design in a mixed-signal design in a mixed-signal environmentenvironment

Analog portion represented by Analog portion represented by generic componentsgeneric components

Digital portion represented by Digital portion represented by behavioral Verilog codebehavioral Verilog code

Simulated together in Cadence Simulated together in Cadence using AHDLusing AHDL

Simulation – CadenceSimulation – Cadence

Simulation (cont’d)Simulation (cont’d)

Simulated behavioral models of Simulated behavioral models of PII function & clock divider in PII function & clock divider in ModelSimModelSim

Verified generation of Nyquist Verified generation of Nyquist clock by clock divider moduleclock by clock divider module

Verified updates of maximum & Verified updates of maximum & minimum values of sinc filter minimum values of sinc filter output by PII function moduleoutput by PII function module

Simulation – ModelSimSimulation – ModelSim

Transistor Count Transistor Count EstimatesEstimates

AnalogAnalog 3 x Analog Op Amps, 3 x 24 = 723 x Analog Op Amps, 3 x 24 = 72 Resistive/Capacitive ElementsResistive/Capacitive Elements

DigitalDigital 8 x 18-bit registers, 8 x 400 = 32008 x 18-bit registers, 8 x 400 = 3200 1 x 12-bit register, 1 x 260 = 2601 x 12-bit register, 1 x 260 = 260 8 x 18-bit adders, 8 x 510 = 40808 x 18-bit adders, 8 x 510 = 4080 1 x 24-bit counter, 1 x 870 = 8701 x 24-bit counter, 1 x 870 = 870 1 x 7-bit counter, 1 x 250 = 2501 x 7-bit counter, 1 x 250 = 250 1 x 12-bit equality function, 1 x 120 = 1 x 12-bit equality function, 1 x 120 =

120120 2 x 18 bit muxes, 2 x 110 = 2202 x 18 bit muxes, 2 x 110 = 220 Misc logic = 200Misc logic = 200

Total = 9,300 transistorsTotal = 9,300 transistors

Initial FloorplanInitial Floorplan

Total Area =

77, 750 sq μm

Power ConsiderationsPower Considerations How much power will our chip consume?How much power will our chip consume? Ultra low-power hearing aids burn about Ultra low-power hearing aids burn about

1 mW1 mW Do we need special low-power adders?Do we need special low-power adders? Brandt & Wooley ’94 suggested using Brandt & Wooley ’94 suggested using

static CMOS ripple carry addersstatic CMOS ripple carry adders Looked at other papers proposing low-Looked at other papers proposing low-

power, high-performance adderspower, high-performance adders These designs were more geared toward These designs were more geared toward

other applications using clocks over 100 MHzother applications using clocks over 100 MHz Since we’re using a 5 MHz clock & a 20 KHz Since we’re using a 5 MHz clock & a 20 KHz

clock, ripple carry is ideal for usclock, ripple carry is ideal for us

Power Considerations Power Considerations (cont’d)(cont’d)

Brandt & Wooley listed their chip’s Brandt & Wooley listed their chip’s power consumption at 6.5 mW at 3Vpower consumption at 6.5 mW at 3V

Our design much smaller and runs at Our design much smaller and runs at much lower speed (20 KHz vs. 176 much lower speed (20 KHz vs. 176 KHz)KHz)

We’ll be using 1.8V sourceWe’ll be using 1.8V source Estimate chip’s total power at about Estimate chip’s total power at about

5 mW5 mW Sinc filter – 1 or 2 mWSinc filter – 1 or 2 mW PII Function & Clock Divider – 1 mWPII Function & Clock Divider – 1 mW Analog Portion – 2 or 3 mWAnalog Portion – 2 or 3 mW

Analog Device SizesAnalog Device Sizes

Some concern about sizing of Some concern about sizing of analog componentsanalog components

Average size of analog transistors Average size of analog transistors = 30 = 30 μmμm x 0.5 x 0.5 μmμm = 15 sq = 15 sq μmμm

Average size of analog resistors (500 Average size of analog resistors (500 Ω) = 24 μm x 600 nm = 14.4 sq μmΩ) = 24 μm x 600 nm = 14.4 sq μm

Average size of analog capacitors (1 Average size of analog capacitors (1 pF) = 30 μm x 30 μm = 900 sq μmpF) = 30 μm x 30 μm = 900 sq μm

May have to look at alternativesMay have to look at alternatives

Design DecisionsDesign Decisions

Decided on using static CMOS ripple carry Decided on using static CMOS ripple carry addersadders

Decided on modifying PII function to allow Decided on modifying PII function to allow user to input time period to wait before user to input time period to wait before clearing max and min registersclearing max and min registers Using 24-bit counter with 20 KHz clock to compare Using 24-bit counter with 20 KHz clock to compare

against wait periodagainst wait period Upper 12 bits of counter compared to wait periodUpper 12 bits of counter compared to wait period Gives wait period range of 200 ms to 14 minutesGives wait period range of 200 ms to 14 minutes

Decided on generating our own Nyquist clock Decided on generating our own Nyquist clock (20 KHz)(20 KHz) If clock needs to be cleaner, we can always go back If clock needs to be cleaner, we can always go back

to assuming two clock inputsto assuming two clock inputs Decided on analog component values (RC Decided on analog component values (RC

values)values)

Problems and QuestionsProblems and Questions

Have we bitten off more than we Have we bitten off more than we can chew?can chew? 9,000+ transistors is a lot for 2-3 9,000+ transistors is a lot for 2-3

digital designersdigital designers Much of transistor count taken up Much of transistor count taken up

by repeated modules like adders, by repeated modules like adders, registersregisters

Can always reduce design (PII Can always reduce design (PII function, clock divider)function, clock divider)

Analog device sizesAnalog device sizes Do we need to change our design?Do we need to change our design?

ResultsResults

More comfortable with overall More comfortable with overall designdesign More familiar now with mixed More familiar now with mixed

analog/Verilog simulationsanalog/Verilog simulations Ready to move forward with designReady to move forward with design

Structural Verilog simulationsStructural Verilog simulations Overall schematic including both Overall schematic including both

analog & digital portions of designanalog & digital portions of design Topology, gate sizing, RLC selection Topology, gate sizing, RLC selection

for analog partsfor analog parts LayoutLayout