Blaze DFM, Inc. Company Confidential

Design For ManufacturingFundamentals

Puneet GuptaBlaze DFM Inc.

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Outline

• Lithography and RET• Antennas and Vias• CMP and Fill

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Subwavelength Gap since .35 µm

Subwavelength Optical Lithography• EUV, X-rays,

E-beams all> 10 years out

• hugeinvestment in> 30 years ofoptical lithoinfrastructure

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Lithography Primer: Basics• The famous Raleigh Equation:

λ: Wavelength of the exposure systemNA: Numerical Aperture (sine of capture angle of thelens = a measure of the size of the lens system)k1: process dependent adjustment factor

• Exposure = amount of light or other radiant energyreceived per unit area of sensitized material.

• Depth of Focus (DOF) = deviation from a definedreference plane wherein the required resolution forphotolithography is still achievable.

• Process Window = Exposure Latitude vs. DOF plotfor given CD tolerance

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Numerical Aperture

•NA = n sin α n = refractive index for air, UB =1.Practical limit ˜ 0.93

•NA increase ⇒ DOF decrease DOF = λ / (2NA2)

•Immersion lithography ? n>1 (e.g., water)Figures courtesy www.icknowledge.com

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k1

• k1 is a complex process-dependent factor that captures RETtechniques, photoresist performance, etc

• Practical lower limit ˜ 0.25• Minimum resolvable dimension with 193nm steppers: 0.25 *

193nm / 0.93 = 52nmSource: www.icknowledge.com

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• Light interacting with the mask is a wave• Any wave has certain fundamental properties

– Wavelength (λ)– Direction– Amplitude– Phase

• RET is wavefront engineering to enhance lithographyby controlling these properties

Reticle Enhancement Technology (RET)Basics

λ

Amplitude

Direction

Phase

Courtesy F. Schellenberg, Mentor Graphics Corp.

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Direction: Illumination

• Regular Illumination

• Many off-axis illumination (OAI) strategies

– Annular

– Quadrupole / Quasar

– Dipole+

or

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OAI: Impact on Physical Design• Off axis amplifies certain

pitches at the expense of theothers “Forbidden” pitches

• Plot: DOF < 0.5um isunacceptable the pitch isforbidden

• Quasar / QuadrupoleIllumination– Amplifies dense 0°, 90°

lines, destroys ±45° lines– Dipole Illumination

• Prints only oneorientation

• Must decompose layoutfor two exposures

Socha et al. “Forbidden Pitches for 130 nmlithography and below”, in OpticalMicrolithography XIII, Proc. SPIE Vol. 4000(2000), 1140-1155.

Acceptable

Unacceptable

130 nm lines, printedat different pitches

Quasar illuminationNA=0.7

Isol

ated

Den

se

Dep

th o

f Foc

us0

0.5

1

1.5

200 400 600 800 1000 1200 1400Pitch (nm)

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Printing at Different k1 Values

Source: Lars Liebmann, IBM

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Aperture: OPC (and Phase: PSM)

In layout tool

Scattering bars and serifs

Phase-0 and phase-180apertures to print smallerfeatures at the samewavelength

There is still plenty of residual CD error !

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OPC (Optical Proximity Correction)

• Gate CD control is extremely difficult to achieve– Min feature size outpaces introduction of new hardware solutions

• OPC = one of available reticle enhancement techniques(RET) to improve pattern resolution– Proactive distortion of photomask shape compensate CD

inaccuracies

Before OPC After OPCC.-H. Park et al., SPIE 2000

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Residual CD Error After OPC

}Edge Placement Error

• Sub wavelength features are not printed perfectly even withthe use of OPC, less so with process fluctuations

• The residual CD error after OPC is called Edge PlacementError (EPE)

• EPE is an important component of line width variation

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SRAFs and Bossung Plots

• Bossung plot– Measurement to evaluate lithographic manufacturability– Maximize the common process window– Horizontal axis: Depth of Focus (DOF); Vertical axis: CD

• SRAF OPC– Improves process margin of isolated pattern– Larger overlap of process window between dense and isolated lines

-20

20

60

100

140

180

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

DOF (um)

CD (n

m)

1211.51110.5109.5

Bias OPC SRAF OPC

-20

20

60

100

140

180

-0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8

DOF (um)

CD

(nm

)

1211.51110.5109.5

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0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

0.22

0.0 0.1 0.2 0.3 0.4 0.5 0.6

SRAF2 SRAF1 No SRAF

DOF

CD

2 SB 1 SB W/O SB

SB = Scattering Bar ≡ SRAF

Thanks: Chul-Hong Park, UCSD

SRAFs and Depth of Focus

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Phase: PSM

conventional maskglass

Chrome

phase shifting mask

Phase shifter

0 E at mask 0

0 E at wafer 0

0 I at wafer 0

• Phase Shifting Masks etch topography into the mask– Creates interference fringes on the wafer boost contrast Can make extremely small gates

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Double-Exposure Bright-Field PSM

0

180

180 + =

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The Phase Assignment Problem• Assign 0, 180 phase regions such that critical

features with width (separation) < B areinduced by adjacent phase regions withopposite phases

Bright Field Dark Field

0 180180

0

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Key: Global 2-Colorability

• If there is an odd cycle of “phase implications”layout cannot be manufactured

– layout verification becomes a global, not local,issue

?180 0

0180 180

180

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Restricted Design Rules (RDR’s)

Source: Lars Liebmann, IBM• Correct by construction approach• “Soft reset” of Moore’s Law• Impacts studied by Gupta et al., Proc. DAC04

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Outline

• Lithography and RET• Antennas and Vias• CMP and Fill

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Charging and Antennas

• Process steps use plasmas, charged particles– Charge collects on conducting poly, metal surfaces– Capacitive coupling: large electrical fields cause

damage or breakdown of gate oxides, induced Vtshifts

• Limit antenna ratio = (Apoly + AM1 +.. ) / Agate-ox

– AMx = metal(x) area that is electrically connected tonode without using metal (x+1), and not connectedto an active area

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Charging and Antennas

• There is no problem after chip is complete, sinceevery net has a driver

• Long line connected only to a gate causes failureduring manufacturing

Driver (diffusion) Load (poly)

M1M2

Driver (diffusion) Load (poly)

M1

Courtesy Lou Scheffer

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Today’s Antenna Solutions

Driver (diffusion) Load (poly)

M1M2

Driver (diffusion) Load (poly)

M1M2

Driver (diffusion) Load (poly)

M1M2

RerouteVias, hard topost-process

BridgeExtra wire, vias,congestion

DiodeExtra leakage,area, delay

Courtesy Lou Scheffer

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Antenna Futures• Tightness of antenna rules depends on gate leakage

– Thin oxides are leaky, and have better antenna ratios!– 180nm: antenna ratio = 2000 for thin-oxide in chip core, 400

for thick-oxide at I/Os• Antenna ratios are already getting worse

– 90nm: as low as 30, depending on process and library• High-k dielectrics thicker gate oxide less leakage

hard fails antenna ratios will get much worse!• Future: More preemption?

– Post-processing strategy will fail– Automatic use of dioded cells?– Antenna-aware global routing?

• Buffering and sizing with antenna-awareness• Unfixed antenna yield loss vs. fixed antenna yield loss

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Related: Thermal Voiding in Copper• Cu processing causes new problems for vias

– Voids migrate under thermal stress towards vias• More stress on smaller vias at 90nm

– Single via in large metal causes failure need 2-,3- or 4-cut vias when connecting to wide metal

– Also applies to “close connections” to wire-wires

Courtesy Lou Scheffer

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Via Doubling• Single-cut via Double-cut via• Improves yield and reliability• Post-processing: Easy to get

70-80% doubling, but not more

K.S. Leung, ISPD-2003

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Outline

• Lithography and RET• Antennas and Vias• CMP and Fill

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CMP and Layout Density• Plasma etching

– Density-dependent loading effects– Short range (microns), helped by wide-wire rules

• Chemical-Mechanical Planarization (CMP)– Dielectric, barrier layer, metal have different hardness– Planarize at different rates– Long range (hundreds of microns), helped by dummy fill

• Keep layout density even, at multiple length scales

wafer carrier silicon wafer

polishing pad

polishing table

slurry feeder

slurry

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CMP Types

• Cu Damascene CMP

• STI CMP

(A) deposit Copper into trench; (B) polish bulk Copper by CMP(C) remove barrier by CMP

(A) fill the trench with oxide after etching Nitride film; (B) polish oxide until the nitride by CMP (C) etch Nitride and underlying oxide to expose the active device area

Area Fill for Cu CMP• Dishing can thin the wire or pad, causing

higher resistance wires or low-reliability bondpads

• Erosion can also result in a sub-planar dip onthe wafer surface, causing short-circuitsbetween adjacent wires on next layer

Oxide

CopperOxide erosion

Copper dishing

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Density Control By Filling/Slotting

• Area fill: electrically inactive;floating or grounded

• Slotting: helps thermal stressand local density rules

– Many wires are “wide”: >2.5um width must be slotted insome 90nm rules

• Post-layout slotting vs. “bus” ofthin wires?

Post-CMP ILD thicknessFeatures

Area fillfeatures

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Dummy Fill Requirements• Evolution of Requirements

– 180nm – 20% to 80%, whole chip– 130nm – 20% to 80%, sliding window of 300u x 300u– 90nm – 25% to 75%, 300u x 300u– 90nm – 30% to 70%,1000u x 1000u– 90nm – 45% to 50%, whole chip– Still a saddle point between foundry and EDA

• “crouching customer, hidden value”• Fill (transitively) tied to power/ground?

– No floating metal– Shallow ties

• no big branch dangling from power/ground mesh• big branches behave like floating metal

• Fill with minimal impact on timing?– Stay away from signal geometries whenever possible

• Fill as additional power mesh for better IR-drop?– Fill to strengthen low-k dielectric?

K.S. Leung, ISPD-2003

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Floating vs. Grounded Fill Solutions

FA

W

W – Variable Width

Active Geometry

FillGeometry

W

FA

S

W - Width of fillFA – Fill to activespacingS –Fill Spacing

Traditional Floating Fill Grounded Fill

W

Next Layer

VSS

• Floating: less capacitance, but unpredictable• Grounded: more capacitance, but predictable

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Today’s Design-Manufacturing Interfaces

Litho/Process(Tech. Development)

Library(Library Team) Layout & libs

(Corner CaseTiming)

Design(ASIC Chip)

Mask: Dataprep(Mask House)

Design RulesDevice Models

Tapeout Layout

(collection of polygons ?)

RET

Guardbanding all the way in all stages!!(e.g. clock ACLV guardband ~ 30%)

What do we lose ?• Performance Too much worst-casing• Turnaround time Huge runtimes, overdesign• Predictability RET is applied post-design• Mask costs Overcorrection• Designer’s intent lost RET is not driven by design

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Future Design-Manufacturing Interface• Design, EDA, mask, lithography, etch communities

must together maintain the cost (value) trajectory ofMoore’s Law

• Bidirectional design-mfg pipeline driven by cost, value– Pass functional intent to mask and foundry flows– Pass limits of mask and foundry flows up to design

• Examples– Manufacturability and cost/value optimization– Exploitation of systematic variations– Composability– Performance impact-limited dummy fill– Intelligent mask data prep, restricted design rules...

• Bringing into production: Much work lies ahead