design flow pads

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VHDL to Place-and-Route Design Flow Tutorial

By: Wei Lii Tan

Advisor: Dr. Robert ReeseThis revision: October 30, 2001

Mississippi State UniversityDallas Semiconductor

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Major Changes in This Revision• Added explanation for Display Options and Find

forms.• Added section on ‘checking for shorts between

VDD and GND’ in the ICFB section.

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Introduction• This tutorial will guide you through the synthesis

of a fully placed-and-routed design from a VHDL entity.

• The tutorial will use the following CAD tools:

- Synopsys Design Compiler

- Cadence Design Planner

- Cadence Silicon Ensemble

- Cadence ICFB

- Modelsim QHDL

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Introduction

• The following conventions will be used in this tutorial:- File names will be in italics, e.g. /ccs/issl/micro/users/tan/myfile.vhd- User input (e.g. what you need to type)

will be in boldface, e.g. type swsetup cadence-ncsu

• It is highly recommended that you go through the ‘no pads’ tutorial before you start on this one.

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The Example Design

• The design we will be using as an example for this tutorial is a VHDL model of a Dallas Semiconductor DS1620k temperature sensing kit.

• The interface reads the temperature from the DS1620k, then outputs the data to a seven-segment digit display.

• The design also includes some simple gates for debugging, such as a NAND gate, NOR gate, inverter, and a DFF.

• A simple counter is included in the design too.

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The Example DesignThe main top-level signals in the design are:• inv_in, inv_out: input and output for simple

inverter• nand2in_a, nand2in_b, nand2_out: inputs and

output for simple NAND gate.• nor2in_a, nor2in_b, nor2_out: inputs and output

for simple NOR gate.• _csb_6_ to _csb_0_: Signals for MSB of the

seven-segment digit display.• _lsb_6_ to _lsb_0_: Signals for LSB of the seven-

segment digit display.

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Copying Example Files

• Copy the entire directory /ccs/issl/micro/users/tan/tutorials/design_flow into your work directory

• *important*All directories will start with your_work_directory/design_flow, unless specified otherwise.

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Design Flow

Synopsys Design Compiler

Modelsim

Cadence Design Planner

Cadence Silicon Ensemble

Cadence ICFB

Modelsim

VHDL Model

Verilog Model

Verilog Model

DEF File

DEF File

Verilog Model

VHDL -> VerilogConversion

Verilog Verification

Standard Cell Placement

Standard Cell Routing

Export to Other Formats,SPICE Verification

Verilog Verification

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• This tool will convert a VHDL model to a Verilog model. It requires the use of the following user-provided files:- Library file, in .db format.- Script file (file extension .script)- The VHDL file to be converted to Verilog.

• At this stage, we will be using Design Compiler to generate a Verilog model, without pads, of a VHDL file called topchip_gold_pads.

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• The VHDL file that we will be using is topchip_pads.vhd.

• Using a script file with Design Compiler, we will convert this VHDL model to verilog.

• The script file is called topchip_pads_int.script, and can be found in the synopsys/run_syn directory.

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Why use a script file?

• Using a script file with dc_shell is equivalent to typing the exact commands in dc_shell interactively.

• A script file automates the process of typing in all the commands manually.

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What is the .db file for?• The database (.db) file holds information

about the standard cell library used to implement the VHDL design.

• It provides information about the standard cells: the names of the standard cells, input/output ports, as well as timing characteristics and functionality.

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Design Compiler

1. Change to the directory synopsys/run_syn

2. Type swsetup synopsys

3. Type dc_shell –f topchip_pads_int.script

4. The ‘-f’ option tells design compiler to use a script file, and not run in interactive mode.

5. After design compiler finishes (it should take about 5 minutes to finish the compilation), a verilog netlist file called topchip_pads.v should be created in the directory synopsis/gate.

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Getting Rid of Unwanted Characters

• Cadence’s family of CAD tools have strict rules about naming ports and nets. Therefore, we need to get rid of some unwanted symbols in our Verilog netlist, so that we won’t run into problems further down the road, when using the Cadence Tools.

• Symbols like front-slashes, back-slashes, and other numerical operators are not allowed in net names, if you are using Cadence tools.

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Getting Rid of Unwanted Characters

6. Change to the synopsys/gate directory.

7. Run the perl script called myfilter.pl on the verilog netlist file, by typing:

perl myfilter.pl topchip_pads_int.v

8. This will filter out all the unwanted characters from the netlist file.

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Adding I/O Pads (Synopsys Design Compiler)

9. Using another script file (topchip_pads.script), we will add I/O Pads to the verilog netlist topchip_pads_int.v.

10. Type dc_shell –f topchip_pads.script

11. This will generate another verilog netlist file, topchip_pads.v, in the directory synopsys/gate.

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Making Other Changes

• Design Compiler will add input and output pads automatically, but we still need to add the VDD, GND and bi-directional and no-connection Pads manually.

• Go to the /synopsys/gate directory.

• Using any text editor, open up the file topchip_pads.v for editing.

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Adding Other Pads• Add in these pad declaration lines (somewhere

before the endmodule line).

PAD_BIDIRHE MY01 ( .DO(ds_dqout), .DI(ds_dqin), .OEN(tri_direction),

.YPAD(ds_dq));

PADVDD MY02 ( .vdd(vdd), .YPAD(vdd_pad));

PADNC MY03 ();

PADGND MY04 ( .gnd(gnd), .YPAD(gnd_pad));

PADNC MY05 ();

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Adding Other Pads• The Cadence P&R tools will not auto-route

the vdd and gnd I/O pins to the supply rings, no matter what name you give their ports in the verilog netlist. We will have to do this by hand later on in ICFB.

• The two PADNC pads are there just to fill in extra space (we are using a 40-pad square padframe, therefore we need 10 pads on each side).

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Changes to Module Ports

• We now need to modify the module ports in the verilog netlist.

• Delete the nets ds_dqin, ds_dqout, and tri_direction from the module port declaration.

• Add the net ds_dq to the module port declaration.• Delete the net ds_dqin from the input declaration.• Delete the nets ds_dqout and tri_direction from

the output declaration.• Add an inout declaration with the net ds_dq.• Refer to the next slide for details

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Changes to Module Portsmodule topchip_pads ( inv_in, inv_out, nor2in_a, nor2in_b, nor2_out,

nand2in_a, nand2in_b, nand2_out, dff_out, dff_in, ds_dqout, ds_dqin, tri_direction, led_a, led_b, switch_control, count_enable_not, clk, msb_dp, lsb_dp, _csb_6_, _csb_5_, _csb_4_, _csb_3_, _csb_2_, _csb_1_, _csb_0_, _lsb_6_, _lsb_5_, _lsb_4_, _lsb_3_, _lsb_2_, _lsb_1_, _lsb_0_, resetn, ds_rn, output_rdy, clk_out, ds_dq );

input inv_in, nor2in_a, nor2in_b, nand2in_a, nand2in_b, dff_in, ds_dqin, switch_control, count_enable_not, clk, resetn;

output inv_out, nor2_out, nand2_out, dff_out, ds_dqout, tri_direction, led_a, led_b, msb_dp, lsb_dp, _csb_6_, _csb_5_, _csb_4_, _csb_3_, _csb_2_, _csb_1_, _csb_0_, _lsb_6_, _lsb_5_, _lsb_4_, _lsb_3_, _lsb_2_, _lsb_1_, _lsb_0_, ds_rn, output_rdy, clk_out;

inout ds_dq;

Add

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Sample File with Changes Implemented

• The file synopsys/gate/topchip_pads_sample.v contains all the changes that we talked about in the previous slides.

• You can use that file as a reference on what to change in the verilog netlist, or simply copy it over your topchip_pads.v file if you don’t feel like making the changes yourself.

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Modelsim• The next step in the design flow is simulating the

verilog netlist that we generated. • Change to the qhsim directory, and type swsetup

modelsim.1. If the qhsim/work directory does not exist, create

one by typing qhlib work. - The ‘qhlib work’ command creates a

directory called ‘work’, and also stores Modelsim information in the ‘work’

directory. This directory will be the object directory for standard cells and top-level designs that are compiled using Modelsim.

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Modelsim3. Before we compile our top-level design

(topchip_pads.v), we need to compile the standard cells that make up topchip_pads.v. In the qhsim directory, type: qvlcom ../synopsys/gate/libcells.v.

4. Type: qvlcom ../synopsys/gate/topchip_pads.v. This will compile our top-level design file.

5. Now, type: qvlcom ../synopsys/gate/tb_topchip_pads.v. This will compile the testbench for our design. The testbench supplies input vectors needed to test the functionality of our design.

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Modelsim6. To enter Qhsim and simulate our design, type:

qhsim tb_topchip_pads. Note that the argument after the ‘qhsim’ command refers to the Verilog module name of our design, not the file name.

7. After you do step 6, you should see a screen that looks like Figure 1. In the command window, type view signals <enter> and view wave <enter>. These commands bring up the signals and waves windows respectively.

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Figure 1: Modelsim Command Window

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Modelsim8. Go to the signals window, click on view -> wave

-> signals in region. This will add all the top-level signals to the wave window.

9. Type run 150 us in the command window. This will run the testbench for 150 microseconds.

10. Note that all the commands that you entered in the command window can be entered into a text file, then recalled by typing do filename in the command window.

7/31/2001 WLTFigure 2: Simulation Results Waveform

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Getting Ready to Import into Design Planner

• Now that we have verified that the Verilog netlist works properly, let’s import the Verilog netlist into Cadence Design Planner.

• Copy the file topchip_pads.v from the directory synopsys/gate to the directory cadence/dp_se/netlist.

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Starting Design Planner

1. Change to the directory cadence/dp_se. 2. From this directory, the main

subdirectories are: run: This will be the directory to invoke all of the Design Planner tools.tech: Contains the tech.dpux file.netlist: contains the gate level verilog netlist

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(continued from previous page)

design_db_ami06: Contains the pillar database of the design

jennings_ami06_pads_noqn: Contains the pillar database of the standard

cells.

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3.Change to the run directory.

4.Type “swsetup cadence-dp”

5.Type “areaPdp –tech ../tech &”. This will invoke the Design Planner. You should see two windows: the Pillar window, and the AreaPdp PCW log window.

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Importing the Netlist

1.In the Pillar window, click on:

File -> Import -> Verilog

2.Wait for the ver2hld form to show up - it may take a couple of minutes to show up, and clicking on other menu items at this time may cause the program to crash.

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Importing the Netlist

3.In the ver2hld form, type in “../netlist/topchip_pads.v” for input verilog filename.

4.Check the run translation box, and type “topchip_pads” for name of top cell.

5.Check the name of global nets box, and type “vdd” for power, “gnd” for ground.

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Importing the Verilog Netlist into Design Planner

6. In the ver2hld form, check the tie nets (up down) box, and enter “vdd gnd” for that field.

7. Type in “design_db_ami06” for the output library name.

8. Make sure the ‘Create Pins for Top Layer of Cell’ box is NOT checked.

9. Click on OK. This will generate an AutoLayout view for topchip_pads.v.

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Figure 3: Ver2hld

form

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Floorplanning (Design Planner)

1.In the Pillar window, click on File -> Explore Libraries

2.In the browse libraries form, double click on design_db, topchip_pads, then autoLayout.

3.The areaPdp main edit window will show up. Notice that all blocks and cells are placed at the origin (0,0).

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Figure 4: topchip_pads autoLayout, before Floorplan Initialization

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Initializing the Floorplan (Design Planner)

1.In the areaPdp edit window, click on Floorplan -> Initialize

2.The Initialize Floorplan form will appear. Estimate aspect ratio will determine the aspect ratio of the design – any value other than 1.0 will generate a rectangular design, while 1.0 will generate a square design.

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Initializing the Floorplan (Design Planner)

3.Enter 110 for I/O Circuit to Core Dist

4.Make sure that the Move-Fixed box is checked, and the None box is not checked.

5.Click the Apply & Close button.

7/31/2001 WLTFigure 5: After Floorplan Initialization

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Placing Pads (Design Planner)

1.In the areaPdp window, click on

Place -> I/O -> Pads/Pins

2.A form will appear. Select the following selections for the form fields:

I/O Init Module: Print Random Io File

I/O Init Filename: ioPlace

I/O Init File Format: normal

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I/O Init I/O Boundary Mode:

Generate new

I/O Init I/O Side Ordering:

B:L->R R:B->T T:R->L L:T->B

3.Click on the Apply button. This will generate a file called ioPlace that contains I/O cell placement information.

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4.Now that the ioPlace file has been generated, we will proceed to actually place the I/O pads with the information contained in the ioPlace file.

5.Change I/O Init Module to Load File & Auto Place

6.Change I/O Init I/O Boundary Mode to Maintain Existing

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7.Click on the Apply & Close button.

8.In the areaPdp edit window, you should see the top layer pins placed evenly on all four sides of the boundary.

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Figure 6: Place I/O Form

7/31/2001 WLTFigure 7: After Pads Placement

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Getting The Correct Pad Orientations

• When the pads are placed, their orientation will be incorrect.

• For each pad, highlight the pad and press shift-r twice. This will orientate the pads correctly

• A small triangle marks the top-right corner of the pad (this is true for all other cells too). Use this triangle to help determine if the pads are in correct orientation.

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Figure 8: Incorrect vs. Correct Pad Orientation

Incorrect Orientation Correct Orientation

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Placing Corner Pads

1.In the areaPdp edit window, click on

Place -> I/O -> Corner Cells -> Add

2.Once the add corner cells form shows up, click on all 4 of the I/O Corner [BL], I/O Corner [BR], I/O Corner [TL] and I/O Corner [TR] boxes.

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Placing Corner Pads

• You can use the Browse button to select the correct corner pad, or you can simply type in your selection in the boxes.

• Type in the following for all four corner pads:

Library Name: Jennings_ami06_pads_noqn

Cell Name: padfc

View Name: abstract

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Placing Corner Pads• Select R0, R90, R180 and R270 for BL, BR, TR

and TL orientation respectively.• Click on the Apply & Close button.

7/31/2001 WLTFigure 9: After Corner Pad Placement

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Placing Corner Pads• You may notice that Figure 9 show more layers

than just the cell boundary. To show more layers, go to the View -> Preferences menu

• Next, drag the levels bar all the way to the right.

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Getting the Correct Corner Pad Orientation

• As shown in Figure 9, the orientation for the four corner pads are wrong.

• To fix this, click on a corner pad, then press shift-r once. This should set the pad in correct orientation.

• Do the same for all corner pads.• Save your design as ‘pads’ by clicking on

File -> Save as… , then typing ‘pads’ for the save filename.

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Figure 10: Correct Corner Pad Orientation

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File-Save Woes• Note: If you are using an xterm connection to run

Design Planner (i.e. you are not using a UNIX machine), Design Planner will have a tendency to freeze when saving files. Unfortunately you cannot do anything about this, except to save often, so that if Design Planner happens to freeze while you are saving a file, you can always go back to your last saved version.

• You can also try using ‘save’ instead of ‘save as’. The ‘save’ command usually will not cause the program to crash. This will overwrite the previous file, though.

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Creating Supply Rings (Design Planner)

1.In the areaPdp window, click on

Floorplan -> Preroutes -> Supply Rings

2.The create supply rings form will appear.

3.Click on Nets: Named. Type “vdd gnd” for the names.

4.Select Area for ring mode. Check Snap to grid.

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5. Now we will enter the characteristics for the horizontal and vertical ring layers. For LayerH, select met1, type in “4.5 4.5” for width(s) and “3 3” for spacing(s).

6. For LayerV, select met2, type in “4.5 4.5” for width(s) and “3 3” for spacing(s).

7. This will create supply rings for vdd and gnd 4.5 units wide, with 3 units spacing in between, using metal 1 for the horizontal ring portions and metal 2 for the vertical ring portions.

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Figure 11: Route Rings Form

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8. Click on the Apply & Close button. 9. The mouse cursor will change into a crosshair.

Click on the top left corner of the ring, then the bottom right corner. The positions you click will be used as the inner positions of the supply ring, so be sure to leave some space outwards of the positions you click on.

You should now be able to see the supply rings in the areaPdp window.

10. Save your file as ‘supply_rings’.

7/31/2001 WLTFigure 12: After Creating Supply Rings

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Creating Region of Rows (Design Planner)

1. In the areaPdp window, click on Floorplan -> Rows -> Create region of rows

2. Set Site Name as core.3. Set Row orientation as Horizontal.4. Uncheck the Number of rows box.5. Check Channel Offset, and set offset to 0.06. Check Site Orient Pattern and set Orient to R0.7. Set Pattern to R0 MX.8. Check the Abutted box.

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Figure 13: Draw Site Region Form

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9. Click the Apply button.

10. The mouse cursor should change into a crosshair. Click the top left corner of the region to be created, then click the bottom right corner. The region should be placed somewhere inside the pad frame, within the supply rings.

11. A region of rows is created; this is where the single height logic cells will be placed.

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12. Now, change Site Name to dbl_core.

13. Repeat the process for the dbl_core rows. Try to get the dbl_core and core rows to overlap as closely as possible – design planner will automatically ‘snap’ them into place.

14. This will create a region of rows for double-height cell placement.

15. Save your design as ‘rows’.

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• Note about creating rows:• Try to have both the core and dbl_core regions overlap

each other exactly. If they don’t, Design Planner might crash when you are placing the cells.

• You can zoom into an area (right-click and drag) or out of an area (left-click the zoom out button on the right of the editing window), even while you are placing the rows.

• You can also pan left, right, up or down when placing the rows. Click on the arrow buttons to the right of the editing window.

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• You should first zoom in to the top-left corner of the region of rows when your cursor looks like a crosshair.

• Then left click once on the top-left corner of the region of rows.

• Zoom out so you can see the entire region, the zoom into the bottom right corner.

• Left click again on the bottom right corner of the region of rows.

• This should allow you to place overlapping regions easily.

7/31/2001 WLTFigure 14: After Creating Region of Rows

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Qplace (Design Planner)

• The next step is to use Qplace to automatically place standard cells within the pad frame, inside the region of rows we created earlier.

1.In the areaPdp window, click on Place -> Blocks/Cells (Qplace)

2.Leave the settings as the defaults, then click on Apply and Close.

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Figure 15: Qplace Sequencer Form

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Qplace (Design Planner)

• This process may take a few minutes. After that, the standard cell blocks should be placed inside the region of rows.

• If the region of rows you created earlier was too small for the cells to fit, an error message will be generated and Qplace will fail.

• After Qplace succeeds, save your design as ‘qplaced’.

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Figure 16: After QPlace

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Exporting to DEF Format (Design Planner)

1.In the areaPdp window, click on Interfaces -> Silicon Ensemble -> Export -> DEF

2.In the hld2def form, specify an output filename for the DEF file. This should go into the Output Def File Name slot. Include the desired path for the target file too.

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3. Type “../def_files/topchip_pads_qplaced.def” for the Output Def File Name.

4. Set the DEFOUT Library Name to design_db_ami06.

5. Type in “topchip_pads” for DEFOUT Cell Name.

6. Type in ‘qplaced’ for the DEFOUT View Name. DEFOUT will use this saved file to generate the Def file.

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7.Fill in the rest of the options according to Figure 17, on next slide.

8.Click on OK.

9.This will generate the Def file: cadence/dp_se/def_files/topchip_pads_qplaced.def

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Figure 17: hld2def

form

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Why export to DEF?

• The DEF format is Cadence’s method of transporting designs from one Cadence CAD tool to another.

• DEF stands for ‘Design Exchange Format’. You will need to export to DEF when transferring a design from Design Planner to Silicon Ensemble, or from Silicon Ensemble to ICFB.

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Silicon Ensemble

• We will now move on to using Silicon Ensemble to complete the design flow.

1. Quit AreaPdp by closing the Pillars window.2. Make sure that you are in the cadence/dp_se/run

directory.3. In the terminal window, type:

swsetup cadence-sesedsm &

• This will start Silicon Ensemble.

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Importing the LEF File (Silicon Ensemble)

1.In Silicon Ensemble, click on File -> Import -> LEF.

2.In the Import LEF form, select the file ../tech/jennings_ami06_pads_noqn.lef, then click on OK.

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Importing the LEF File (Silicon Ensemble)

3.In the Silicon Ensemble window, click on File -> Import -> DEF.

4.In the Import DEF window, Select the file ../def_files/topchip_pads_qplaced.def

5.Click on OK.6.If the design does not show up, click on Fit

in the Silicon Ensemble window to view the design.

7/31/2001 WLTFigure 18: The Imported DEF File

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Viewing Layers (Silicon Ensemble)

• To view nets, special wires, pins, cell boundaries etc. while you are working on your design, make sure all the appropriate Vs (visible) fields are checked.

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Adding Filler Cells (Silicon Ensemble)

1. Click on Place -> Filler Cells -> Add Cells.

2. In the SROUTE Add Filler Cells form, type in “FILL” for Model, and “fill” for prefix.

3. Make sure ONLY the North and Flip South boxes are checked.

4. In the special pins section, add one entry for vdd and one entry for gnd (refer to Figure 19 on the next slide)

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Figure 19:

Add Filler Cells Form

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Adding Filler Cells (Silicon Ensemble)

5.Click on OK.

6.This will add filler cells to your design. Filler cells provide n-well continuity for your standard cells.

7/31/2001 WLTFigure 20: After Adding Filler Cells

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Routing Power (Silicon Ensemble)

1.Click on Route -> Route Power -> Follow Pins.

2.In the Layers section of the Sroute Follow Pins form, set Width to 1.80.

3.Click on OK.

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Figure 21: Sroute Follow

Pins Form

7/31/2001 WLTFigure 22: After SRoute Follow Pins

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Wroute (Silicon Ensemble)1. Click on Route -> Wroute.2. In the Wroute form, click on OK.• Wroute will run. This will take a few minutes to

complete.• After this point, all the interconnect routing of the

design has been done.

7/31/2001 WLTFigure 23: After WRoute

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Viewing Different Layers in Silicon Ensemble

• You won’t be able to see the interconnect metal layers in Figure 23 unless you enable the layer to be viewable.

• Click on View -> Layers.

• In the Layer Visibility form, click on All Objects, then check all the layer check boxes.

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Display Options• Silicon Ensemble allows you to customize

the view window to display/not display certain parts of your design.

• In the main window, click on View -> Display Options…

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Display Options• Notice the top part of the Display Option form

allows you to select ‘On, Here, Big, Small etc’ for the Level. By choosing a level here and clicking on the checkboxes, the selection for that particular checkbox will rotate between ‘OFF’ and the level you chose.

• For example, select Small for the level. Now, click once on the Cells checkbox in the Objects section.

• If the checkbox was originally set to On, it will switch to Off after the first time you click it. Click on it again to set it to Small.

• Click on Apply.

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Display Options• Your cell boundaries will now only be

visible when you are zooming into a smaller portion of the design.

• If you click on the Fit button in the main window, you will not see the cell boundaries any more.

• Try zooming into a small area of the design. The cell boundaries will be visible again.

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Display Options

• The following explains the different levels:

- On: visible at any level.

- Here: visible at level that is currently displayed in the main window.

- Big, medium, small: visible at big, medium or small levels respectively.

- Off: not visible at any level.

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Checking Pin Names• You can easily check to see the names of the routed pins in

the standard cells using the Display Options form.

• In the Names section of the Display Options form, set Pins to On, or Small.

• Click on the Apply button. The pin names will now be visible.

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The Find Form• You can find cells, nets and pins etc. with the

Find form. Click on Edit -> Find… to access the Find form.

• On the Find form, set Type to Net. • Type n1022 for the Name.• Set the background dimmer to 70, then click on

the Hilight button.• The display will be dimmed, while the msb_dp

net will be highlighted in the color selected in the Find form.

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The Find Form• You can also give partial

names, e.g. n10* instead of n1022. If you click on the Show List checkbox, you will see a list of matching names.

• Type n10* for the net name, click on Show Lists, then click on Find. You should see a list of net names starting with ‘n10’.

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The Find Form

• You can now click on each individual entry in the list, and highlight the particular net, or select it.

• The Find form, together with the Display Options form, provide a convenient way of debugging your overall routed design.

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Checking for Violations

• Violations will appear as ‘X’ marks on your design. Be sure that there are no violations created during the routing.

• Silicon Ensemble will tell you the number of violations created during Wroute (Refer to Figure 24, on the next slide). If there are any violations, be sure to fix them before moving on. You should not get any violations for this exercise.

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Figure 24: Total Number of Violations Reported by Silicon Ensemble

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Export to DEF Format (Silicon Ensemble)

1. Click on File -> Export -> DEF.

2. Type “../def_files/topchip_pads_wrouted.def” for the DEF file name.

3. Make sure the All checkbox is checked.

4. Click on OK.• This will create the DEF file

cadence/dp_se/def_files/topchip_pads_wrouted.def.

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Running SEDSM in Script Mode

• When using SEDSM in interactive mode (like we just did), SEDSM will echo back your commands in the command-line window.

• If you enter these commands into a text file, you can run SEDSM in script mode. To run SEDSM in script mode, type the following in the cadence/dp_se/run directory:sedsm –b –gd=ansi “EXECUTE script.mac;” &where script.mac is the name of your script file.

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Running SEDSM in Script Mode

• The cadence/dp_se/run directory has a script file called topchip_pads.mac which will essentially perform all the procedures we did in interactive mode, from importing the LEF file to exporting the topchip_pads_wrouted.def file.

• To execute the script file, go the the cadence/dp_se/run directory, and type:

sedsm –b –gd=ansi “EXECUTE topchip_pads.mac;” &

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Re-running SEDSM after a Crash

• If Silicon Ensemble crashes while you are running it, you need to delete all the .dtp files in the cadence/dp_se/run directory before you run it again. The .dtp files are the lock files for Silicon Ensemble

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Adding Pin Placement via Perl Script• Before importing the DEF file into ICFB, we need

to add top-layer pin placement to the file topchip_pads_wrouted.def.

• Go to the cadence/dp_se/def_files directory.• Type: perl insert_pads.pl

topchip_pads_wrouted.def• This perl script, written by Dr. Robert Reese, will

automatically place top-layer pins in the correct positions (on top of their respective YPAD ports) by modifying the PINS section of the DEF file.

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Cadence ICFB

• Cadence ICFB is the last CAD tool in this design flow. In ICFB, our design can be exported into a HSpice netlist, a Verilog netlist, or GDSII / CIF formats, among others.

• Cadence ICFB is potentially the most powerful CAD tool among the tools in this design flow, but it is also the most complex.

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Starting ICFB

1. If you’ve previously used Design Planner or Silicon Ensemble in your current xterm window, launch a new xterm window.

2. Change to the cadence/dfII directory.3. Type swsetup cadence-ncsu.4. Type “icfb &” to launch ICFB.5. You should see three windows pop up: the ICFB

Command Interpreter Window (CIW), the Library Manager window, and another windows telling you about the changes for the latest version of ICFB. Close the third window.

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Importing DEF into ICFB1. In the CIW, click on File -> Import -> DEF.

2. Enter “tutorial” for Library Name, “topchip_pads” for Cell Name, and “autoRouted” for View Name.

3. Enter “../dp_se/def_files/topchip_pads_wrouted.def” for DEF File Name.

4. Make sure Silicon Ensemble is checked.

5. Refer to Figure 25 (next slide) for all other options in the form.

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Figure 25: Import DEF

Form

7/31/2001 WLTFigure 26: topchip_pads autoRouted view

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Importing DEF into ICFB

6. Open the autoRouted view of topchip_pads.

7. In the autoRouted view, before you do anything, click on Design -> Save. This ensures that if anything goes wrong, you can always come back to the autoRouted view.

8. Click on Tools -> Layout. This changes the tool from abstract-editing mode to layout-editing mode.

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Importing DEF into ICFB9. Click on Edit -> Search…10. In the Search form, search for inst in current cellview,

with view name = abstract. Replace with view name -> layout. (Refer to Figure 27, next slide).

11. Click on Apply, then Replace All.12. Close the search form, then click on Design -> Save

as…13. Save the design in the same library and cell, but change

the view to ‘layout’.14. When you close the editing window, you will be asked if

you want to save changes for the autoRouted view. Do not save any changes here or the autoRouted view will be over-written.

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Figure 27: Search Form

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Viewing Layers in ICFB• Whenever in ICFB’s layout editor, you can press

shift-f to increase the number of layers viewed, or ctrl-f to decrease the number of layers viewed.

• For example, if you press shift-f while viewing the topchip_pads layout, you will be able to see the metal, poly, active etc. layers of the individual standard cells. If you press ctrl-f, you will only be able to see the boundaries of the individual standard cells.

7/31/2001 WLTFigure 28: topchip_pads layout view

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Before You Start…• This section attempts to briefly teach you a

few basics of ICFB layout editing, namely selecting layers, drawing rectangles and copying objects.

• These methods will be employed later in the ‘Extracting a Verilog Netlist’ section.

• If you are already familiar with the basics of ICFB, feel free to skip this section.

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ICFB Layout Basics

• In the Library Manager window, make sure the ‘tutorial’ library is selected.

• Select File -> New -> Cellview from the menu bar.

• Fill in the options as shown in the figure below.

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ICFB Layout Basics• A new layout window should pop

up. • To draw a metal1.drawing rectangle,

select the metal1.dg layer from the LSW window (click on it once).

• Then, click once on the layout editor window, and press ‘r’.

• Click once on one corner of the rectangle to be drawn, then click once on the opposite corner.

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ICFB Layout Basics• To copy the rectangle you just

created, press ‘esc’ to exit rectangle drawing mode, then click once on your rectangle to select it.

• Press ‘c’, then click once on your rectangle, then click once on the location you want it to be copied to.

• You can experiment with multiple copies by changing the ‘row’ and ‘column’ values in the copy form.

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ICFB Layout Basics

• The ‘move’ function is basically the same as the ‘copy’ function, except you press ‘m’ to activate it, instead of ‘c’.

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Connecting PADVDD and PADGND to the VDD and GND

Rings1. Open the layout view of

topchip_pads for editing.2. You should default in the

Abstract editor. You should also see another window, the OSW window pop up.

3. Click on the “AS” button of the OSW window. This will enable you to select all parts of the design (instances, nets, pins etc).

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Rings4. Click on Tools -> Layout in the layout

editing window.5. Press ctrl-f once, so that you only see the

top-layer of the design.6. Click on the inner supply ring once (you

might have to zoom in a little to make sure). Then press ‘q’. This will bring up the properties of that piece of metal.

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Rings

7. Click on the “connectivity” button once. Then, verify that the net name is vdd.

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Rings

8. Now, select metal1 (dg) from the LSW window, and place a metal1 rectangle from the VDD port of PADVDD, to the inner supply ring. Refer to Figure 29, next slide.

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Figure 29: Adding the connection from PADVDD to the VDD ring.

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Rings

9. After that is done, copy and place a few more VIA instances along the connection region of the supply ring and your metal1 rectangle, to provide a better connection. (Figure 30, next slide)

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Figure 30: Adding Extra Vias

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Rings

10. Now, repeat the process to connect the GND port of PADGND, to the GND supply ring.

11. The GND ring should be the outer ring, but you should verify that before you continue (by looking at the path properties with the ‘q’ key)

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Figure 31: Connections for VDD and GND added

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Extracting a Verilog Netlist• We need to extract a Verilog netlist out of

our placed-and-routed design to verify that the place-and-route tools did their jobs without errors.

• This Verilog netlist will be simulated using Modelsim to verify for correct functionality.

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Extracting a Verilog Netlist

• Before starting this section, change to the directory cadence/dfII.

• Then, type:

rm –rf topchip_pads.verilog

This will clear the Verilog netlister work directory.

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Extracting a Verilog Netlist1. After the copy is done, open the Layout view of

topchip_pads.

2. In the layout window, select Tools -> Layout.

3. Now, go to the CIW window (the window labeled as ‘ICFB’). In the CIW window, type:

load “skill_code/cover_pins.il”

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4. Now, type:

cpins

in the CIW window.

5. This will load the SKILL procedure ‘cpins’ into memory, and run the procedure. This procedure adds top-layer metals to pins of the I/O pads (this will be discussed further in the next few slides). Without this step, macro-cell extraction of the design will fail.

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Figure 32

YPAD port: The CPINS procedurewill automatically cover this with

an identically shaped metal1 rectangle.

Input/Output port will be covered with

an identically-shaped Metal2

(drawing) rectangle.

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Figure 33

VDD/GND port. The cpins procedure will cover this with an identically-shaped Metal1 (drawing) rectangle.

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6. Press ctrl-f to view only top-level objects. After running the cpins procedure, the layout should look like the Figure 34 (next slide).

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Figure 34

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Why do we have to cover all the YPAD and I/O ports of the pads?

• The macro-cell extractor (which we shall use in a minute) expects all ports of all cells to be completely covered with a top-level layer. If this is not done, the extractor will fail.

• In our originally imported design, the input/output ports of the pads were only partially covered by the routing metal. The YPAD portion of the pads were not covered by any top-layer metal routing at all.

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Extracting a Verilog Netlist7. Now, we need to create an extracted view of

our design. Open the layout view of topchip_pads.

8. Change the editing tool to layout editing by clicking on Tools -> Layout.

9. Click on Verify -> Extract…10. Make sure the macro cell box is checked. (Refer

Figure 35, next slide)11. Click on OK.12. The extraction process will take a few minutes

to complete.

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Figure 35: The Extractor Form

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Extracting a Verilog Netlist13. Click on Tools -> Verilog-XL. You should see a

new form called Setup Environment pop up on your screen.

14. Enter “topchip_pads.verilog” for the simulation run directory.

15. Simulate the design in: Library: tutorialCell: topchip_padsView: extracted

16. Click on OK. (sample form is on next slide)

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Figure 36: Setup Environment Form

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Extracting a Verilog Netlist17. You will see a warning message as shown below.

Ignore this warning message, since we are not going to simulate our design using Cadence. We are only going to use ICFB to extract a Verilog netlist.

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Extracting a Verilog Netlist18. The Verilog-XL Integration window will now pop up.

Click on Setup -> Netlist…19. The Verilog Netlisting Options form will pop up. Click

on the More >> button. This will enable you to see all the options for this form.

20. For the Netlist These Views field, enter: “behavioral functional symbol verilog”.

21. For the Stop Netlisting at Views field, enter: “behavioral functional symbol”.

22. Enter “vdd” and “gnd” for Global Power Nets and Global Ground Nets, respectively.

23. Make sure the netlist explicitly box is checked. Then, Click on OK.

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Figure 37: Verilog Netlisting Options Form

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Extracting a Verilog Netlist24. Back in the Verilog-XL Integration window, click on

Simulation -> Start Interactive.

25. The first time you run the verilog netlist extraction, you will get two errors regarding inherited nets for every instance you have in your design (on the order of a few thousand errors for our design). Ignore these errors - they are internal errors and should be fixed in the latest version of ICFB. Click on Simulation -> Start Interactive again; you will not get these errors the second time.

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25. Ignore the warning shown below (click on OK). We can ignore this warning because we are not going to run Verilog simulation in ICFB.

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26. A text file called verilog.inpfiles, located in the netlister work directory (cadence/icfb/topchip_pads.verilog) is created. This file tells of the location of the Verilog netlists generated.

27. Using a text editor (pico, VI etc.), view the file verilog.inpfiles.

28. The text file will tell the location of the top-level Verilog netlist – it is going to be in ihnl/cds?/netlist, where ‘?’ will be a number (it is probably going to be the number zero).

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Extracting a Verilog Netlist29. Open the file ihnl/cds?/netlist with any text

editor.30. Make sure the top-level module name is named

as topchip_pads (change it to topchip_pads if it is not already named so). The testbench that we are going to use to simulate the design expects that as the module name.

// Library - tutorial, Cell - topchip_pads, View - extracted// LAST TIME SAVED: Jul 30 14:27:00 2001// NETLIST TIME: Jul 30 14:28:39 2001`timescale 1ns / 1ns

module topchip_pads ( _csb_0_, _csb_1_, _csb_2_, _csb_3_, _csb_4_, _csb_5_, _csb_6_, _lsb_0_, _lsb_1_, _lsb_2_, _lsb_3_, _lsb_4_, _lsb_5_, _lsb_6_, clk_out, dff_out, ds_rn, inv_out, led_a, led_b,

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31. Copy the netlist file from cadence/dfII/topchip_pads.verilog/ihnl/cds?, to cadence/dfII/gate.

32. In the directory /cadence/dfII/gate, rename the netlist file to topchip_pads_icfb.v.

33. The next section of this tutorial will demonstrate how to simulate this Verilog netlist using Modelsim. However, before we go into that, let’s discuss some other issues regarding ICFB.

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Extracting a Hspice Netlist• The procedure for extracting a Hspice netlist is

similar to that of extracting a Verilog netlist, up to the Extractor form. There is only one difference for the Extractor form:

• In the Extractor form, select Flat for Extract Method instead of Macro Cell.

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Extracting a Hspice NetlistAfter running the Extractor form, follow the instructions below to generate a HSPICE netlist:

• Click on Tools -> Simulation -> Other. You should see a new menu item - Simulation – appear on your menu bar.

2. Click on Simulation -> Initialize.3. Enter “topchip_pads.hspice” for the simulation run

directory.4. Click on OK.5. Another Initialize Environment form should pop-

up. This one has the full set of options to choose from.

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Extracting a Hspice Netlist

6. In the Initialize Environment form, choose hspice for the simulator name.

7. Enter “Tutorial” for Library Name, “topchip_pads” for Cell Name, and “extracted” for View Name.

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Figure 38: Initialize Environment Form

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Extracting a Hspice Netlist8. Go back to the Layout editing window, and click

on Simulation -> Options…

9. Make sure the Use Hierarchical Netlister and Re-netlist Entire Design boxes are checked, and the others are left unchecked.

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10. Go back to the Layout editing window, and click on Simulation -> Netlist/Simulate…

11. Make sure that the netlist box is checked, and the simulate box is not. Also, check the Run in background box.

12. The remaining information should be already filled in correctly for you. Make sure they match up to that shown in Figure 39. (next slide)

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Figure 39: Netlist and Simulate Form

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13. Click on OK. Wait for a minute or so as ICFB works in the background to generate the Verilog netlist.

14. A message telling you that the netlister has succeeded should pop up after a minute or so.

15. The HSPICE netlist will be located in the directory that you specified as the run directory (for our case, cadence/dfII/topchip_pads.hspice), with the filename netlist.

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Verilog or Hspice?• For our case, Verilog is a more practical choice. • Verilog is a switch-level language, which means it

does not model any parasitics of the design. This makes simulation much faster than Hspice, which models the parasitics of the system.

• Since we started out with a VHDL file, we can assume that most of our designs will be relatively complex (e.g. having more than a few thousand transistors). Hspice simulation for designs of this scale is too time consuming.

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Verilog or Hspice?• For example, if we were to simulate our

topchip_pads design using Hspice for 150 us, it would take more than 24 hours to simulate. Verilog simulation using Modelsim takes less than 1 second.

• Conclusion: Hspice is great for detailed simulations (especially for analog systems), but for complex, purely digital systems, Verilog simulation is much more practical.

• Other simulators such as IRSim fall somewhere in between Verilog and Hspice simulators.

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DRC Verification (ICFB)

• DRC (Design Rule Check) verification checks for design rule violations. The NCSU Cadence Design Kit comes with a decent (but by no means perfect) DRC checker.

• The NCSU kit DRC checker will flag certain metal constructs that should not be flagged as errors. Refer to the next slide for a more detailed explanation.

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DRC Verification (ICFB)

The NCSU kit DRC checker will flag these as errors if the spacing is less than the minimum spacing for that metal layer, even though it should not matter because they all belong to the same net.

Metal1 shapes

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DRC Verification (ICFB)1. Open the topchip_pads layout using the layout

editor.2. Click on Verify -> DRC…3. Check Flat for checking method, and Full for

checking limit.4. Click OK.5. DRC will run (this will take a few minutes). You

will get a few thousand of DRC errors, some stemming from the false metal error detection discussed in previous slides. The other errors should be located in the pads (I/O pads seldom pass DRC)

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Figure 40: DRC Form

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Checking for Short Circuits between VDD and GND

• The easiest way to make your layout fail, is to have accidental shorts between VDD and GND.

• Shorts between VDD and GND can easily occur during manual layout procedures (e.g. when connecting the VDD and GND pads to the supply rings).

• Verilog extraction will not detect shorts between VDD and GND, because our Verilog simulating method ignores the VDD and GND nets.

• Therefore, it is essential to perform a quick check to make sure VDD and GND are not shorted.

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Checking for Short Circuits between VDD and GND

• A simple way to perform this check is to open the extracted view of the layout. In the Library Manager window, open with extracted view of topchip_nopads.

• Now, click on the VDD (or GND) ring. If you clicked on the VDD ring, you should see the VDD ring, and the VDD rails highlighted. The same goes for the GND ring.

• If you see both rings highlighted when you click on either ring, then a there is a short from VDD to GND in your layout that must be fixed.

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Exporting to CIF• Most industrial foundries use a standard

design transfer file format to send or receive design files. CIF is one such format.

1. To export to CIF, click on File -> Export -> CIF…

2. Enter ‘.’ for the run directory, “tutorial” for the library name, “topchip_pads” for the cell name, and “layout” for the view name.

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Exporting to CIF

3. Enter “cif_files/topchip_pads.cif” for the output file.

4. Check the CIF DB box.5. Click on OK. This will generate a CIF file

called topchip_pads.cif in the cadence/dfII/cif_files directory.

6. You will get some warnings (view the PIPO.LOG file) because not all layers in ICFB are translated into the CIF file. This is OK.

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Figure 41: CIF Out Form

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Modelsim

• The final step in our design flow is to simulate our ICFB-generated Verilog netlist using Modelsim.

• If the place-and-route procedures were successful, we should get the same results for this simulation as the simulation we ran with our Synopsys-generated Verilog netlist.

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Modelsim• There should be the following Verilog

files in the cadence/dfII/gate directory:

1. topchip_pads_icfb.v, which we just created,

2. tb_topchip_pads_icfb.v, the testbench file for the file above.

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Modelsim

1. Change to the qhsim directory.

2. Type swsetup modelsim.

3. Type qvlcom ../cadence/dfII/gate/libcells_icfb.v

4. Type qvlcom ../cadence/dfII/gate/topchip_pads_icfb.v

5. Type qvlcom ../cadence/dfII/gate/tb_topchip_pads_icfb.v

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Modelsim5. Type qhsim tb_topchip_pads &. This will

invoke Qhsim to simulate the testbench.• There is a .do file in the qhsim directory that

displays the signals and wave windows, adds all the top level signals into the wave window, and runs the simulation for 150 us. Activate the script by typing “do tb_topchip_pads.do” in the command window. If you open up that .do file you will find that it contains the same commands that you would type in the command window to achieve the same results.

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Modelsim

7. Verify that the results for this simulation match that of the first Verilog simulation in this tutorial, by looking at the wave window.

7/31/2001 WLTFigure 42: Simulation Results Waveform

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