Design Flow 1

8/3/2019 Design Flow 1

1/21

1

FPGA DESIGN FLOW (I)

1. Designing with Programmable Logic Devices

1.1. Design Flow

For designing digital systems using programmable logic devices (PLDs), such as

FPGA devices, computer aided design (CAD) software packages are used. These software

packages assist the designer through all the stages of the design process. Therefore, most of

the CAD packages for programmable logic devices provide the following main functions:

Description of the digital system;

Synthesis of the description, which means transforming the description into a netlistcontaining basic logic gates and their interconnections;

Functional simulation of the system based on the netlist obtained, before the imple-mentation in a specific device;

Implementation of the system in a device, by adapting the netlist for an efficientusage of the devices available resources;

Configuration (programming) of the device in order to perform the desired function.

Figure 1. Digital system design flow using programmable logic devices.


2/21

2 Structure of Computer Systems

Figure 1 illustrates the steps of the design process for digital systems using program-

mable logic devices. IP ( Intellectual Property) cores represent complex hardware modules

that are tested extensively and which can be used in various designs to reduce significantly

the design time.

Next, the main design steps are described in more details.

1.2. System Description

There are several methods for describing digital systems. Figure 2 illustrates the main

methods: by logic diagrams (schematics), by hardware description languages (HDLs), and bystate diagrams.

Traditionally, digital systems are described with schematics. For this description a

schematic editor is employed, which allows specifying the components to be used and the

way these components have to be interconnected. This method is illustrated in Figure 2. The

circuit in this figure detects the binary sequence 1010 applied at the input X. When this se-

quence is detected, the outputZwill be set to logical 1.

Figure 2. The steps of description of a digital system using schematics: (a) selecting and placing the components;(b) connecting the components; (c) adding the I/O ports.

The main steps of using logic diagrams for designing a digital system are the follow-

ing:

1. In a schematic editor, the required components are selected from a library of compo-nents. Such components can be, for instance, basic gates, multiplexers, decoders,counters, arithmetic units, etc. Depending on the device that will be used, the designer

must select a particular library of components, because there are libraries that are spe-cific to various vendors of programmable logic devices and to various device fami-


3/21

3FPGA Design Flow

lies. Devices from a specific family differ in their capacity, speed, and package used.

At this step, there is no need to specify the exact device that will be used from a cer-

tain family.

2. The components selected and placed in a schematic are interconnected through con-nection wires. The designer performs the component interconnection in order to ob-

tain the necessary configuration for a specific application.

3. The I/O ports are added and labeled. These ports define the inputs and outputs of thesystem, allowing to apply signals to the input pins of the digital system and to get the

output signals generated by the system at the output pins. The input signals are ap-plied to the inputs of the digital system via input buffers, and the output signals are

obtained from the digital system via output buffers. These buffers isolate the digital

system from the outside. In some cases, the I/O buffers are automatically added by the

CAD system.

Besides logic diagrams, another possibility for describing digital systems is using a

hardware description language. These languages are widely used today, and they are preferred

for the description of systems with high complexity, due to the following advantages:

The capability of a functional description of systems, this being a higher-level de-scription, without detailing the structure at the basic gate level. Therefore, the time

required for describing complex systems is significantly reduced.

The independence of the HDL description among different types of devices. Whilethe logic diagrams are made with library components specific to a certain device fam-

ily, HDL descriptions are completely independent of a specific device, so that the

same description can be used for implementing the system in a certain FPGA device,

but also in another type of programmable logic device, for instance, in programmablelogic array.

The possibility to modify the HDL description of a system in a simpler manner, due

to the fact that such a description also represents a documentation of the system.

Figure 3. Description in the VHDL language of the circuit illustrated in Figure 2.


4/21


There are many hardware description languages, but the most widely used languages

are VHDL (VHSICHardware Description Language) and Verilog. These languages are stan-

dardized by the IEEE. Figure 3 presents a possible description in the VHDL language of the

circuit illustrated in Figure 2.

For describing finite state machines, state diagrams are widely used. CAD systems for

designing with programmable logic devices may contain editors for state diagrams, which

allow specifying in graphical form the system states, state transitions, and output signals that

have to be generated in each state. A state diagram will be compiled by the CAD system to an

internal representation or an HDL description, which can be simulated and then used for im-plementing the state machine in a specific device. Figure 4 presents a state diagram that is

equivalent to the circuit illustrated in Figure 2 and the VHDL description of Figure 3.

Figure 4. Equivalent state diagram of the circuit represented by the schematic of Figure 2 and the VHDL descrip-tion of Figure 3.

1.3. System Synthesis

After describing the digital system, the next step in the design process is the system

synthesis. The synthesis consists in the translation of the logic diagram, HDL description, or

state diagram into a netlist. This translation is performed by a synthesis software of the CAD

system. The netlist represents a compact description of the digital system in a textual form,

where the system components, the interconnections between them and the input/output pins

are specified. The netlist is processed by other components of the CAD system for carrying

out the next steps in the designing process.

There are different formats for the netlists. The EDIF (Electronic Digital InterchangeFormat) is the most used and it represents an industrial standard. In addition to this standardformat, various formats that are specific to certain device vendors can be used. An example is

the XNF (Xilinx Netlist Format) format, which is a proprietary format of the Xilinx company.

Another possibility is to use a hardware description language as a format for the netlist. For

instance, the CAD system can use a structural representation of the designed system in ahardware description language specified by the designer.

The relationship between the logic diagram of a simple circuit and a possible format

of a netlist is illustrated in Figure 5. In the first part of the netlist, the components within the

diagram are declared, and in the second part the connections between components are speci-

fied. The names of the components are G1..G7, and the names of the connections are

N1..N10. These names are either specified by the designer, or automatically assigned by the

CAD system.In the circuit illustrated in Figure 5, there are two inverters (G1 and G2), two AND

gates with two inputs (G3 and G4), an AND gate with four inputs (G7), and two JK flip-flops

(G5 and G6). The inverters have an input pin IN, an output pin OUT, a power pin Vcc, and a

ground pin GND. Similarly, the two-input AND gates have two input pins IN1 and IN2, an

output pin OUT, a power pin and a ground pin. The flip-flops have two pins for the J and K

data inputs, a pin for the clock input C and a pin for the output Q, besides the power andground pins. For simplicity, the pins as well as power and ground signals are omitted in this

figure. A connection is represented by listing all the pins that are connected together. The in-

put signalsXand CLKare connected to the input pins with the same name of the circuit, and

the output signalZis connected to the output pin of the circuit.


5/21

5FPGA Design Flow

Figure 5. The relationship between the logic diagram and the netlist for the circuit of Figure 2.

The designer can specify various optimization criteria that can be taken into account

during the synthesis process. Examples of such options are: minimizing the number of re-

quired basic gates, achieving the maximum operating speed of the device, or minimizing the

power consumption. The designer may experiment with different optimization criteria in or-der to achieve the most suitable solution for the application.

1.4. Functional Simulation

In this stage, a simulator software is used to verify the functionality of the designed

system, before implementing it in a programmable logic device. This verification only refers

to functional aspects of the system, without considering the signals delays, which will be

known only after implementation. For functional verification, the designer provides the simu-

lator software with several combinations of the input signal values; such a combination is

called test vector. The designer can also specify the output signal values that must be generat-

ed by the system for each test vector. A sequence of test vectors applied to the inputs of the

system represents a testbench.The simulator applies test vectors to the system inputs one by one, determines the

output signals which are generated by the system, and compares them with the values of the

signals specified by the designer. When differences appear, the simulator displays messages

indicating the differences that appeared. The designer performs the required modifications of

the system description in order to correct the errors, performs the synthesis of the modified

description, and executes again the functional simulation. These steps are repeated until the

system will operate according to the requirements.

Figure 6 illustrates the way in which the input and output signals of the sequence de-

tector, used as example in the previous sections, can be visualized on the computer screen.


6/21


Figure 6. Input and output signals of the sequence detector displayed at the functional simulation of the circuit.

1.5. Technology Mapping

The next steps in the synthesis process perform the implementation of the designed

system in a programmable logic device. The first step of the implementation is technology

mapping. This step consists of a series of operations which process the netlist and adapt it to

the characteristic features and available resources of the device used for implementation. The

operations performed in this step vary depending on the design system. The most common

operations are: adapting to the physical resources of the device, optimization, and checking

the designing rules (for instance, testing if the number of I/O pins available in the device isexceeded). During this step, the designer selects the type of the programmable logic device

that will be used, the package of the integrated circuit, the speed, and other options specific to

the particular device.

After executing the operations of the technology mapping step, a detailed report is

generated with the results obtained. Besides the error and warning messages, usually a list is

created with the resources used within the device.

Figure 7 illustrates the technology mapping step for the circuit used as example. You

may notice that the circuit schematic has been modified for using D-type flip-flops instead ofJK flip-flops, and the AND gates have been replaced with NAND gates. We mention that

these transformations are performed on the netlist obtained after the synthesis step, and the

schematic of Figure 7 is only illustrative.

Figure 7. Illustration of the technology mapping step for the circuit of Figure 2.

1.6. Placing and Routing

These operations are performed when an FPGA device is used for implementation.For designing with other PLDs, the equivalent operation is called fitting. Placing is the


7/21

7FPGA Design Flow

process of selecting particular modules or logical blocks of the programmable logic device

which will be used for implementing the various functions of the digital system.Routing con-

sists in interconnecting these logical blocks using the available routing resources of the de-

vice.

Most of the CAD systems perform the placing and routing operations automatically,

such that the user does not have to know the details of the device architecture. Some systems

allow the expert users to manually place and route of some critical parts of the digital system

in order to obtain higher performance.

Figure 8 illustrates the placing and routing of the netlist obtained after the technologymapping of the circuit used as example. After selecting the logical blocks to be used for the

circuit implementation, these are configured for implementing some parts of the circuit. For

interconnecting the signals generated by the various logical blocks, the available routing re-

sources are used. These resources are indicated in the figure by horizontal and vertical lines.

The used inputs and outputs of the logical blocks are connected to the routing lines through

programmable connection points (represented by circles in the figure), and the routing lines

are interconnected with programmable switches.

Figure 8. Illustration of the placing and routing steps for the circuit of Figure 7.

The routing and placing operations may require a long time for execution in case of

complex digital systems, because complex operations are required to determine and configure

the required logical blocks within the programmable logic device, to interconnect them cor-

rectly, and to verify that the performance requirements specified during the design are en-

sured.

1.7. Timing Analysis

CAD software packages for designing digital systems usually contain a software

called timing analyzer, which can provide information about the signal delays. This informa-

tion refers to the delays introduced by logical blocks, as well as to the delays introduced by


8/21


interconnections. The analyzer can display this information in different modes, e.g., by sort-

ing the connections in the descending order of signal delays. The designer may use the infor-

mation about signal delays to perform a new simulation of the system, where to take into ac-

count these delays. This operation through which the simulator is provided with detailed in-

formation about the signal delays is called back-annotation.

1.8. Device Configuration or Programming

The configuration operation refers to programmable logic devices based on volatile

static RAM memories and consists of loading the configuration information to the devicememory. Theprogramming operation refers to programmable logic devices based on nonvo-

latile memories (such as the devices that contain antifuses). This operation is executed simi-

larly with the configuration operation, but the configuration information is also retained after

the voltage supply is interrupted.

At the end of the placing and routing operations, a file is generated that contains all

the necessary information for configuring the device. This information refers to the configura-

tion of logic blocks as well as to the specification of interconnections between the logicblocks. The file where this information is written contains a bitstream, each bit indicating the

closed or open state of a switch. Programmable logic devices contain a large number of such

switches. A switch can be implemented by a transistor or a memory cell. A bit of 1 from the

bitstream will determine the closing of a switch, and therefore establishing a connection. The

bits from the configuration file are arranged in a specific format in order to make a correspon-

dence between a certain bit and the corresponding switch.

The content of the configuration file is transferred to the programmable logic device,

usually located on a printed circuit board or development board together with other devices.

The device switches close or remain open depending on the bit values in the configuration

bitstream.Because a volatile memory is used, the device must be configured again after each

interruption of the voltage supply. The configuration information can be kept in a nonvolatile

memory, and the device can be automatically configured from this nonvolatile memory whenthe voltage supply is applied.

The configuration or programming can be performed from a computer using several

types of interfaces: a parallel interface, such as the standard or the enhanced parallel port; a

serial interface, such as SPI (Serial Peripheral Interface); the USB (Universal Serial Bus)interface. The board with the programmable logic device should contain a connector for the

particular interface being used.

Another possibility is to use a special cable and a configuration methodology pro-

posed by the JTAG (Joint Test Advisory Group) organization. This methodology, also known

asBoundary-Scan, has been standardized by the IEEE and ANSI institutes as the 1149.1 stan-

dard, and represents a set of design rules which facilitate the configuration or programming of

devices, their testing and debugging. One end of the JTAG cable connects to the parallel or

USB interface of the computer, and the other end of the cable connects to a number of fivespecial pins on the development board. The configuration information is transferred serially to

the programmable logic device. This type of cable also allows testing the implemented digitalsystem by reading some information (signal values or the contents of memory locations) from

the programmable logic device during operation, transferring this information to the comput-

er, and displaying them on the screen.

Figure 9 presents the connection of a JTAG cable in JTAG mode (or Boundary-Scan

mode) to a development system containing one or more programmable logic devices. The

connection wires connect at one end to the JTAG pins of the cable, and at the other end to the

corresponding JTAG pins of the development board. This type of cable can be used for confi-guring a single programmable logic device as well as for several devices connected in a

boundary-scan chain.


9/21

9FPGA Design Flow

Figure 9. Connecting a JTAG cable to a development system inBoundary-Scan mode.

Table 1 presents the naming and the meaning of JTAG signals used for configuring

programmable logic devices.

Table 1. Naming and meaning of the JTAG signals used for configuring programmable logic devices.

Name Meaning

VCC Supply Voltage supply (5 V, 3.3 V or 2.5 V)GND Ground Reference for the electrical ground

TCK Test Clock Clock signal for programmable logic devices

TDO Test Data Out Signal for reading data from programmable logic devices

TDI Test Data In Signal for transferring instructions and data to programmable logic devices

TMS Test Mode Select Signal decoded by the JTAG controller for controlling the operations

1.9. System Verification and Debugging

In this last step of the design process, the operation of the digital system is verified in

real conditions. An improper operation can be due to not complying with the design specifica-tions, with the specifications of the device used for implementation, it can be related to the

signal delays etc. Debugging can be simplified if the device is configured to contain somespecial modules which allow reading the signal values during operation and transferring this

information to the computer, using a JTAG cable and special software for displaying thewaveform of the desired signals.

2. The Xilinx ISE Design Suite Environment

The Xilinx ISE Design Suite environment integrates all the tools required for design-

ing digital systems with Xilinx programmable logic devices, in particular, with FPGA devic-

es. This environment provides a graphical interface and tools that can be launched from thegraphical interface or from the command prompt. These tools allow passing through all the

steps of the design flow, from system description, through implementation, device configura-

tion, and in-circuit verification of the implemented system.The main components of the Xilinx ISE design environment are described in the fol-

lowing sections.

2.1. Project Navigator Graphical Interface

Project Navigator represents the graphical interface of the Xilinx ISE design envi-

ronment. This interface manages the design files and allows running processes to perform the

various steps of the design flow, from design creation to programming the selected Xilinx

device. The Project Navigatorscreen contains four main areas. The first is the toolbar area,which provides convenient access to frequently used menu commands.

The Design panel area provides access to three sections. The first section is

represented by the View pane, which allows selecting a design phase in order to control thesource files displayed in the second section, calledHierarchy pane. This pane contains all the


10/21


source files of the project. The third section of the Design panel area is the Processes pane,

which allows running the processes required in the various phases of the design flow. The

source file selected determines the processes available in the Processes pane.

The workspace area allows viewing and editing the design using various tools, and

provides access to reports in theDesign Summary section. The Transcriptwindow offers the

possibility to view output logs, messages, errors, and warnings as they are generated.

2.2. Design Entry Modules

Design entry is the first step in the design flow. During this step, source files arecreated in order to represent the design. The top-level design source file can have one of the

following formats:

Hardware description language, such as VHDL or Verilog;

Schematic (SCH file);

Embedded processor (XMP file);

EDIF or NGC/NGO file (if the design should be synthesized outside of the ProjectNavigator).

For designs with an HDL or schematic file as the top-level source file, lower-level

source files can have several formats, including HDL files, schematic files, IP cores, and

netlists. For designs with an EDIF or NGC/NGO netlist as the top-level source file, EDIF or

NGC/NGO files are the only source file types allowed in the project.

2.2.1. HDL Editor

The HDL editor allows creating a file in a hardware description language, such as

VHDL or Verilog, which describes the behavior and structure of the design. Using HDLs of-

fers the following advantages:

The HDL allows using a synthesis tool to translate the design to gates. Synthesis de-creases design time by eliminating the need to define every gate. In addition, the syn-

thesis tool can automate the process, using several encoding styles for state machinesor performing automatic I/O buffer insertion during optimization, resulting in greater

efficiency.

The design functionality can be verified early in the design process by simulating theHDL description. Design simulation at the gate-level before implementation allows

evaluating the architectural and design decisions.

The code can be retargeted to different architectures.

Large designs are easier to handle with HDL tools than schematic tools.

2.2.2. Schematic Editor

The schematic editor allows creating a visual representation of the designed system.

The editor can be used for the top-level design file, the lower-level design files, or both.

A schematic can represent a top-level design, and the lower-level modules can be

created using any of the following source types: HDL files, CORE GeneratorIP cores,Archi-

tecture WizardIP cores, or schematic files.

Schematics can also be used to define the lower-level modules of the design. If the

top-level design file is a schematic file, then a schematic symbol must be created from each

lower-level module and then it must be instantiated in the top-level schematic file. If the top-

level design file is an HDL file, an HDL instantiation template must be created from theschematic, and then the template must be instantiated in the top-level HDL file.


11/21

11FPGA Design Flow

All schematic files are ultimately converted to either VHDL or Verilog structural

netlists before being passed on to the synthesis tool during the synthesis step.

2.2.3. CORE Generator Software

The CORE Generatorsoftware reduces design time by providing access to paramete-

rized IP (Intellectual Property) cores for Xilinx FPGA devices. The software provides a cata-log of architecture specific, domain specific (embedded, connectivity, DSP), and product spe-

cific (automotive, consumer electronics, military equipments, communications) IP cores.

These user-customizable IP cores range in complexity from commonly used modules, such as

memories and FIFO memories, to system-level building blocks. Using these IP cores can re-

duce significantly the design time.

The CORE Generatorsoftware includes the following types of IP cores:

Building blocks: memories and FIFO memories, arithmetic operators (adder, accumu-lator, multiplier, complex multiplier, etc.);

Debug and verification: ChipScope Pro Integrated Controller, Integrated Logic Ana-

lyzer, Virtual Input/Output;

Connectivity: standard bus interfaces, such as PCI and PCI-X;

DSP functions.

2.3. Synthesis Module

After design entry and optional simulation, the next step in the design flow is the syn-

thesis. The Xilinx ISE Design Suite environment includes the Xilinx Synthesis Technology

(XST) software, which synthesizes VHDL or Verilog designs to create Xilinx-specific netlist

files, known as NGC files. Unlike outputs from other tools, which consist of an EDIF filewith an associated NCF constraints file, NGC files contain both logical design data and con-

straints. The NGC file is then accepted as input to the translate step of the design implementa-tion process.

Figure 10 shows the types of files used by the XST software.

Figure 10. Types of files used by the XST software.

In addition to NGC files, the XST software also generates the following outputs: a

synthesis report, an NGR file with the RTL (Register Transfer Level) schematic, and a tech-nology schematic. The synthesis report contains the results from the synthesis run, including

an area and timing estimation. The RTL schematic is a representation of the design before the

optimization using generic symbols, such as adders, multiplexers, counters, gates. This sche-

matic is generated after the HDL synthesis phase of the synthesis process. The technology

schematic is a representation of an NGC file using logic elements optimized to the target ar-


12/21


chitecture or technology. This schematic is generated after the optimization phase of the syn-

thesis process.

Figure 11 illustrates each of the steps performed by the XST tool during synthesis.

Figure 11. Synthesis steps performed by the XST software.

First, a parsing of the HDL code is performed, when XST checks whether the HDL

code is correct and reports syntactic errors. If there are no syntax errors, the HDL synthesis is

performed. XST analyzes the HDL code and attempts to infer specific design building blocks

or macros (such as multiplexers, memories, adders, subtractors) for which it can create effi-

cient technology implementations.To reduce the amount of inferred macros, XST performs a resource sharing check that

leads to a reduction of the area and an increase in the clock frequency. At this step, the XST

software recognizes the Finite State Machines (FSMs) independent of the modeling style

used. To create the most efficient implementation, XST uses the optimization criterion that

has been specified (area or speed) to determine the FSM encoding algorithm that will be used.

The last step of the synthesis is the low-level optimization. XST transforms inferred macros

and general logic into a technology-specific implementation.

2.5. Modules for Entering Design Constraints

The design constraints are instructions given to the FPGA implementation tools to

direct the design processes and help improving the performance. Constraints specify place-ment, implementation, signal direction, and timing considerations for timing analysis and for

design implementation.

The design constraints are usually placed in the User Constraints File (UCF), but they

may exist in the HDL code or in a synthesis constraints file.

2.5.1. Types of Constraints

Each type of constraint serves a different purpose and is recommended in different

situations. The most commonly used types of constraints are the following:

Timing constraints;

Placement constraints;

Synthesis constraints.

Timing constraints describe the timing performance requirements of the design. Tim-

ing constraints are usually specified globally, but can also be specified for individual paths.

Global constraints include period constraints for each clock signal (PERIOD), setup times for

each input (OFFSET_IN), and time specifications from the clock edge at the input pin until

data becomes valid at the output pin (OFFSET_OUT). Timing constraints can be entered us-

ing the Create Timing Constraints process in the Project Navigatorgraphical interface.


13/21

13FPGA Design Flow

Placement constraints control the mapping and placement of symbols defined in the

netlist to the resources of the device used for implementation. These constraints can be de-

fined for each type of logic element of the FPGA device. Individual logic gates are mapped

into CLB (Configurable Logic Block) function generators before the constraints are read, and

therefore cannot be constrained. In a constraints file, each placement constraint acts upon one

or more symbols. Every symbol in a design carries a unique name, which is defined in the

input file.

Synthesis constraints instruct the synthesis tool to perform specific operations. Syn-

thesis constraints control how the synthesis tool processes and implements FPGA resources,such as state machines, multiplexers, and multipliers, during the HDL synthesis and low-level

optimization steps. Synthesis constraints also allow control of register duplication and fanout

control during global timing optimization.

2.5.2. The Constraints Editor

Using the Constraints Editor tool is the recommended method for entering timing

constraints in most situations. After synthesis, the editor lists all the elements and nets in the

design. The editor allows grouping the common elements and nets as well as specifying theconstraints for specific nets.

2.5.3. The PlanAhead Software

The PlanAhead software is a design and analysis tool that allows entering placement

constraints that control I/O pin and logic assignments, global logic placement, and area group

assignment. The PlanAhead software provides a comprehensive environment for analyzing

the design for connectivity, density, and timing. After analyzing the design, the placement

constraints can be applied in order to guide the implementation tools toward improved results.

These constraints may include location constraints to lock specific logic elements into specific

sites on the device, or area constraints to constrain a group of logic elements within a specific

area of the device.In addition, the circuit performance can be improved by analyzing the design RTL

source files, synthesized netlists, and implementation results. The PlanAhead software in-

cludes a hierarchical data model that enables an incremental design capability referred to asDesign Preservation. By partitioning the design, unchanged modules can be preserved, there-

fore providing consistent results and in some cases reduced runtimes.

2.5.4. Using a Text Editor

Using a text editor is recommended for modifying design constraints in order to meet

changing timing requirements. A text editor can also be used for creating multiple versions of

the constraints file in order to test how different constraints affect the design.

The names of objects in the design, such as net names, must exactly match the namesas they exist in the source design netlist, either uppercase or lowercase.

To organize constraints, multiple UCF files can be assigned to a top-level module inthe design. When the design is implemented, the constraints from all of the UCF files are ap-

plied. Constraints are applied in order, starting with the first UCF file added to the project.

3. Design Example

This section presents a design example that is based on the VHDL language and uses

the Xilinx ISE Design Suite environment for implementation. The example illustrates the

steps of the FPGA design flow and demonstrates the main capabilities of the Xilinx ISE soft-

ware package.


14/21


3.1. Design Description

The design implements a real-time clock maintaining time in hours, minutes andseconds, together with the ability to set the time. The design is targeted for the Spartan-3E

Starter board and it uses the liquid crystal display of this board. In the real-time clock design

example, the system clock is generated by the 50 MHz on-board oscillator.

The input signals of the real-time clock are the following:

clk: System clock with a frequency of 50 MHz.

rst: Initializes the clock and resets the time to 12:00:00.

mode: Puts the clock in time setting mode. By repeatedly pressing the mode button, itis possible to set the hour, the minute, and the second.

up: Increments the hour, minute, or second in time setting mode.

down: Decrements the hour, minute, or second in time setting mode.

The output signals of the clock are the following:

sf_d(3:0): Represents the data bus for the LCD display used to display the time.

sf_ce0: Disables the Intel StrataFlash memory on the Spartan-3E board, since the fourdata lines of the LCD display are shared with the StrataFlash memory.

lcd_e,lcd_rs, lcd_rw: Represent the control signals for the LCD display.

The design consists of the following functional blocks:

debounce: Implements a simple debounce circuit for the mode, up, and down inputsignals.

control: Module that implements a state machine for generating the control signalsrequired for the operation of the real-time clock.

time_cnt: Module that updates the clock during normal operation as well as in timesetting mode. This module has six 4-bit outputs, representing the digits of the clock.

lcd_ctrl: Module that performs the initialization and controls the operation of theLCD display.

3.2. Creating a New Project

Start the Project Navigatorsoftware of theXilinxISE Design Suite package by select-

ing StartAllProgramsXilinx ISE Design Suite 12.4ISE Design ToolsProject

Navigator. To create a new project using theNew Project Wizard, perform the following op-

erations.

1. In the Project Navigatorwindow, select FileNew Project. TheNew Project Wi-zarddialog window is displayed.

2. In theName field, enter the name of the project (for instance, clock).

3. In theLocation field, click the button to browse to the folder where the projecthas to be created (this should be a subfolder of the D:\Student\folder), and then select

the OKbutton.

4. Verify that HDL is selected in the Top-level source type field, and select theNextbut-ton. The Project Settings page of theNew Project Wizarddialog window is displayed.

5. Select the following values in the Project Settings page:

Product Category: General Purpose

Family: Spartan3E


15/21

15FPGA Design Flow

Device: XC3S500E

Package: FG320

Speed: -4

Synthesis Tool: XST (VHDL/Verilog)

Simulator: ISim (VHDL/Verilog)

Preferred Language: VHDL6. Click theNextbutton. In the Project Summary page, click the Finish button to com-

plete the project creation.

3.3. Design Entry

In this step of the design flow, the source files of the design example will be added to

the project, syntax errors will be corrected, a new VHDL module will be created, and it willbe connected to the other modules.

3.3.1. Adding Source Files

The VHDL source files of the design examples are available in the clock.zip archiveon the laboratory web page. Add the source files to the project as follows:

1. Extract the files from the clock.zip archive to a temporary folder.

2. Select ProjectAdd Copy of Source or click on theAdd Copy of Source buttonon the left bar of theDesign panel. Browse to the temporary folder, select all the .vhdfiles, and click the Open button.

3. In theAdding Source Files dialog window, verify that in the Association field of thefiles All is selected, and in the Library field work is selected (Figure 12). Click the

OKbutton. This will copy the source files to the project folder. If the files are already

copied to the project folder, the Add Source option can be used instead of the Add

Copy of Source option.

4. In theHierarchy pane, expand the clockentry to display the design units of the top-level module.

TheHierarchy pane displays the design units currently added to the project, with the

associated entity name. Each design unit is represented in the following form: instance_name

entity_name architecture_name (file_name).

Figure 12.Adding Source Files dialog window.

3.3.2. Correcting Syntax Errors

When source files are added to the project and when they are saved, the syntactical

correctness of the files is automatically checked. Possible error messages are displayed in theConsole andErrors panels.


16/21


The time_cnt.vhd file contains syntax errors that must be corrected. To correct the

errors in the source file, perform the following operations.

1. In the Console or Errors panel, click the file name in the first error message. Thesource code is displayed in the text editor window with a yellow arrow next to the

line with the error.

2. Browse to the beginning of the sec_cnt process that contains the error. Review thisprocess and notice that one of the end if statements is written as endif. Correct the

error and then save the file by selecting FileSave or by clicking the Save but-ton. The error messages in the Console panel should disappear.

3. To detect other possible syntax errors, in theHierarchy pane select the time_cnt mod-ule, in the Processes pane expand the Synthesize XSTprocess if it is not already ex-panded, and double-click the Check Syntax process. This launches the XST (Xilinx

Synthesis Technology) tool for syntax checking. The time_cnt module is compiled and

several error messages are displayed in the Console panel. These messages indicate

that the + and operators are not defined for operands of type std_logic_vector.

4. To correct the errors, browse to the beginning of the file and modify the second usestatement by replacing the NUMERIC_STD package with the STD_LOGIC_UNSIGNED

package. Save the file and launch the Check Syntax process again. Now the compila-

tion should be completed successfully.

3.3.3. Creating a New VHDL Module

With the Xilinx ISE design environment, new VHDL modules can be created using

the ISE text editor and theNew Source Wizard. The new VHDL modules are connected to the

top-level module through instantiation and are implemented with the rest of the modules.

In the initial design of the real-time clock, the mode, up, and down input signals are

connected directly from push-buttons on the Spartan-3E board to the control module. A

new VHDL module will be created for debouncing the mode, up, and down input signals. To

create the VHDL module, perform the steps described next.

1. Select ProjectNew Source or click on theNew Source button on the left bar oftheDesign panel. TheNew Source Wizardis launched.

2. In the Select Source Type page, select VHDL Module.

3. In the File name field, enter debounce and select theNextbutton.

4. In the Define Module page, enter the following ports into the Port Name field: clk,d_in, and q_out. Change the direction of the q_outport to out and select the Next

button.

5. The Summary page displays a description of the module. Select the Finish button toopen the skeleton of the new module in the ISE text editor. This skeleton contains the

entity and architecture declarations of the debounce module.

3.3.4. Adding a Language Template

The ISE text editor provides VHDL and Verilog language constructs for simulation

and synthesis, representing widely used logic components. The Debounce Circuitsynthesis

construct will be used in the design example. Perform the following operations to select the

required template and to add this template to the source file of the debounce module.

1. SelectEditLanguage Templates or click theLanguage Templates button.


17/21

17FPGA Design Flow

2. Expand the VHDL language templates, expand Synthesis Constructs, expand CodingExamples, expand Misc, and then select the template called Debounce circuit. The

template content is displayed in the right pane of the screen.

3. Select the debounce.vhd file and position the cursor under the begin statement inthis source file.

4. Return to theLanguage Templates window, right-click on theDebounce circuittem-plate, and select Use in File. The template will be inserted at the cursor position.

5. Close theLanguage Templates window.

6. In the debounce.vhd file, move the line with the signal definitions so that it is placedbetween the architecture and begin keywords.

7. Remove the reset logic, which is not used in this design, by deleting the five lines be-ginning with if (= '1') and ending with else, and delete the first

end if line.

8. Replace with clk in the process sensitivity list and in the if statement.

9. Save the file by selecting FileSave or by clicking the Save button.

10. In theHierarchy pane, select the debounce module.

11. In the Processes pane, double-click the Check Syntax process. Verify that the syntaxcheck is completed successfully. Correct any errors if necessary.

3.3.5. Instantiating the VHDL Module

The debounce VHDL module created previously will be instantiated in the top-level

module and it will be connected to the existing modules of the design. To instantiate and to

connect the debounce module, perform the steps described next.

1. In theHierarchy pane, double-click the clock.vhd file to open it in the editor window.

2. Insert a component declaration for the debounce module after the architecturekeyword. You may copy the entity declaration of this module from its source file andtransform it into a component declaration.

3. In the clock.vhd file, declare three new signals of type std_logic after the lastsignal statement and name them mode_d, up_d, and down_d. These signals will

represent the outputs of the debouncing modules that will be instantiated in the top-

level module.

4. Instantiate the debounce component three times after the begin keyword and con-nect the ports as illustrated in Figure 13.

Figure 13. Instantiation of the debounce component.

5. In the instantiation statement of the control component, change the mode, up, and

down signals to mode_d, up_d, and down_d, respectively. By these changes, the

mode, up, and down input signals will be debounced before connecting them to the

control component.


18/21


6. Save the clock.vhd file by selecting FileSave or by clicking the Save button.In theHierarchy pane, notice that the instances of the debounce component are add-

ed to the design hierarchy (Figure 14).

7. While the clock module is selected in the Hierarchy pane, double-click the CheckSyntax process in the Processes pane. Correct any possible syntax errors.

Figure 14. Design hierarchy shown in theHierarchy pane.

3.4. Synthesizing the Design

After the design entry step, the design will be synthesized with the XST software tool,which has been used previously only for syntax checking. This tool will compile the VHDL

files into a netlist optimized for the target architecture. After synthesizing the design, loca-

tions will be assigned to the I/O pins with the PlanAhead software, which will create a user

constraints file (UCF). The netlist file and the UCF file will be used later by the Xilinx im-

plementation tools.

3.4.1. Entering Synthesis Options

Synthesis options allow to modify the behavior of the synthesis tool in order to make

optimizations according to some options. The most used options are to specify optimizationsbased on either area or speed. Other options are to specify the maximum fanout of a flip-flop

output, to specify the desired frequency of the circuit, or to preserve the hierarchy of the de-

sign.

By default, the design hierarchy is not preserved by the synthesis tool. However, pre-

serving the hierarchy may be advantageous for large designs, because the optimization is per-formed on separate modules, and therefore the complexity is reduced and the processing time

required by the synthesis tool is decreased.

Perform the operations described next to generate a hierarchical netlist and to view

the synthesis report.

1. In theHierarchy pane, select the top-level clock module if it is not already selected.

2. In the Processes pane, right-click on the Synthesize XST process and select theProcess Properties option. The Process Properties dialog window opens with the

Synthesis Options category selected by default.

3. In the Value field of the Keep Hierarchy property, choose the Yes option.

4. Click the OKbutton to close the Process Properties dialog window.

5. In the Processes pane, double-click the Synthesize XSTprocess.

6. When the synthesis is finished, select theDesign Summary (Synthesized) tab, and thenselect Synthesis Reportunder theDetailed Reports category.

7. In the synthesis report, read the Device utilization summary section to find out the

resources of the FPGA device required for the design.


19/21

19FPGA Design Flow

8. In the synthesis report, find the Timing Summary section. Make a note of the esti-mated maximum frequency of the design.

9. With the cursor in the synthesis report, select Edit Find or press Ctrl-F. In theFind field type fanout and press the Enter key. Press repeatedly the Find the next

phrase button and determine what is the maximum fanout and what is the re-

source with this fanout.

10.Close the synthesis report.

Large fanouts can cause difficulties during the routing phase. Therefore, the XST syn-thesis tool tries to limit the fanout by duplicating gates with large fanout or by inserting buf-

fers. These buffers will be protected against logic optimization during the implementation

phase by defining a KEEP attribute in the netlist.

To reduce the maximum fanout and to observe the effect of this reduction on the syn-

thesis process, perform the operations described below.

1. In the Processes pane, right-click on the Synthesize XSTprocess and select ProcessProperties.

2. In the Process Properties dialog window, select theXilinx Specific Options category.In the Value field of theMax Fanoutproperty, change the default value of500 to 50.

3. Click the OKbutton to close the Process Properties dialog window.

4. While the clock module is selected in the Hierarchy pane, in the Processes panedouble-click the Synthesize XSTprocess to re-synthesize the design.

5. When the synthesis is finished, in the Processes pane double-click the Design Sum-mary/Reports process.

6. Open the synthesis report and determine what is the fanout of the resource that hadthe maximum fanout in the previous report.

7. Close theDesign Summary window.

3.4.2. Viewing the RTL or Technology Schematic

The XST synthesis tool can generate a schematic representation of the synthesis re-

sult. Two forms of schematic representations can be generated. The RTL schematic is the re-

presentation of the VHDL code before the optimization step. The technology schematic is the

representation of the design mapped to the target device.To view a schematic representation of the design, perform the steps presented next.

1. In the Processes pane, double-click the View RTL Schematic process.

2. If the Set RTL/Tech Viewer Startup Mode dialog window appears, select the Startwith a schematic of the top-level blockoption and click the OKbutton. The symbol ofthe top-level clock module will be displayed.

3. Double-click inside the symbol of the clock module to view its internal structure.

4. Use theZoom Out button to view a larger area of the schematic.

5. Double-click inside one of the components to view its internal structure. Click the

Previous Schematic button to return to the schematic of the top-level module.

6. Close the schematic window.


20/21


3.4.3. Assigning I/O Pin Constraints

The PlanAhead software will be used to assign constraints to the I/O pins of the de-

sign. The PlanAhead software writes the constraints to the project UCF file, which will be

used later for design implementation.

Assigning constraints to I/O pins can be performed either before synthesis or aftersynthesis. Whenever possible, it is recommended to perform this operation after synthesis,

because the design then contains the information required for the design rule checks per-

formed by the PlanAhead software.

To assign constraints to the I/O pins of the design, perform the steps described next.

1. In theHierarchy pane ofProject Navigator, select the top-level clock module.

2. In the Processes pane, expand the User Constraints entry, and double-click on theI/OPin Planning (PlanAhead) Post-Synthesis process.

3. In theISE Project Navigatordialog box, click the Yes button to create a UCF file andadd it to the project.

4. The PlanAhead software is launched, which automatically creates a project and readsthe design files generated by synthesis. The Welcome to PlanAheadwindow is dis-played, which provides a link to the PlanAhead user guide and suggests chapters toread from this documentation. Select the Close button to close this window.

5. In the upper left part of the PlanAhead screen, select the I/O Ports tab, expand theSF_D entry, and expand the Scalar ports entry (Figure 15).

Figure 15. TheI/O Ports tab in the PlanAhead software screen.

6. In the I/O Ports panel, select the SF_D[0] signal. In the I/O Port Properties panel,make sure that the General tab is selected, enter R15 to the Site field, and click theApply button. Then select the Configure tab. In the I/O Standardfield, select

LVCMOS33, in theDrive Strength field select 4, and for the other options keep their

default values. Click theApply button to assign these properties.

7. Repeat the previous step to assign constraints to the remaining I/O pins, according toTable 2.


21/21

21FPGA Design Flow

Table 2. I/O pin constraints.

Signal Site I/O Standard Drive Strength Pull Type

clk C9 LVCMOS33

rst H13 LVTTL PULLDOWN

mode D18 LVTTL PULLDOWN

up V4 LVTTL PULLDOWNdown K17 LVTTL PULLDOWN

LCD_E M18 LVCMOS33 4

LCD_RS L18 LVCMOS33 4

LCD_RW L17 LVCMOS33 4

SF_CE0 D16 LVCMOS33 4

SF_D[0] R15 LVCMOS33 4

SF_D[1] R16 LVCMOS33 4

SF_D[2] P17 LVCMOS33 4

SF_D[3] M15 LVCMOS33 4

8. Select FileSave Design to save the I/O pin constraints to the UCF file.

9. Select File

Exitto close the PlanAhead software. Confirm to exit in the dialog box.10.In theHierarchy pane, notice that a .ucf file has been added to the design hierarchy.

Select this file. In the Processes pane, expand the User Constraints line and double-

click theEdit Constraints (Text) process to open the .ucf file created. Review the file

to confirm that the constraints have been set correctly.

11.Close the .ucf file.

4. Applications

4.1. Answer the following questions:

a. What are the advantages of using hardware description languages for designing digi-

tal systems?

b. What is the main operation performed in the design synthesis step?

c. What is technology mapping?

d. What are the operations performed at design placement and routing?

e. What are the operations performed by the XST tool during design synthesis?

f. What are the main types of design constraints?

4.2. Perform the steps described in Section 3 for the design example of the real-time

clock.

Design Flow 1

Documents

Transcript of Design Flow 1