Design and Performance of the 5 GHz Waveform Digitizing Chip DRS3 for the MEG Experiment

Design and Performance of the 5 GHz Waveform Digitizing Chip DRS3 for the MEG Experiment

Stefan RittPaul Scherrer Institute, Switzerland

many

2 Nov. '07 IEEE/NSS Honolulu 2007 2

Trends in DAQ

• Higher event rates pile-up

• Baseline estimation event-by-event removal of 60 Hz noise

• Particle identification by signal shape from PMTs

• Usage of FADCs instead of ADCs/Discriminators/TDCs

• Problems:

• expensive

• high power requirement

• low density

Moving average baseline

hit

s


Switched Capacitor Array

Shift RegisterClock

IN

Out

“Time stretcher” GHz MHz“Time stretcher” GHz MHz

Waveform stored

Inverter “Domino” ring chain0.2-2 ns

FADC 33 MHz

Keep Domino wave running in a circular fashion and stop by trigger Domino Ring Sampler

(DRS)

Keep Domino wave running in a circular fashion and stop by trigger Domino Ring Sampler

(DRS)


Folded Layout

Linear inverter chain causes non-linearity


Simple inverter chain

1 0 0 0 0 0

0 0 0 0 00

1 0

0 0 0 0 00

1

0

10 0 0

1 1 1 1

1 1 1 1 1

1 1 1 1 1

1 1 1 1 1 1

11

1 0 0 0 0 0

0 0 0 0 00

0

0 0 0 0 00

0

0 0 0

1

1

1

0 0 00

0 0 0 0

0 0 0 0

00

0 0 0 0 00

00


Design of Inverter Chain

PMOS > NMOS

PMOS < NMOS


“Tail Biting”

enable

1 2 3 4

1

2

3

4

speed


Stopping

enable

1 2 3 4

1

2

3

4

speed

time

enable


Stop Schematics

D Q D Q D Q

WE

RES RES RES

1 2 3

1

2

3

WE


Sample readout

0.2 pF 20 pF

DRS1DRS1Tiny signal

TemperatureDependence

~kT

DRS2DRS2I

DRS3DRS3


ROI readout mode

readout shift register

Triggerstop

normal trigger stop after latency

Delay

delayed trigger stop

Patent pending!

33 MHz

e.g. 100 samples @ 33 MHz 3 us dead time

(2.5 ns / sample @ 12 channels)

e.g. 100 samples @ 33 MHz 3 us dead time

(2.5 ns / sample @ 12 channels)


DRS3

• Fabricated in 0.25 m 1P5M MMC process(UMC), 5 x 5 mm2, radiation hard

• 12 ch. each 1024 bins,6 ch. 2048, …, 1 ch. 12288

• Sampling speed 10 MHz … 5 GHz

• Readout speed 33 MHz, multiplexedor in parallel

• 50 prototypes receivedin July ‘06

CHANNEL 0IN0+IN0-

CHANNEL 1IN1+IN1-

CHANNEL 2IN2+IN2-

CHANNEL 3IN3+IN3-

CHANNEL 4IN4+IN4-

CHANNEL 5IN5+IN5-

CHANNEL 6IN6+IN6-

CHANNEL 7IN7+IN7-

CHANNEL 8IN8+IN8-

CHANNEL 9IN9+IN9-

CHANNEL 10IN10+IN10-

CHANNEL 11

STOP SH IFT REGISTER

READ SHIFT REGISTER

IN11+IN11-

W SRCLKSRIN

W SRO UTSRLO AD

RSRLO AD

WR

ITE

SH

IFT

RE

GIS

TE

R

DENABLEDW R ITEDSPEEDDM ODE

DO MINO WAVE CIR CUIT

DG ND

AGND

DVDD

AVDD

DTAP A0 A1 A2 A3

M UX

EN

AB

LE

M UXOUT /OU T0

OU T1

OU T2

OU T3

OU T4

OU T5

OU T6

OU T7

OU T8

OU T9

OU T10

OU T11

BIAS

RO FS

SSROUT

RSRCLKRSRRST

RSROU T

DRS3 Test Results


Sampling speed

PLL

ReferenceClock (1-4 MHz)

Vspeed

~200 psec~200 psec

• Unstabilized jitter: ~70ps / turn

• Temperature coefficient: 500ps / ºC

• Unstabilized jitter: ~70ps / turn

• Temperature coefficient: 500ps / ºC

f SA

MP[G

Hz]

DSPEED [V]0 0.5 1 1.5 2 2.5

0

1

2

3

4

5

6

30°C

50°C

R. Paoletti, N. Turini, R. Pegna, MAGIC collaborationR. Paoletti, N. Turini, R. Pegna, MAGIC collaboration


Bandwidth + Linearity

Readout chain shows excellent linearity from 0.1V … 1.1V @ 33 MHz reaout

Analog Bandwidth is currently limited by high resistance of on-chip signal bus, will be increased significantly with DRS4

AM

PL

ITU

E [

dB

]

FREQUENCY [MHz]1 10 100

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

1

2

AM

PL

ITU

E [

dB

]

FREQUENCY [MHz]1 10 100

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

1

2

450 MHz (-3dB)NO

NL

INE

AR

ITY

[m

V]

ANALOG OUTPUT [V]

0 0.2 0.4 0.6 0.8 1 1.2-2

-1

0

1

2

ROFS = 0.95 VBIAS = 0.70 V

NO

NL

INE

AR

ITY

[m

V]

ANALOG OUTPUT [V]

0 0.2 0.4 0.6 0.8 1 1.2-2

-1

0

1

2

ROFS = 0.95 VBIAS = 0.70 V

0.5 mV max.


Signal-to-noise ratio

“Fixed pattern” offset error of 5 mV RMScan be reduced to 0.35 mV by offsetcorrection in FPGA

SNR:

1 V linear range / 0.35 mV = 69 dB (11.5 bits)

“Fixed pattern” offset error of 5 mV RMScan be reduced to 0.35 mV by offsetcorrection in FPGA

SNR:

1 V linear range / 0.35 mV = 69 dB (11.5 bits)

AN

AL

OG

OU

TP

UT

[V

]

BIN NUMBER0 200 400 600 800 1000

0.48

0.49

0.5

0.51

0.52

Crosstalk from trigger signal

OC

CU

RE

NC

E

OUTPUT VOLTAGE [V]0.48 0.49 0.5 0.51 0.520

20

40

60

80

100

120

140

160

180

200

OC

CU

RE

NC

E

OUTPUT VOLTAGE [V]0.48 0.49 0.5 0.51 0.520

20

40

60

80

100

120

140

160

180

200

OffsetCorrection


“Residual charge” problem

R

“Ghost pulse”2% @ 2 GHz

“Ghost pulse”2% @ 2 GHz

After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulses

After sampling a pulse, some residual charge remains in the capacitors on the next turn and can mimic wrong pulsesSolution: Clear before write

write clear


VPC & USB boards

PSI general purposeVME board with 2 PPC cores

DRS2DRS2

DRS3DRS3USB interface

board

32

ch

an

nels

in

pu

t

14-bit flash ADCAD9248

14-bit flash ADCAD9248


Availability

32-channel 65 MHz/12bit digitizer

“boosted” by DRS4 chip to 5 GHz

32-channel 65 MHz/12bit digitizer

“boosted” by DRS4 chip to 5 GHz

an

alo

g fro

nt e

nd

DRSFADC12 bit

65 MHz

MU

X FPGA

trigger

LVDS

SRAM


Conclusions

•3000 Channels with DRS2 chip run-ning in MEG experiment since 2006

•The DRS3 chip solves temperature dependence of DRS2 chip, DRS4 solves ghost pulse problem

•The DRS4 chip will be available in larger quantities beginning 2008

http://midas.psi.ch/drs

Backup Slides


Complete Domino Cells

DQ

RES

DQ

RES

DQ

RES

Sampling Cell 1 Sampling Cell 2 Sampling Cell 3

VspeedEnable

Write

Start

Domino Cell 1 Domino Cell 2 Domino Cell 3

Design and Performance of the 5 GHz Waveform Digitizing Chip DRS3 for the MEG Experiment

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Transcript of Design and Performance of the 5 GHz Waveform Digitizing Chip DRS3 for the MEG Experiment