Design and Performance of Beam Test Electronics for the PHENIX Multiplicity Vertex Detector

C. L. Britton, Jr., W. L. Bryan, M. S. Emery, M. N. Ericson, M. S. Musrock, M. L. Simpson, M. S. Smith, J. W. Walker, A. L. Wintenberg, G. R. Young

Oak Ridge National Laboratory, Oak Ridge, Tennessee 3783 1-6006

M. D. Allen, L. G. Clonts, R. L. Jones, E. J. Kennedy, R. S. Smith The University of Tennessee, Knoxville, Tennessee 37996-2 100

J. Boissevain, B. V. Jacak, D. Jaffe, J. S. Kapustinsky, J. Simon-Gillo, J. P. Sullivan, H. Van Hecke, N. Xu

Los Alamos National Laboratory, Los Alamos, New Mexico 87545

‘The submitted manuscript has been authored by a contractor of the U.S. Government under contract No. DEACO5-96OR22464. Accordingly, the U. S. Government retains a nonexclusive, royalty-free license to publish or reproduce the published form of this contribution, or allow others to do so, for U.S.Govemment purposes.”

DISCLAIMER

This report was prepared as an account of work sponsored by an agency of the United States Government. Neither the United States Government nor any agency thereof, nor any of their employees, makes any warranty, express or implied, or assumes any legal liability or responsi- bility for the accuracy, completeness, or usefulness of any information, apparatus, product, or process disclosed, or represents that its use would not infringe privately owned rights. Refer- ence herein to any specific commercial product, process, or service by trade name, trademark, manufacturer, or otherwise does not necessarily constitute or imply its endorsement, recom- mendation, or favoring by the United States Government or any agency thereof. The views and opinions of authors expressed herein do not necessarily state or reflect those of the United States Government or any agency thereof.

*Research sponsored by the U.S. Department of Energy and performed at Oak Ridge National Laboratory, managed by Lockheed Martin Energy Research Corporation for the U.S. Department of Energy under Contract No. DE-AC85-960R22464.

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1 '

Design and Performance of Beam Test Electronics for the PHENIX Multiplicity Vertex Detector

C. L. Britton, Jr., W. L. Bryan, M. S. Emery, M. N. Ericson, M. S. Musrock, M. L. Simpson, M. C. Smith, J. W. Walker, A. L. Wintenberg, G. R. Young

Oak Ridge National Laboratory, Oak Ridge, Tennessee 3783 1-6006

M. D. Allen, L. G. Clonts, R. L. Jones, E. J. Kennedy, R. S. Smith The University of Tennessee, Knoxville, Tennessee 37996-2100

J. Boissevain, B. V. Jacak, D. Jaffe, J. S. Kapustinsky, J. Simon-Gillo, J. P. Sullivan, H. Van Hecke, N. Xu

Los Alamos National Laboratory, Los Alamos, New Mexico 87545

Abstract The system architecture and test results of the custom

circuits and beam test system for the Multiplicity-Vertex Detector (MVD) for the PHENIX detector collaboration at the Relativistic Heavy Ion Collider (RHIC) are presented in this paper. The final detector per-channel signal processing chain will consist of a preamplifier-gain stage, a current-mode

This paper presents measurements of the prototype circuits including the preamplifier-discriminator, analog memory unit ( M U ) , analog-digital converter (ADC) and heap manager for the MVD detector front-end electronics (FEE). The system was run in the BNL AGS facility as a fixed-target experiment. The electronics, however, were run as simultaneous read-write with a sampling rate of 400 ns.

summed multiplicity discriminator, a 64-deep analog memory (simultaneous read-write), a post-memory analog correlator, and a 10-bit 5 ps ADC. The Heap Manager provides all timing control, data buffering, and data formatting for a single 256-channel multi-chip module (MCM). Each chip set is partitioned into 32-channel sets. Beam test (16-cell deep memory) performance for the various blocks will be presented as well as the ionizing radiation damage performance of the 1.2 p n-well CMOS process used for preamplifier fabrication.

I. INTRODUCTION The requirements of low-power consumption, small

physical area, a channel count of approximately 34,000, and flexible data handling make the MVD of the PHENIX detector at RHIC one of the most challenging of the PHENIX detector subsystems [ 13. Additional requirements, which include a minimum 1O:l system signal-to-noise ratio for a single Minimum Ionizing Particle (MIP) signal (which results in noise less than 2500 electrons rms) and discrimination of a 0.25 MIP event for the per-channel multiplicity discriminator, offer a challenging set of problems.

The MVD is a 2-layer barrel detector comprised of 112 strip detectors and 2 disk-shaped end caps comprised of 24 wedge-shaped pad detectors. It is a clam-shell design, constructed in two halves to close about the beam pipe. The main physics goals of the detector are to provide a multiplicity measurement to the PHENIX level 1 trigger, and to reconstruct the collision vertex to better than 2 mm.

'Research sponsored by the U.S. Department of Energy and performed at Oak Ridge National Laboratory, managed by Lockheed Martin Energy Research Corporation for the U.S. Department of Energy under Contract No. DE-AC05-960R22464.

II. ELECTRONICS ARCHITECTURE A block diagram of the electronics is shown in Figure 1.

This includes the preamplifier, discriminator, current-sum output, analog memory-correlator and ADC. The system controller, or Heap Manger, is not shown but will also be discussed.

Analog A-D Preamp Memory correiator converter

To +data

i bus

Current sum out

Figure 1: System block diagram.

The electronics will be mounted on a MCM. Each MCM will be connected to a 256 channel strip detector and will contain 8 preamplifier-discriminator chips and 8 analog memory-ADC chips. Each of these chips will contain 32 channels of its respective functions. In addition, the MCM will contain the Heap Manager chips and associated control logic. In the prototypingheam test round, we have fabricated an 8-channel die set.

A. Preamplijier The preamplifier, shown in Figure 2, utilizes a PMOS

cascode amplification stage for low l/f noise. The input device operates in weak inversion with a drain current of 100 PA. Versions of this design are presently being used by not only

PHENIX, but also by the PHOBOS detector collaboration [2] (also at RHIC), and the Naval Research Laboratories (NRL) for Germanium spectroscopy [3]. The PHENIX version employs a wideband gain stage after the preamplifier. The resultant power dissipation of the PHENIX preamplifier is approximately 1.2 mW. The circuit is fabricated in 1.2 pm n-

where n is the subthreshold slope and g, is the device transconductance. If we add a feedback resistor across the feedback capacitor, the transfer function becomes

= (1 + scf Rf )(I+ sC,Rb) well CMOS and has an 85 @channel pitch. 0

(3)

W L = 2500u/1.2u

Vdd

Detector Amplification, (diode, coupling level-shifting, capacitor, bias resistor) buffering

Figure 2: Preamplifier and detector block diagram.

At low frequencies, equation (3) clearly predicts less noise than (1) because Cf << C,. While these equations give some insight into the effects of the components, they are difficult to use when including all effects such as the I/f noise of the transistors, finite open-loop gain of the preamplifier, etc.

The correlated sampling present in the analog memory reduces the low frequency noise, but does nothing to effect the preamplifier directly. Unexpected noise spikes due to detector pickup or power line variations can have the effect of overloading the preamplifier and driving the output of the preamplifier into a nonlinear region. In order to understand the contribution of the feedback resistor to noise at the output of the preamplifier, the circuit was simulated in HSPICE and the signahoise for a variable feedback resistor was plotted. The detector capacitance was 10 pF, Cc was equal to 200 pF, and Rb was as previously stated. The signahoise ratio for the preamplifier both before ( S / N direct) and after ( S / N DCS) an ideal double-correlator are plotted as a function of the feedback resistor in Figure 3.

The preamplifier has a dynamic range of 75 fC which corresponds to a full scale output voltage of 1.5V and a signal range of 19 MIPS. This range was chosen because the expected charge deposited in a single strip in one reset period (1 ms) for a Si-Cu beam is 7 MIPS. A factor of at least two above this maximum was chosen to ensure linear operation for even unforeseen operating conditions. The integral non- linearity over a 12.5 MIP input range (-1V) is +0.3% and -0.1%, most adequate for the application. The measured preamplifier risetime is 29 ns at 0 pF and 41 ns at 10 pF versus simulations of 26 ns and 44 ns respectively. The measured double-correlated rms noise (225 ns difference time) of th8 preamplifier is 590e at 0 pF and 910 e at 10 pF (slope = 32 e/pF) versus simulations of 524 e and 11 12 e respectively. We have experienced such discrepancies with our noise simulations before and are presently in the process of deriving new noise models.

30 -

;i;

01 I 1 .00E+O6 1 .00E47 1.00E48 1.00E49

Feedback resistor (ohms)

The detector, shown in dotted line, has an ac-coupling capacitor equal to approximately 150 pF and a bias resistor equal to approximately 5 Ma. This configuration, when combined with the preamplifier, exhibits a noise transfer function equal to

(1)

2i,, (ignoring flicker noise) is defined as [4]

Figure 3: Signalhoke vs. Feedback resistor.

The results indicate that a feedback resistor between 10 MQ and 100 MQ results in approximately the same SIN ratio for both correlated sampling and direct output. This range is an acceptable compromise between having good double-correlated performance and limiting the effects of low- frequency noise pickup. For the beam test, the feedback switch, which is a pmos FET, was biased on at all times and adjusted for minimum overall system noise. The final version of the preamplifier has a long channel (W=1.8 pm, k 2 0 0 pm) pmos FET in the feedback which will allow an appropriate adjustment of the feedback time constant.

1 .

B. Discriminator The multiplicity discriminator [5] block diagram is

presented in Figure 4. Each time an input step greater than the threshold setting is detected, a fixed-value current source is switched to a summing node. The current-mode outputs of 256 discriminators are summed in this manner to produce a multiplicity output whose amplitude is proportional to the number of fued discriminators. The resultant current sum is buffered by a transimpedance amplifier and input to a flash ADC for the multiplicity count.

The design allows triggering at every beam crossing (108 ns) with no deadtime and has a total power consumption of approximately 500 pW/channel.

Discriminator

controlled

Common threshold

Current source

P From other current switches

output sum

Figure 4 Block diagram of the discriminator.

C. Analog memory-correlator The final analog memory unit (AMU) is a 64-cell deep,

voltage-write-voltage-read, deadtime-less topology with a power dissipation of approximately 1 mW/channel. The beam test electronics utilized a 16-cell deep prototype version thqt had the same cell design and output amplifier as the larger unit. The memory is followed by an analog correlator that performs the double-correlated sampling. Both direct memory output and correlated output are available to the subsequent analog-digital converter (ADC). The memory reading and writing is addressed externally from the Heap Manager. The read and write logic decoders are completely independent to allow simultaneous read-write (deadtime-less) operation. A block diagram of the memory is presented in Figure 5. Due to time constraints in the software development, the correlator was not used in the beam test. The data was subtracted off line.

From

Analog Memory Analog Correlator

Figure 5: Memory block diagram.

The memory was originally fabricated a 1.2 pm nwell process. Recently, tests were performed to measure the amount of dielectric absorption [6] present in the particular process. Dielectric absorption (DA) will cause a trigger latency-dependent degradation of the charge stored on the memory storage capacitor. Some testing by other collaborators [7] had indicated the process exhibited significant DA. Our testing revealed that there is indeed some DA at approximately the 10-11 bit level. This is a marginal effect for the MVD subsystem but it could be a serious problem for the calorimeters and other subsystems within the detector. Because we are planning to use this memory for all subsystems, the decision was made to fabricate in another 1.2 p n-well process. This process was tested by both ORNL and Nevis Laboratory and found to have DA equal to or less than 1 part in 4000 (12 bits).

D. Analog-digital converter To allow easy maintainability and take advantage of the

economics of scale, the readout architecture of the subsystems within the PHENIX detector have been designed to resemble one another. A universal AMU/ADC chip that will be used in several PHENIX subsystems is currently being designed. The architecture of the chip is 32 channels of 64-deep AMU and 32 channels of switchable 9-, lo-, 11-, 12-bit ADC. Due to dynamic range requirements, the MVD ADC will be set for 10-bit operation. The ADC has an adjustable dynamic range of up to 4.5 Volts. The prototype chip implements an eight channel version of the ADC [8, 91. The circuit dissipates 1.19 mW/channel for the 8-channel prototype at 100 MHz clock frequency (5 ps conversion time for 10-bit conversions).

E. Heap Manager A generic Heap Manager has been developed [ 10, 111 for

use in all PHENIX detector subsystems using analog memory for front-end signal buffering d k n g the Level-1 trigger decision; however, due to the reduced size and power requirements for the MVD, this functional block has been partitioned such that the minimum required electronics are physically located near the detectors. The remaining circuitry resides at the ends of the detector subassembly as interface cards to the data collection modules (DCMs). Figure 6 is a block diagram of the MVD Heap Manager in context of the overall Front-End Module (FEM) showing the basic functional blocks and system partitioning.

The Heap Manager controls all on-board functions including AMU address list management and control (for asynchronous read and write operations), correlator timing, Level-1 buffering associated with trigger latency, ADC precharge/acquisition/conversion control, data handling, command interpretatiotdexecution, and timing.

This function has been implemented using commercially available RGAs allowing in-circuit programmability for future functional upgrades. A multi-function serial interface is used for FPGA programming, calibration setup, diagnostics and monitoring.

* * *

The beam test heap manager was implemented in two Xilinx field-programmable gate arrays (FPGA) and ran at a 10 MHz internal clock which produced a 2.5 MHz beam clock sampling frequency. The new version of the circuit is also implemented in two Xiiinx FPGAs but runs as high as 63 MHz internal clock which will generate up to a 16 MHz beam clock sampling frequency, more than adequate for the 10 MHz needed by PI-IENIX.

other, and a downstream coincidence paddle. The two scintillators defined the trigger. The trigger rate to strip rate ratio was about 50:l. The test setup is pictured in Figure 7.

The electronics die were packaged in commercial ceramic packs and interconnected on a standard G-10 printed circuit board (PCB). The silicon detectors were both outer layer types, with 7.5 cm long strips. The kapton cable(s) connecting the strips to the readout boards was 19 cm long.

Timing & Control Bu

Data Path

Figure 6: Front-end module including heap manager.

m. RADIATION EFFECTS Due to the proximity of the detector to the interaction

region, some significant (-10 mad) radiation exposure is expected. The desire to utilize a standard non-radiation hardened 1.2 p CMOS process, resulted in the need for radiation effect measurements to be performed to ensure acceptable circuit operation. Versions of the preamplifier, analog memory and ADC circuits have been irradiated to various doses of ionizing radiation. The process appears to be sufficient for doses to 75 kRad for most functions [12]. The major problem lies in the leakage current of the input protection for the preamplifier. Devices used for protection networks begin to exhibit increased leakage current due to radiation-induced decrease in the nmos threshold voltage. A protection pad that utilizes a pmos device for positive excursion protection and a p-implant substrate diode with channel stops for negative excursion protection was developed. The resultant input pad leakage is now approximately that of a completely unprotected preamplifier with its associated transistor junctions. Tests with 400 keV x- rays have revealed the pad shows no degradation for a 10-20 m a d dose.

Iv. BEAM TEST RESULTS Each element of the front-end has been prototyped in

8-channel versions. We recently instrumented 32 channels each of two MVD silicon strip detectors, and tested them at the AGS at BNL in a secondary beam line that provided a minimum ionizing beam flux. The setup consisted of an upstream finger scintillator that covered the instrumented section of the strips, the two strip detectors, one behind the

Figure 7: Beam test electronics.

The test successfully demonstrated the operation of the entire electronics chain [ 131. We measured the signal-to-noise ( S / N ) on the output of the preamplifier to be about 15:l. Figure 8 shows the ADC distribution from a single silicon strip. The shape of the Landau is well resolved, though the absolute separation of signal to noise is not as good as we would like. The ratio of the Landau peak to the one-sigma width of the residual noise distribution is about 6:1, whereas our goal is to achieve 10: 1. Part of the noise width is due to a known problem in the version of the ADC we used for the test which had a noisy ramp. This problem has been solved in a subsequent layout. The greater noise contribution is, we feel, due to coupling of the fast clocks on the PCB into the ADC. In particular, we feel the problem is exacerbated by the long trace lengths that carry these signals.

V. FUTUREWORK The platform that we will use in the MVD is a multichip-

module. The process we will employ is the High Density Interconnect (HDI) process. In this process, wells are milled out of an alumina substrate, and the bare die are placed into these wells so that the surface of the die are coplanar with the unmilled surface of the substrate. A polyimide layer is placed over the substrate and holes are laser drilled through the layer, directly over the die bond pads, and the contact is made by aluminization. Multiple layers are built up of trace, power and ground. We have laid out a four layer MCM. The first layer routes the analog signal traces. The second layer is a power

* . * c

plane split between analog and digital. The third layer routes the digital traces. The final layer is a split ground plane. The 32 channel prototype is functionally equivalent to the chain we used in the beam test, with the exception that we will use the improved ADC. The-clock traces are several times shorter than on the PCB counterpart. This fact, together with the direct contacts to the die pads, and the excellent analog to digital isolation that can be achieved in the HDI process, should significantly reduce the system noise. The MCM design is complete and ready for fabrication. It will be tested

E 120

5 -

1w

8 0 -

60

40-

20

O

iter this year.

-

-

-

-

0-

Figure 8: ADC distribution from a single silicon strip.

VI. CONCLUSIONS <

The circuits for the PHEN-m MVD have been presented. The readout consists of preamplifier, ‘multiplicity discriminator, analog memory, ADC and Heap Manager controller. Prototypes of the major functional blocks have been fabricated and tested and the entire system put into a beam test. The radiation tolerance of the CMOS has been tested and appears to be adequate.

VIT. ACKNOWLEDGMENT The authors would like to thank Norma Hensley and Teri

Subich for their help in preparing this manuscript and Chen Yi Chi and Bill Sippach for their help in dielectric absorption testing.

VIII. REFERENCES [l] C. L. Britton, Jr., W. L. Bryan, M. S. Emery, M. N. Ericson,

M. S . Musrock, M. L. Simpson, J. W. Walker, A. L. Wintenberg, F. Plasil, G. R. Young, M. D. Allen, L. G. Clonts, E. J. Kennedy, R. S . Smith, J. Boissevain, B. V. Jacak, J. Kapustinsky, J. Simon-Gillo, J. P. Sullivan, H. Van Hecke, and N. Xu, “Multiplicity-Vertex Detector Electronics for Heavy-Ion

Detectors,“ Proceedings of the First Workshop on Electronics for LHC, Lisbon, Portugal, September 1995, pp. 84-87.

[2] M. Plesko and B. Wadsworth, ‘Test Results for the PHOBOS-1 Preamp Chip,” MIT-LNS Electronics Facility, Tech. Note 94-8, August 1994.

[3] R. A. Kroeger, W. N. Johnson, R. L. Kinzer, J. D. Kurfess, StIoderhees, M. D. Allen, G. T. Alley, C. L. Britton, Jr., L. C. Clonts, M. N. Ericson, and M. L. Simpson, “Charge Sensitive Preamplifier and Pulse Shaper Using CMOS Process for Germanium Spectroscopy,” IEEE Trans. Nucl. Sci., Vol. 42, No.

[4] C. Toumazou and D. G. Haigh (eds.), Analogue IC Design: The Current-Mode Approach, Peter Peregrinus, Ltd., London

[SI R. Smith, et al., “A Discriminator with a Current-Sum Multiplicity Output for the PHENIX Multiplicity Vertex Detector,” Presented at the 1996 Nuclear Science Symposium, Anaheim, CA, Nov. 5-8, 1996.

[6] J. W. Fattaruso, et al., “The Effect of Dielectric Relaxation on Charge-Redistribution A/D Converters,” IEEE Journal of Solid- State Circuits, Vol. 25, No. 6, pp. 1550-1561.

[7] C. Y. Chi and W. Sippach, Nevis Laboratory, private communications.

[8] A. L. Wintenberg, T. C. Awes, C. L. Britton, L. G. Clonts, M. S. Emery, M. N. Ericson, F. Plasil, M. L. Simpson, J. W. Walker, G. R. Young “Monolithic Circuits for the WA98 Lead Glass Calorimeter,” Proceedings of the 1994 NSS, Norfolk, VA, Oct.

M. S . Emery, et al., “A Multichannel ADC for use in the PHENIX Detector,” Presented at the 1996 Nuclear Science Symposium, Anaheim, CA, Nov. 5-8,1996.

[lo] M. N. Ericson, M. S . Musrock, C. L. Britton, Jr., J. W. Walker, A. L. Wintenberg, G. R. Young, and M. D. Allen, A Flexible Analog Memory Address List Manager for PHENIX,” IEEE Trans. Nucl. Sci., Vol. 43, No. 3, June 1996 (1629-1633).

[ 111 M.N. Ericson, “Development of a Front-End Controller/Heap Manager for PHENIX,” Presented at the 1996 Nuclear Science Symposium, Anaheim, CA, Nov. 54,1996.

[I21 C. L. Britton, Jr., A. L. Wintenberg, G. R. Young, T. C. Awes, M. Womac, E. J. Kennedy, R. S. Smith, “Post-Radiation Memory Correction Using Differential Subtraction for PHENIX,“ IEEE Trans. Nucl. Sci., Vol. 43, No. 3, June 1996

[ 131 J. S. Kapustinsky et al., “A Multiplicity Vertex Detector for the PHENIX Experiment at RHIC,“ submitted to proceedings of the 4th International Conference on Position Sensitive Detectors, Manchester, UK, Sept. 9-13, 1996.

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(1564-1569).