Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering,...

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esign and Implementation of VLSI System (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison Wesley – Rabaey Pearson]

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Transcript of Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering,...

Page 1: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Design and Implementation of VLSI Systems(EN0160)lecture03

Sherief RedaDivision of Engineering, Brown University

Spring 2008

[sources: Weste/Addison Wesley – Rabaey Pearson]

Page 2: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Recap

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+

nMOS pMOS

Page 3: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

3-input NANDs

Page 4: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Series-Parallel Combinations

Page 5: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

What are the transistor schematics of the NOR gate?

Page 6: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

And-Or-Inverter (AOI) gate

Page 7: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Transmission gate

Page 8: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Tri-state inverter

Page 9: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Multiplexer (MUX)

Page 10: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Latch design

Page 11: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Flip-flop (edge triggered) design

Page 12: Design and Implementation of VLSI Systems (EN0160) lecture03 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Summary

• Introduction to VLSI systems and the semiconductor industry

• Basic overview of pn junctions and MOS transistors

• Designing digital logic gates using transistors

• HW1 is out and the due date is Wednesday February 6


S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture10: Delay Estimation Prof. Sherief Reda Division of Engineering, Brown University.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture10: Delay Estimation Prof. Sherief Reda Division of Engineering, Brown University.

Another Example: MIPS From the Harris/Weste book Based on the MIPS-like processor from the Hennessy/Patterson book.

Another Example: MIPS From the Harris/Weste book Based on the MIPS-like processor from the Hennessy/Patterson book.

Design and Implementation of VLSI Systems (EN1600) lecture05 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

Design and Implementation of VLSI Systems (EN1600) lecture05 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Weste/Addison.

San Antonio Weste Es Inventory as of MARCH 2014

San Antonio Weste Es Inventory as of MARCH 2014

Design and Implementation of VLSI Systems (EN0160) lecture03

Design and Implementation of VLSI Systems (EN0160) lecture03

Weste N.H.E., Harris D. CMOS VLSI design (3ed., Pearson AW, 2005).pdf

Weste N.H.E., Harris D. CMOS VLSI design (3ed., Pearson AW, 2005).pdf

Sherief Reda Division of Engineering, Brown University ...scale.engin.brown.edu/classes/EN0291S40F06/lecture04.pdf · Division of Engineering, Brown University Fall 2006. 2 • Static

Sherief Reda Division of Engineering, Brown University ...scale.engin.brown.edu/classes/EN0291S40F06/lecture04.pdf · Division of Engineering, Brown University Fall 2006. 2 • Static

HOW TO A ETTE WESTE...HOW TO A ETTE WESTE 6 need be deployed quickly, or Squarespace, which bundles design tools with content management options. After selecting a CMS, the look and

HOW TO A ETTE WESTE...HOW TO A ETTE WESTE 6 need be deployed quickly, or Squarespace, which bundles design tools with content management options. After selecting a CMS, the look and

Principles of CMOS VLSI Design - A Systems Perspective (Neil Weste & Kamran Eshragian)

Principles of CMOS VLSI Design - A Systems Perspective (Neil Weste & Kamran Eshragian)

Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.

Design and Implementation of VLSI Systems (EN1600) lecture04 Sherief Reda Division of Engineering, Brown University Spring 2008 [sources: Sedra/Prentice.

HOKCHHAY TANN, HENG ZHAO, and SHERIEF REDA, Applications ... · Hokchhay Tann, Heng Zhao, and Sherief Reda. . A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional

HOKCHHAY TANN, HENG ZHAO, and SHERIEF REDA, Applications ... · Hokchhay Tann, Heng Zhao, and Sherief Reda. . A Resource-Efficient Embedded Iris Recognition System Using Fully Convolutional

Reconfigurable Computing S. Reda, Brown University Reconfigurable Computing (EN2911X, Fall07) Lecture 07: Verilog (3/3) Prof. Sherief Reda Division of.

Reconfigurable Computing S. Reda, Brown University Reconfigurable Computing (EN2911X, Fall07) Lecture 07: Verilog (3/3) Prof. Sherief Reda Division of.

Reducing Test Application Time Through Test Data Mutation Encoding Sherief Reda and Alex Orailoglu Computer Science Engineering Dept. University of California,

Reducing Test Application Time Through Test Data Mutation Encoding Sherief Reda and Alex Orailoglu Computer Science Engineering Dept. University of California,

Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation

Design and Implementation of VLSI Systems (EN0160) Lecture 13: Power Dissipation

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources:

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Prof. Sherief Reda Division of Engineering, Brown University Spring 2007 [sources:

Design and Implementation of VLSI Systems (EN0160) Lecture 27: Datapath Subsystems 1/3

Design and Implementation of VLSI Systems (EN0160) Lecture 27: Datapath Subsystems 1/3

Design and Implementation of VLSI Systems (EN0160) Lecture 20: Circuit Design Pitfalls

Design and Implementation of VLSI Systems (EN0160) Lecture 20: Circuit Design Pitfalls

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 27: Datapath Subsystems 1/3 Prof. Sherief Reda Division of Engineering,

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 27: Datapath Subsystems 1/3 Prof. Sherief Reda Division of Engineering,

Weste n.h.e., Harris d. Cmos Vlsi Design (3ed., Pearson Aw, 2005)(Isbn 0321269772)(600dpi)(t)(o)(1003s)_ee

Weste n.h.e., Harris d. Cmos Vlsi Design (3ed., Pearson Aw, 2005)(Isbn 0321269772)(600dpi)(t)(o)(1003s)_ee

Technical drawing (by: Sherief Elmetwali)

Technical drawing (by: Sherief Elmetwali)