Design and Implementation of a Sigma Delta ADC

By:

Moslem Rashidi, March 2009

Introduction

The first thing in design an ADC is select architecture of ADC that is depend on parameters like

bandwidth, resolution, power and so on. First we can see a brief comparison between different

architectures of analog to digitals.

Integrating ADCs

Integrating ADCs provide high resolution and can provide good line frequency and noise

rejection. The integrating architecture provides a novel yet straightforward approach to

converting a low bandwidth analog signal into its digital representation. They are found in many

portable instrument applications, including digital panel meters and digital multi-meters.

Flash ADCs

Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert

an analog signal to a digital signal. They are suitable for applications requiring very large

bandwidths. However, flash converters consume a lot of power, have relatively low resolution,

and can be quite expensive. This limits them to high frequency applications that typically cannot

be addressed any other way. Examples include data acquisition, satellite communication, radar

processing, sampling oscilloscopes, and high-density disk drives.

Pipeline ADCs

The pipelined analog-to-digital converter has become the most popular ADC architecture for

sampling rates from a few mega samples per second (MS/s) up to 100MS/s+, with resolutions

from 8 to 16 bits. They offer the resolution and sampling rate to cover a wide range of

applications, including CCD imaging, ultrasonic medical imaging, digital receiver, base station,

digital video (for example, HDTV), xDSL, cable modem, and fast Ethernet.

SAR ADCs

Successive-approximation-register (SAR) analog-to-digital converters (ADCs) are frequently the

architecture of choice for medium-to-high-resolution applications, typically with sample rates

fewer than 5 megasamples per second (Msps). SAR ADCs most commonly range in resolution

from 8 to 16 bits and provide low power consumption as well as a small form factor. This

combination makes them ideal for a wide variety of applications, such as portable/battery-

powered instruments, pen digitizers, industrial controls, and data/signal acquisition.

Sigma Delta ADCs

Sigma Delta analog-to-digital converters (ADCs) are used predominately in lower speed

applications requiring a trade off of speed for resolution by oversampling, followed by filtering

to reduce noise. Sigma Delta converters are common in Audio designs, instrumentation and

Sonar. Bandwidths are typically less than 1MHz with a range of 12 to 18 true bits.

With above introduction we decided to design our ADCs with Sigma-Delta architecture, in

below we see how we select details:

Design Issues

Sigma-Delta ADCs benefit from both noise-shaping and oversampling to give an optimum trade-

off between speed and resolution. Because of using integrator in a feedback, noise is shaped in a

high pass filter that improves SNR after filtering. Figures of architecture and power spectrum of

first order Sigma-Delta modulator are shown in Figure 1 and Figure 2.

Figure1. First order sigma-delta modulator

Figure2. Spectra of sigma-delta modulator

As we know most critical block of ∑Δ modulator is the DAC as the shaping and the feedback

does not help in reducing its error. A simple way to overcome the linearity requirement is to use

a DAC with 2-level voltages or 1-bit quantization. Then it encourages us to use 1-bit ADC and

DAC in our design.

The equation of SNR for first order modulator is:

SNR=6.02n’+1.76-5.17+9.03 log2(OSR)

For 1-bit then k=1

n’=log2(k)=log2(1)=0, if SNR=70db => OSR>256

Then it needs OSR>256 that is fairly large for our design with some limitation in hardware

implementation like op-amp settling time, also in practice output spectrum for first order is in

some cases, poorly shaped and has large tones that could fall in the signal band that makes it

unpleasant to use.

Better performances and features are secured by using second-order modulator as shown in

Figure3. In Figure4 we can see first order and second order effect on output spectra.

Figure3. Second order sigma-delta modulator

Figure4. Effect of first and second order on noise spectrum

The equation of SNR for second order ∑Δ is: SNR=6.02n’+1.78-12.9+15.05.log2(OSR)

That with 1-bit ADC for SNR=70dB we should have OSR=64.

When we apply a step signal to input of op-amp it takes time to stable output at desired that

called settling time. In Figure4 this matter is shown. Then for a correct operation of circuit next

condition should be verified:

tsettle < Ts/2 => fs < 1/(2tsettle) here tsettle=7ns => fs < 71.4MHz

According to specifications fB=1MHz then fs=64MHz and the op-amp can satisfy this

requirement and can use fs=64MHz as sample frequency with OSR=64.

Figure5. Step response of op-amp

Another parameter that should be verified is open loop gain of op-amp that according to equation

(6.33) from Maloberti’s book:

π(A0+2) >> OSR => A0 > 18 here we have A0=60dB or 1000 times that is verified.

In later sections we are trying to simulate second-order Sigma-Delta ADC ideally and then with

non-ideal effects:

Ideal simulation:

In the first place we simulate ideal case of design without any non-linearity, Figure6 shows the

model of ideal case in simulink, it uses two delayed integrators whose gains are 0.5 and 2 for the

first and second respectively that in addition to the benefit of an extra clock period available for

the feedback loop implementation, realizes appropriate signal and noise transfer functions and,

also, obtains a scaling of the first integrator that we will see in non-linearity effects.

Figure6. Ideal model in simulink

Amplitude of input is -4dB and sample rate is 1024*64.The output of integrators and spectra of

output are shown below, the value of SNR with perfect filter is 71dB also value of SFDR is

86dB.

Figure7. Output of first integrator

Figure8. Output of second integrator

Figure9. Spectra of output in ideal modeling

After ideal case we are going to simulate non-idealities on Sigma-Delta modulator like sampling

jitter, KT/C noise and operation amplifier parameters (finite gain, finite bandwidth, slew rate and

saturation voltage).

Modeling Clock jitter:

In a real situation sampling is affected by uncertainty in the clock. The effect of clock jitter on

Sigma-Delta ADC can be described by computing its effect on the sampling of the input signal.

Sampling clock jitter results in non-uniform sampling and increases the total error power in the

quantizer output. The error introduced when a sinusoidal signal with amplitude A and frequency

fin is sampled at an instant which is in error by an amount δ is given by:

x(t+δ)-x(t)≈ 2π fin δ A cos(2π fin t)= δ dx(t)/dt

We simulate above equation by below model. Sampling uncertainty δ is supposed to be a

Gaussian random process then we use Uniform Random Number that its deviation can be set to :

Δτ= A 2πfin Cos(2πfint) δ , with assumption δ=0.1 Ts => Δτ= π *0.1*10/65536= 4.8e-5

Figure10. Clock jitter modeling

Figure11 shows simulation result with 10% clock jitter. It moves noise floor in the signal band

but the effect is so smooth. It seems jittering acts like dithering technique here or we can say

second order sigma delta is too robust against clock jitter because of noise shaping. The value of

SNR with 10% jitter is 70.8dB and with 50% jitter is 70.3dB.

Figure11. Spectra of jitter modeling

KT/C Noise:

Thermal noise is most important source of noise in switch capacitor Σ∆ modulator associated to

sampling switches. It adds to input of integrator in each sampling.

Next figure shows model for simulation of KT/C noise. We use a Random Number with variance

equal KT/C to generate white noise and add it with input of integrator and then apply to an ideal

integrator. Value of KT for room temperature is 4.14*10^-21 and C is sampling capacitor. The

value of sampling capacitor is given from this equation: Cs=(12kT/VFS2).2

2N is 0.8pf for 12 bit

resolution, then here we choose it 1p.

Figure12. kT/C noise model

The result of simulation with kT/C noise is shown in figure 13. We see noise floor in signal band

increases with apply kT/C noise and reduce SNR from 71dB for ideal case to 70.2dB for noise

case, with another value of C=100f SNR comes more down to 68dB.

Figure13. Spectra of output with kT/C noise model

Tolerances:

Tolerances of passive elements like capacitors in integrator section can lead to non-linearity

because it changes loop gain and transfer function. Figure14 shows switch capacitor

implementation of second order sigma-delta modulator, that Cf=2Cs. In ideal case without

tolerance, the gain of first stage is Gain1=Cs1/Cf1=1/2 and the gain of second stage is

Gain2=Cs2/Cf2=2 but because of tolerance actual gain is Gain1=Cs1(1+er,1)/Cf1(1+er,2) and

Gain2= Cs2(1+er,2)/ Cf2(1+er,1) that er,1, er,2 are the relative precision. The result of simulation

with 1% random tolerance is so smooth and hard to see, the SNR in this case is 70.5dB. The

effect can be exaggerated with 10% tolerance that reaches to 68dB. Spectra in Figure15 show

that tolerance effects on whole band of frequency.

Figure14. Switch capacitor implementation of sigma-delta

Figure15. Spectra of output with 10% tolerance effect

Op-Amp performances:

Op-amp non-idealities like finite gain and bandwidth, slew rate and saturation voltages can

influence integrator performance from ideal behavior. These non-idealities are discussed here:

1-Open loop gain:

Ideally open loop or dc gain of op-amp is infinite but in practice it is limited by circuit

constraints. The finite gain of an op-amp reduces the dc response of the integrator from infinite

to the value of the op-amp gain. Next figure shows ideal and finite gain states:

However finite gain does not affect SNR if this condition satisfies: π(A+2)>>OSR

Here in our design we use an op-amp with 60dB gain or 1000 times and OSR=64 that it is clear

that satisfy above condition then in simulation the effects are so smooth and the result are the

same as before then we try it with a lower open loop gain like A=100 and as we expect it

increases in-band noise in low frequency and SNR diminishes to 70.5dB. The spectra are shown

below:

Figure16. Spectra of output with finite gain A=100

Bandwidth and Slew Rate:

The effect of the finite bandwidth and the slew-rate are related to each other and could be

interpreted as a non-linear gain. In figure x when Φ1 is on, output of integrator during nth period

is:

Where Vs =Vin(nT-T/2) and α is integrator leakage and τ=1/(2πGBW) is the time constant of

integrator, GBW is unity gain frequency of op-amp. The maximum slope of this curve is:

According to definition of slew rate, if SR (slew rate of op-amp) is more than above value then

there is not slew-rate limitation. The problem is when SR is less than above value and in this

case op-amp is in slewing, therefore, output voltage relation is divided into two parts and in the

first part it is linear with slope SR :

We model above formula in simulink with a building block placed in front of the integrator

which implements a MATLAB function. Next figure shows that.

Figure17. Modeling of integrator with op-amp non-ideality

The minimum slew rate for correct operation of integrator is calculated with help of (6.37)

relation of Maloberti’s book: SR > ΔVout/Ts/2 that for first stage is SR1> 192V/us and

SR2>448V/us. Actually in our simulation we normalize bandwidth of signal from 1MHz to 512

and then the values of slew rate should be normalized properly in simulation settings. In

simulation the limit starts when slew rate is about 25V/μs and bandwidth is about 15MHz. The

result of limited slew rate for first integrator results in odd harmonics. The second integrator has

less influence on the SNR and distortion because of better shaping. Next figures show effect of

limited slew rate and bandwidth on spectra:

Figure18. Spectra with limited slew rate at first integrator

Figure19. Spectra with limit slew rate for second stage

Saturation:

The voltage swing at the output of an integrator depends on signal amplitude and quantization

noise. When the integrator output exceeds the dynamic range of the op-amp the signal is clipped

to a saturation level resulting in a loss of feedback control. In specification specify full-scale

swing of op-amp between 1v to 2.8v then the dynamic range is 2.8v-1=1.8v. As we saw in ideal

model the output of integrators are about 1.5v and 4.5v for first and second stage respectively

that are larger than the full scale swing and make problem. The solution is to use scaling as it is

shown in above model. We model saturation with a Saturation block that upper limit and lower

limit can be set to a specified value. Also with adding a Gain blocks in front and end of

integrator. The level of input is scaled lower with 0.9/2 and .9/5 and finally at the end of

integrator it will be scaled up with 3/0.9 and 5/0.9 factor. To see effect of saturation we can

change scaling factor and see spectra in next figure:

Figure20. Spectra with saturation effect at first integrator

Figure21. Spectra with saturation effect at second integrator

Quantizer section:

The performance of modulator can reduce with static and dynamic limitations of a real ADC and

DAC. The shaping of sigma-delta modulator acts on error of ADC then if εADC<εQ ,the ADC

error does not disturb the circuit performance. For 1-bit ADC the dynamic range is large enough

and this condition is easily verified. It could be implemented with a comparator with a threshold

voltage. In our design we prefer more gain and less delay for comparator then we choose

differential amplifier with gain 200. After differential amplifier we use a Latch. This

combination is an efficient way to infinite gain. The auto zero crossing type comparator is useful

for high resolution quantizer. We simulate quantizer with a Sign block and sum block to add

offset. As we expect the result does not change.

Figure22. Quantizer

Whole effects:

With applying jitter, noise, tolerance and finite gain together the result of SNR with perfect filter

is 69.3dB and spectra is in figure23 that is almost close to requirements. Also we use a 6-order

Butterworth filter with corner frequency at fs/128=512Hz to remove high frequency noise at

output. The value of SNR after filter is 68.8dB and the spectra are shown in figure24.

Figure23. Spectra with whole non-idealities

Figure24. Spectra of filtered output

Power estimation:

Figure14 shows schematic of second order sigma delta modulator. It uses two op-amps and a

quantizer.

The power for op-amp with 0.5p load is 5mw and it is proportionally with load.

If C1=1p , C2= 0.5p

1-First stage op-amp:

Max. Cload=2C1+2C2= 2*1p+1p=3p

P1= 5 * 3 * 2=30 mW

2-Second stage:

Max. Cload=C1= 0.5p

P2= .5 * 5 * 2=5mW

3-The power of sampler according to relation:

Ps=12 kT fs 22N

kT=4.14E-21 , N=12 (SNR=70dB), fs=64E6

Ps=12 * 4.14E-21*64E6*224

=54uW

4- Comparator:

The relation from reference [2] gives us:

Pc=22n

* 12kTγVeff/(αTdVFS)

N=12, kT=4.14E-21, γ=2, Veff=200mV, α=0.1, Td=1/fs, VFS=2V

Pc=215uW

Also there are some power for digital filter and leakage power that we can estimate it to 1mW

Total power : 30mW+5mW+54uW+215uW+1mW=37mW

Area estimation:

Most of area in CMOS circuits is occupied by capacitors. Schematic of figure14 shows 4

capacitors C1=1p, C2=.5p then whole capacitance is 1p+2p+1p+.5p=4.5pF. The nominal

capacitance per area is 0.86fF/um2 then for 6p need:

Area= 4.5pF/0.86fF = 5200 μm2

Conclusion:

In this project we design and simulate an ADC with SNR of 70dB in second order sigma-delta

architecture. Simulation starts with ideal case and in each stage one non-ideality is added and the

results are examined. Some effects like jitter, kT/C noise, tolerance and finite gain does not

degrade too much the performance of ADC provided that their values are resaonable, but

limitations like slew rate, bandwidth and saturation can make huge disturbance in design. Power

and area of ADC were estimated to be about 37mW and 5200um2 respectively.

References:

[1]S. Brigati, F. Francesconi, P. Malcovati, D. Tonietto, A. Baschirotto and F.Maloberti,

“MODELING SIGMA-DELTA MODULATOR NON-IDEALITIES IN SIMULINK”

[2] C. Svensson, Stefan Andersson, Peter Bogner,” On the power consumption of analog to

digital converters”

[3]http://www.edatechforum.com/journal/dec2005/which_adc.cfm

[4] http://www.maxim-ic.com/an1870

[5] http://www.wikipedia.com