Design and Implementation of a Data Compression Scheme: A Partial

8/14/2019 Design and Implementation of a Data Compression Scheme: A Partial

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Design and Implementation of a Data

Compression Scheme: A Partial Matching

Guided by: Prof H. R. Vishwakarma

SUJESH P. LAL, VIT University, Vellore


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PPM

Predictive by Partial Matching (PPM)

Altera FLEX10K FPGA device

Followed by

timing analysis,

circuit synthesis for the validation,

Functionality,

performance of the designated circuit.

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Prediction by Partial Matching

Finite-context statistical modeling technique.

Blending together several fixed-order context models to predictthe next character in the input sequence.

Benchmark Version: PPMC In 1999, Charles Bloom developed PPMZ

uses an adaptive second level model to estimate the optimum value as afunction of the order, the total character count, number of uniquecharacters, and the last one or two bytes of context.

In 2002, Dmitry Shkarin developed PPMII PPMII inherits the statistics of shor ter contexts to set the init ial estimate

when a longer context is encountered for the first time

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PPMONSTR and PPMD

PPMONSTR is a variation of PPMD

That trades compression rate for execution speed.

Ziv.Lempel coding are more commonly used in practice.

The PPM algor ithm for binary data compression was

successfully written and modeled in VHDL.

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VHDL

VHDL - a hardware description language.

VHSIC Hardware Description Language(VHDL)

Very High Speed Integrated Circuit(VHSIC)

Strength Ability to model a digital system at many levels of abstraction.

Easy to design (Rapid prototyping)

Low cost

Faster time to market Exploration of design space

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Field Programmable Gate Array (FPGA)

Offers a potential alternative to speed up the hardware

realization.

Strengths

lower cost

higher density

shorter design cycle

Building blocks

Each block consist of

Programmable look-up table Storage registers

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Design Methodology

Involves two steps

The generation of the adaptive model

Uses Markov modeling

The compression/decompression using arithmetic coding

Adaptive coding allows the model to be constructeddynamically by both encoder and decoder during the

course of the transmission

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block diagram of a complete data compression system

Compression is dependent upon the fact that data is redundant

and that its generation was based on a fixed set of rules

Data that has been compressed need to be decompressed to return

it to its original form. Therefore a decompressor comes hand-in-

hand with a compressor

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PPM Implementation

Generation of an adaptive model

The compression or coding

What is happening is counted and used as the basis of

subsequent coding so that the counts only needs to be

incremented in the event that a character is correctly

predicted.

The adaptive model is generated using a Markov

predictor.

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Arithmetic Encoder and Decoder

To generate variable length codes

Replaces a sequence of symbols with a coding range of

real numbers between 0 and 1 (according to theprobability of occurance)

Generates a tag(a floating point value) from that range fora sequence encoded

The first phase generates a unique identifier or tag for agiven sequence of symbols

The second phase gives a unique binary code to the tag

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Algorithm for Arithmetic encoding and

decoding

The algorithm for decoding is:Low=0

High=1

Loop for all symbols Range = H igh Low

High = Low + Range * Q(x)

Low = Low + Range * Q(x 1)

where,

Q(x) = high range of symbol being encoded

Q(x- 1) = low range of symbol being encoded

The algorithm for decoding is:

Loop for all symbols.

Range = Q(x) Q(x 1)

= Tag Q(x 1)Tag = Tag / Range

Where,

Q(x)=high range of symbol being decoded

Q(x-1)=low range of symbol being decoded

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Flowchart of the Markov predictor

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Software Implementation

The whole design is described using IEEE compliant VHDL

language

A bottom-up approach is adopted(PPM module issubdivided)

Three sub modules: Markov predictor

Arithmetic encoder

Arithmetic decoder

The Markov predictor would be combined with thearithmetic encoder and referred to as the Markov mode.

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Markov Model

Builds the probability distribution from the input symbolsseen andthe arithmetic encoder generates a unique identifier or tag basedon the probability distribution of symbols.

Input to the Markov model sub-module is bit_stream1_1Two output por ts: prob0_0 and prob1_0

enable-1, clock-1

Outcome: The high and low range

The tag is generated and outputted at output_tag1

The sub-module would output a high bit to por t t rigger_decoder for the decoderto start decoding.

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Arithmetic Decoder and ppm model

Block diagram of arithmetic decode

Top-level view of PPM [email protected]


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Hardware Implementation

Hardware implementation is the unique abstract of thiswork

The physical hardware layout is generated using thesynthesis tool Quartus II version 5.0

Software is configured and downloaded to the FLEX10KEPF10K30BC356-3 FPGA

The FLEX10K family provides the density, speed, andfeatures to integrate entire systems, including multiple 32-

bit buses into a single chip

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Thank You

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Design and Implementation of a Data Compression Scheme: A Partial

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