Design and Implementation
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Transcript of Design and Implementation
Design and Implementation
of a Very Simple CPU
Sections 6.1 and 6.2
Stanton Lee
6.1 Specifying a CPU
• Determine its applications
• Choose an instruction set
• Design a state diagram
Overview
General CPU Cycle
Fetch Cycle: Fetch an instruction from memory then go to the decode cycle
Decode Cycle: Determine which instruction was fetched then go to the execute cycle
Execute Cycle: Execute the instruction then go back to the fetch cycle
Generic CPU State Diagram
6.2.1 Specifications
• The CPU can access 64 bytes of memory each byte being 8 bits wide
• The CPU will output a 6-bit address through pins A[5..0] and read an 8-bit value through pins D[7..0]
• There will only be one programmer usable 8-bit accumulator register labeled AC
Instruction Set
Internal Registers
AR: A 6-bit address register that supplies an address to memory via A[5..0]
PC: A 6-bit program counter that contains the address of the next instruction to be executed
DR: An 8-bit data register that receives instructions and data from memory via D[7..0]
IR: A 2-bit instruction register that stores an opcode
6.2.2 Fetching Instructions from Memory
First State of the Fetch Cycle
• Copy the address in PC to AR
• AR will then send the address to memory for reading
• FETCH1: AR <-- PC
Second State of the Fetch Cycle
• The memory will output the requested data to D[7..0]
• The CPU will read the data and store it in DR
• Increment PC
• FETCH2: DR <-- M, PC <-- PC + 1
Third State of the Fetch Cycle
• Copy the two high-order bits of DR to IR (opcode)
• Copy the six low-order bits of DR to AR
• These six bits in AR can be used for ADD and AND or ignored for JMP and INC
• FETCH3: IR <-- DR[7..6], AR <-- DR[5..0]
6.2.3 Decoding Instructions
• Determine which instruction was fetched
• Invoke the correct execution routine
• For this very simple CPU there are four routines
Fetch and Decode Cycles
6.2.4 Executing Instructions
The ADD Instruction
ADD1: DR <-- MFetch an operand from memory. Recall that AR alreadycontains an address from FETCH3.
ADD2: AC <-- AC + DRPerform the addition and store result in AC
Begin the Fetch Cycle again
The AND Instruction
This is similar to the ADD instruction
AND1: DR <-- MObtain an operand
AND2: AC <-- AC ^ DRPerform a logical AND and store
Begin the Fetch Cycle again
The JMP Instruction
JMP1: PC <-- DR[5..0]Simply copy the jump address to PC. The nextFetch Cycle will use that address.
Note that because the address was also copied to ARduring FETCH3 we can also perform PC <-- AR
Begin the Fetch Cycle again
The INC Instruction
INC1: AC <-- AC + 1Just add 1 to the accumulator’s value and store theresult back into the accumulator
Begin the Fetch Cycle again
Complete State Diagram
6.2.5 Establishing Data Paths
We now design the internal data paths of the CPU tosupport all possible data transfers
Two Approaches
• Direct paths between each pair of components that transfer data
• A common bus used by all components that need to transfer data
Data Transfers
AR: AR <-- PC; AR <-- DR[5..0]
DR: DR <-- M
IR: IR <-- DR[7..6]
These components only need to perform data loading
Data Transfers (continued)
PC: PC <-- PC + 1; PC <-- DR[5..0]
AC: AC <-- AC + DR; AC <-- AC ^ DR; AC <-- AC + 1
These components not only load data but they alsoperform increments
PreliminaryRegisterSection
Note the tri-statebuffers
Modify the Design
• AR transfers data to memory not to the bus
• IR does not supply data to the other registers
• AC does not supply data either (unrealistic for a real CPU)
• The bus is 8 bits wide but not all transfers use 8 bits. Use bits 5..0 of the bus for AR and PC. Use 7..6 for IR.
• The CPU must be able to compute AC + DR and AC ^ DR. Therefore we need an ALU.
FinalRegisterSection
Note the ALU
6.2.6 Design of an ALU
We now consider the implementation of a simple ALU
• The two inputs are DR via the bus and AC (direct)
• The output goes to AC
Functions
1. Add the two inputs
2. Logically AND the two inputs
A Very Simple ALU
Note the 2-1 MUX and the Control Signal
6.2.7 Designing the Control Unit
Components
• Counter: Contains the current state
• Decoder: Generates individual signals for each state
• Logic Block: Generates control signals for each component
Generic Control Unit
CPU States
Recall that this CPU has a total of 9 states:
FETCH1, FETCH2, FETCH3ADD1, ADD2AND1, AND2JMP1INC1
We will require a 4-bit counter and 4-16 decoder
Some Guidelines
• Assign FETCH1 to counter value 0 and use the CLR input of the counter to reach this state
• Assign sequential states to sequential counter values and use INC on the counter to traverse these states
• Assign the first state of each execute routine based on the opcodes and maximum number of states
The Mapping Function
Some of the execute routines have two states. Thereforewe must ensure that their first states are at least two apart.
A mapping function that satisfies this is as follows:
1IR[1..0]0
Diagram for Control Unit
Control Signals
We create control signals for the registers
PCLOAD = JMP1PCINC = FETCH2DRLOAD = FETCH2 OR ADD1 OR AND1ACLOAD = ADD2 OR AND2ACINC = INC1IRLOAD = FETCH3
Control Signals (continued)
We create control signals for the ALU, the buffers,and M.
MEMBUS = FETCH2 OR ADD1 OR AND1PCBUS = FETCH1
READ = FETCH2 OR ADD1 OR AND1
The ALU has a control input ALUSEL of either 0 or 1to select the proper function.
Control Signal Diagram
End of Presentation