Design and development of PLL based X-band carrier...

International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 3, March 2014

567

ISSN: 2278 – 7798

All Rights Reserved © 2014 IJSETR

Abstract— The design and experimental verification of an

X-band phase-locked loop (PLL) using PE83336 fabricated on

RT-duroid 6010 substrate is presented. This PLL is used as

frequency synthesizer which generates a stable and low phase

noise X-band signal. A stable reference is fed to the PLL

through a temperature compensated crystal oscillator

(TCXO). Experimental results of the frequency synthesizer

demonstrate the excellent performance achieved in X-band

frequency, with frequency resolution of 5.7MHz, and phase

noise at X-band better than -87dBc/Hz @ 100Hz offset.

Index Terms— PLL, frequency divider, phase detector (PD),

loop filter, voltage controlled oscillator (VCO), prescaler.

I. INTRODUCTION

With the developments in the field of modern satellite

communication, radar, mobiles and many other electronic

counter measures, the interest in microwave carrier

generations has increased manifold [1]. The low phase noise,

low spurious and broadband frequency synthesizer has

become the main trends of its development.

The modern technology of frequency synthesis has been

developed and classified into 3 main categories. They are

Direct Synthesis (DS), Digital Direct Synthesis (DDS) and

PLL Frequency Synthesis [2]. DS has excellent performance

on short frequency switching time, but it consumes more

power as it needs to integrate filter, mixer, etc. DDS can

provide high resolution and low phase noise signals but

however it generates a low frequency and weak spurious

suppression signal [3]. PLL has a wide output range and a

great suppression of spurious frequency. A PLL design can

be integer (N) based PLL or fractional (F) based PLL.

In this paper, integer N-type PLL frequency synthesis

structure is proposed and implemented. The implemented

model has excellent performance on high frequency with

resolution of 5.7MHz, output in X-band and phase noise

Manuscript submitted Feb, 2014.

Vabya Kumar Pandit, RF Communication, Centre for Emerging

Technologies, Jain University. Bangalore, India, Mobile No. +91

8951164439

Chitra R., Division Head, Data Transmitter and Navigation Division,

Communication Systems Group, ISRO Satellite Centr , Bangalore, India.

Phone No+919449082541.,

Sourabh Basu, Data Transmitter and Navigation Division,

Communication Systems Group, ISRO Satellite Centre , Bangalore, India.

Phone No+91 9972237695.,

Deepak V.Ingale, Assistant Professor at Centre for Emerging

Technologies, Jain University, Bangalore, India.

Phone No+91 9886503032.,

better than –87dBc/Hz@100Hz. The measured result for

X-band carrier generator phase noise matches with the

theoretical values, as described later in this paper.

II. SYSTEM ANALYSIS

The block diagram of the PLL synthesizer is shown in fig.1

Figure 1 Block diagram of the N-type PLL frequency synthesizer.

As Fig.1 shows, the R divider is much smaller than the

other methods discussed in Part (I) because of the IF signal in

low frequency. Therefore, the phase noise is significantly

decreased.

The frequency resolution is given by the Equation (1) by

the analysis of figure 1.

Fc =Fr ÷ (R+1) (1)

The highly stable reference signal (Fr) of PLL is

generated by a temperature compensated crystal oscillator

(TCXO). The PLL output signal synchronizing with a

reference input signal in frequency as well as in phase. More

precisely, the PLL system is the one, which controls the

phase of its output signal in such a way that the phase error

between output phase and reference phase reduces to a

minimum [4].

PLL tracks phase differences between the input Fc and Fp and fed back signal from the VCO. The phase detector

produces voltage PD_U and PD_D which is proportional to

the phase difference between its two inputs. This error signal

is filter by the loop filter and applied to the VCO, changing

the VCO frequency such that the phase difference between

the two phase detector input signals become constant, or

reduces to zero, depending on the type of phase detector used.

When this happens, the loop is said to be locked [5].

The phase detector input Fp is derived by the Equation (2)

Design and development of PLL based X-band

carrier generator for satellite applications

Vabya Kumar Pandit, Chitra R, Sourabh Basu, Deepak V.Ingale


568


Fp = Fin ÷ [10(M+1) +A] (2)

where M and A are the counter values. The output signal

from the VCO is fed to the divide by-8 prescaler. This output

frequency Fin is given by Equation (3)

Fin = [10(M+1)+A]×[ Fr ÷ (R+1)] (3)

In locked condition both Equation (2) and (3) must be

satisfied.

III. CIRCUIT IMPLEMENTATION

The described analysis in section (II) is used to realize

X-band frequency synthesizer. The circuit design of PLL is

described in the following parts-

Part A

The Peregrine’s PE83336 chip is a high performance

integer-N PLL capable of frequency synthesis up to 3.0 GHz.

It provides an excellent simplification of the architecture of

the synthesizer. The superior phase noise performance of the

PE83336 makes it ideal for space environments including:

radio handsets, radar, avionics, missiles, etc. PE83336 PLL

IC has been represented as block A in figure 1. The stable

reference frequency is given by TCXO as shown in figure 2.

Figure 2 Circuit realization of block A

Part B

Figure 3 represents the active loop filter used in

conjunction with the differential output of the PE 83336

phase detector. Since all the parameters of PLL are fixed and

specific to the components used, the loop filter is the only

component that gives a degree of freedom with regard to the

design of the PLL, in terms of close-in phase noise

characteristics and the lock time. The ideal values of resistor

and capacitor in loop filter are gotten from the simulation.

Figure 3 Circuit realization of block B

Part C

A Teledyne Cougar OAS 8900 voltage–controlled

oscillator (VCO) with the tuning range of 6900 MHz to

8900MHz is used to simplify the architecture of the

synthesizer. It offers low phase noise, wide tuning range and

high frequency of operation, eliminating the need of using

additional frequency multipliers to obtain he desired output

frequency.

The output of the VCO (OAS 8900) is fed back to the PLL

IC (PE83336) through a 10dB coupler and a Divide-by-8

prescaler, so that L-band signal reaches the Fin of the PLL IC.

Figure 4 Circuit realization of block C (VCO and prescaler)

A PLL frequency synthesizer with prescalers is used to

generate higher output frequencies. The prescaler is a

frequency divider that is capable of operating at high VCO

output frequencies. The prescaler divides the VCO output

frequency by a specified factor. In this paper divide-by-8

factor is used. This value is not tunable. This system produces

an output frequency related to the input reference frequency

by the following:

Fout =8NFc (4)

From Equation (1) and (4),

Fout =8N[Fr ÷ (R+1)] (5)


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ISSN: 2278 – 7798


IV. SIMULATION AND TESTING

The design of the X-band frequency synthesizer consists of

the PE83336 chip as the main body and auxiliary circuit,

which mainly include reference oscillator, VCO, loop filter

and prescaler. The main technical requirements of the

frequency synthesizer are:

operating frequency band: X-band;

phase noise ≤ -80 dBc/Hz at 100Hz offset;

harmonic suppression ≤ -30 dBc;

spurious ≤ -50dBc;

reference frequency: 22.8 MHz.

The total phase noise of the PLL deteriorates from the

phase noise of TCXO and can be calculated from equation (6)

PLL Phase Noise=

Phase noise of TCXO +20 log (Fout/Fr ) (6)

The phase noise of the TCXO is obtained from figure 5.

The PLL phase noise 87dBc/100Hz is obtained from

Equation (6) when the reference frequency Fr is taken

22.8MHz at output frequency in X-band is as shown in figure

(6)

Figure 5 Phase noise of TCXO

The output of the X-band PLL is multiplied by a frequency

tripler and driven through driver amplifier. Fig.7 and Fig.8

shows the spectrum of the frequency synthesizer output in

Ka-band. A spurious of -47dBc is observed, as seen in figure

7, at an offset of 1070MHz from the carrier, which

marginally misses the desired spurious level of -50dBc or

lesser. Hence, an additional bandpass at Ka-band is required,

which would provide an attenuation of atleast 3dB at the

spurious frequency.

Figure 6 Phase noise of PLL

Figure 7 Frequency synthesizer output in Ka-band

Figure 8 Frequency synthesizer output in Ka-band


570


Figure 9 Top view of fabricated X-band carrier generator on RT-duroid

substrate

Figure 10 Top view of X-band carrier generator with 3X multiplier and driver

amplifier.

V. CONCLUSION

In this paper, X-band frequency synthesizer with

PE83336 chip on RT-duroid substrate is implemented. This

design not only enhances the frequency resolution but also

decreases the phase noise, that is to say, the contradictory

between the resolution and phase noise has been solved. The

carrier generator achieves the frequency resolution of

5.7MHz, and phase noise better then -87dBc/Hz @ 100Hz

offset.

VI. ACKNOWLEDGEMENT

The author expresses sincere gratitude to Sri E. Vasantha,

Dy. Director, DCA & Sri Yateendra Mehta, Group Director,

CMG at ISRO Satellite Centre for their valuable guidance,

encouragement and support. The authors sincerely

acknowledge Sri K. Chandrashekar, Program Head, DSP /

RF - CET & Dr. Krishna Venkatesh, Director, Centre for

Emerging Technologies, Jain University, Bangalore for their

valuable guidance and support.

REFERENCES [1] Piotr Matuszczak, Lukasz Kulas, Krzysztof Nyka “Low Cost Microwave

X-Band Generator”, Proceedings of the 2nd International Conference

on Information Technology, ICIT 2010 • 28-30 June 2010, Gdansk,

Poland.

[2] F. Kroupa, Phase Lock Loops and Frequency Synthesis, John Wiley,

2003.

[3] Yuanwang Yang, Jingye Cai, Liu Lianfu, “A Frequency Synthesis

Structure in Radar Target Simulation System with High Agility and

Resolution Performance”, Microwave Conference Proceedings

(CJMW), 2011 China-Japan Joint. 2011, pp. 1-4.

[4] Hideyasu Hobara1, Yoshiki Kayano1 and Hiroshi Inoue “A Study on

Design of PLL for Low Phase-Noise Characteristics”,SICE Annual

Conference 2012,August 20-23,Akita University, Akita, Japan.

[5] F.M. Gardner, Phaselock Techniques. John Wiley & Sons, Inc., Second

Edition,1979.

Vabya Kumar Pandit, is a final year M.Tech,

Scholar at Centre for Emerging Technologies, Jain

University, Bangalore, in the area of Radio

Frequency Communication. He completed B.E in

Electronics and Tele-communication Engineering,

from Chhattisgarh Swami Vivekananda Technical

University (CSVTU), Bhilai in the year 2011.

Chitra R., completed her bachelor’s in Electronics

& Communication from Madras University in

1980 and her Master’s in Electrical

Communication from Indian Institute of Science

Bangalore in 1990. She has been quite instrumental

in the development of Data Transmitters for

Remote sensing and Geostationary spacecrafts at

ISRO Satellite Centre. Currently she is heading the

Data Transmitter and Navigation Division of

Communication Systems Group at ISRO Satellite

Centre, Bangalore. She has published more than 5

papers in national and international

conferences/journals.

Sourabh Basu, completed his bachelor’s in

Electronic Science from Delhi University in 2001

& his Masters in Microwave Electronics from

Department of Electronic Science, University of

Delhi in the year 2005. Presently, he is working as

a Scientist / Engineer in Data Transmitter and

Navigation Division of Communication Systems

Group at ISRO Satellite Centre, Bangalore.

Deepak V. Ingale, completed his M.Tech in VLSI

and Embedded Systems in 2008. Presently he is

working as an Assistant Professor at Centre for

Emerging Technologies, Jain University,

Bangalore. As a Project Engineer at Wipro

Technologies he was instrumental in component

selection, board re-design(PCB), setting up &

conducting First Piece Evaluation(FPE) of various

telecom switches and related activities. He has

more than 3 papers to his credit which got

published in national and international

conferences/symposiums.

Design and development of PLL based X-band carrier...

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