DESIGN AND ANALYSIS OF POWER EFFICIENT 9T...
Transcript of DESIGN AND ANALYSIS OF POWER EFFICIENT 9T...
Vol 06, Article 09641; October 2015 International Journal of VLSI and Embedded Systems-IJVES
http://ijves.com ISSN: 2249 – 6556
2010-2015 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat,
DOAJ, and other major databases etc.,
1621
DESIGN AND ANALYSIS OF POWER EFFICIENT 9T
ADIABATIC SRAM CELL NISHA YADAV1, SUNIL JADAV2 , PARDEEP3
1,2,3Electronics Engineering Department, YMCA University of Science & Technology, Faridabad, INDIA 1nishayadv@ gmail.com, [email protected] ,[email protected]
ABSTRACT
Leakage power is becoming the dominant power component in deep submicron technology and stability of
the data storage of SRAM (Static Random Access Memory) cells is drawing more concerns with the reduced
feature sizes. A novel 9T SRAM cell design considering these leakage issues for ultra low power applications
is proposed in this paper. The elementary cell structure of proposed adiabatic SRAM resembles behavior
of static CMOS 4T-SRAM consisting of two high load resistors which is constructed of PMOS, a cross-
coupled NMOS pair, NMOS switch which is necessary to restrict short circuit current and two trapezoidal-
wave pulses. From the simulation results, it has been shown that the average power dissipation of the
proposed SRAM reduces by a factor of 98% with no performance degradation and energy is efficiently
recovered using adiabatic operation and body bias. The simulation is carried out at 180nm technology. The
stability of proposed SRAM is investigated using MATLAB.
Keywords—Adiabatic Logics, Average power Dissipation, Body Bias , SRAM.
I. INTRODUCTION
Colossal advances in CMOS technology have made it possible to design chips with high better performance, and
low power consumption. To attain these objectives, the feature size of the CMOS devices has faced aggressive
scaling down to very small features and dimensions. However, the leakage current has increased immensely with
technology scaling, and has become a major contributor to the total IC power. The leakage current is primarily
due to the subthreshold current and secondarily due to Gate Induced Drain Leakage (GIDL). Modern
microprocessors employ on-chip caches, which can effectively reduces the speed gap between the processor and
main memory to boost system performance. These on-chip caches are usually implemented using arrays of SRAM
cells. Thus, SRAMs comprise an increasingly large portion of modern VLSI circuits. The need of low power
devices become popular due to the increasing popularity of portable electronic devices which all uses battery as
power source and also large power dissipation requires larger heat sinks hence increased area and thus cost.
Demands for low power circuits have motivated VLSI designers to explore new approaches to the design of VLSI
circuits. Adiabatic (Energy recovering) logic is a new promising approach because they are able to break the lower
limit of the energy dissipation in static CMOS which amounts to 1
2𝐶(Vdd)2.
In this work a new adiabatic SRAM is presented with controlled sudden current flow. The proposed circuit
which is driven by two trapezoidal-wave pulses can be directly converted from the conventional SRAM circuits,
without drastically increasing the circuit area. In order to reduce the subthreshold leakage current and average
power consumption, bulk bias technique is used.
This paper is organized as follows. The Adiabatic operation and proposed SRAM is presented in Section II. The
stability of the proposed SRAM is investigated in Section III. Average Power Dissipation, and delay of various
SRAM cells are compared in Section IV. Finally, some conclusions are offered in Section V.
II. ADIABATIC OPERATION IN VLSI
A. Conventional Charging
The CMOS inverter consists of a pull-up and pull-down network connected to a load capacitance C. The pull-up
and pull-down network can be modeled by an ideal switch in series with a resistor which is equal to the
corresponding channel resistance of the transistor in the saturation mode, as shown like in Fig. 1, where Vdd
becomes a DC voltage. When the input to the inverter is logic “0”, PMOS becomes ON and there is a sudden flow
current through Rp, where Rp is equivalent resistance of PMOS pull-up network.
Fig. 1. RC equivalent model of CMOS inverter
Vol 06, Article 09641; October 2015 International Journal of VLSI and Embedded Systems-IJVES
http://ijves.com ISSN: 2249 – 6556
2010-2015 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat,
DOAJ, and other major databases etc.,
1622
A charge 𝑄 = 𝐶𝑉𝑑𝑑 is delivered to the load and the energy which the supply applies is 𝐸𝑠𝑢𝑝𝑝𝑙𝑦 = 𝑄𝑉𝑑𝑑 = 𝐶𝑉𝑑𝑑2,
where 𝑉𝑑𝑑 is a DC power supply voltage. The energy stored into the load C is a half of the supplied energy:
𝐸𝑠𝑡𝑜𝑟𝑒𝑑 = 1
2𝐶𝑉𝑑𝑑2. and rest of energy is dissipated across PMOS. Now, when the input is at logic “1”, NMOS
turns ON and the same amount of energy stored in C, is dissipated during the discharge process in the NMOS
pull-down network because no energy can enter the ground rail as Q×Vgnd = Q×0 = 0. From the energy
conservation law, a conventional CMOS logic emits heat and, in this way, it wastes energy in every charge-
discharge cycle:
Etotal = Echarge+Edischarge = 1
2𝐶𝑉𝑑𝑑
2+1
2𝐶𝑉𝑑𝑑
2 = 𝐶𝑉𝑑𝑑2. If the logic is driven by a certain frequency f (= 1/T), where
T is the
period of the signal, then the power of the CMOS is determined as 𝑃𝑡𝑜𝑡𝑎𝑙 =𝐸𝑡𝑜𝑡𝑎𝑙
𝑇= 𝐶𝑉𝑑𝑑
2𝑓.
B. Adiabatic Charging
In thermodynamics, an adiabatic energy transfer through a dissipative medium is one in which losses are made
arbitrarily small by causing the transfer to occur sufficiently slowly. The main idea in an adiabatic switching
shown in Fig. 1.1 is that transitions are considered to be sufficiently slow so that heat is not emitted significantly.
This is made possible by replacing the DC power supply by a resonance LC driver, an oscillator, a clock generator,
etc. If a constant current source delivers the Q = 𝐶𝑉𝑑𝑑 charge during the time period ∆T, the energy dissipation in
the channel resistance Rp (or Rn) is given by
𝐸 = 𝑃∆T = 𝐼2𝑅𝑝∆T = (𝐶𝑉𝑑𝑑
∆T)2𝑅𝑝∆T
The above equation indicates that when the charging period ∆T is indefinitely long, in theory, the energy
dissipation is reduced to zero. This is called an adiabatic switching.
If circuits can be rnade to operate in an adiabatic regime with consequently low energy dissipation, then the
energy used to charge the capacitive signal nodes in a circuit may be
recovered during discharge and stored for reuse. The efficiency of such a circuit is then limited only by the
‘adiabaticity’ of the energy transfers. Conventional CMOS circuits are pathologically non adiabatic. Capacitive
signal nodes are rapidly charged and discharged (the energy transfer)
through MOS devices (the dissipative medium). At times the full supply potential appears across the channel of
the device, resulting in high device current and energy dissipation.
C. Proposed adiabatic sram
The conventional 6T SRAM memory cell is composed of two cross-coupled CMOS inverters with two pass
transistors connected to complementary bit-lines. But our proposed SRAM resembles behavior of static CMOS
4T-SRAM.
Fig. 2. 4T SRAM Cell design
The resistor R1 and T2 of 4T SRAM divide the voltage between Vcc and GND. If T2 is in high impedance state,
then the connection between R1 and T2 is at Vcc voltage. If this is the case, then T3 is enabled and therefore in
low impedance state. As a consequence, the voltage level between R2 and T3 is close to ground. This in turns
disable T2, which remains in high impedance. If however T2 is in low impedance, then the roles of T2 and T3 are
reversed. Thus we have seen that there exists two stable states. This configuration has a certain amount of current
leakage on the lines from ground to Vcc. For this reason, the resistors are replaced by transistors. In the proposed
SRAM two high load resistors are constructed of PMOS.
The elementary cell of proposed circuit consists of two high load resistors which is constructed of PMOS (PMOS
1 and PMOS 2), and a cross-coupled NMOS pair (NMOS 1 and NMOS 2). In order to reduce the energy
dissipation in the elementary cell, the PMOS having off-leak current is used. Using the PMOS as a high resistor
the cell area can be small compared with the conventional 4T-SRAM using poly resistor. NMOS switch (NMOS
3) is necessary to restrict a short circuit current when the data is written in the elementary cell. In the proposed
circuit, decreasing signal voltage on the write (or read) line is limited by transmission gate; however normal
NMOS switch is better from the viewpoint of cell area if voltage drop is no problem.
Vol 06, Article 09641; October 2015 International Journal of VLSI and Embedded Systems-IJVES
http://ijves.com ISSN: 2249 – 6556
2010-2015 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat,
DOAJ, and other major databases etc.,
1623
Fig. 3. Schematic of Proposed SRAM Cell
In general, the bulk of the PMOS transistor and NMOS transistor are connected to the 𝑉𝑑𝑑 and ground potential
respectively. In order to reduce the subthreshold leakage current and average power consumption, bulk bias
technique is used and optimum value of bulk bias(1.8 for PMOS and 0.6 for NMOS) is applied only to inverter
transistors, the bulk of two NMOS and two PMOS transistor which are used as access transistors, connected to
the ground potential and 𝑉𝑑𝑑 respectively.
The adiabatic operation in the proposed cell during write mode is as shown in fig. 4 .When WL is high and BL
ramps from 0 to Vdd the capacitor CL1 is charged through transmission gate and the energy used to charge the
capacitive signal nodes in a circuit may be recovered and stored for reuse during recovery phase i.e. when BL
ramps from Vdd to ground, instead of discharging as heat.
Fig. 4. Adiabatic operation of proposed SRAM Cell
The write mode of the proposed SRAM is as following: At first phase, when WL is High and WLbar is Low level,
MOS transistors: NMOS 4, NMOS 5, PMOS 3, and PMOS 4 are ON. Hence, the node A and Abar is possible to
change the write-mode, and then NMOS 3 is OFF in order to reduce the energy dissipation in the elementary cell.
In second phase, adiabatic signal line BL, and BLbar are on-state, and then the data write on A and Abar. Finally,
when WL and WLbar are Low and High state respectively, MOS transistors: NMOS 4, NMOS 5, PMOS 3, PMOS
4 become all OFF, and then NMOS 3 becomes ON. As a result, data is hold state in the elementary cell. The input
and output waveform of the proposed SRAM are shown in fig. 5. In this simulation, we use 0.18 μm CMOS
standard process where the size of PMOS of elementary cell is W/L = 25 μm/0.18 μm and the size of rest of
transistor is W/L = 0.60 μm/0.18 μm.
III. STABILITY ANALYSIS OF PROPOSED SRAM CELL
In this work, we are investigating the stability of the proposed SRAM using MATLAB. In general, the stability
of SRAM is defined with the help of butterfly curve, but since this configuration is different as it does not contain
back to back connected CMOS inverter. So we are trying to plot the poles of the system and define the stability
on basis of location of poles. The basic methodoly used is that we define a transfer function H(s) =Y(s)/X(s) where
Y(s) and X(s) are output and input response in laplace. Later, poles of the transfer function are plotted and on
basis of that stability is analyzed. The analysis will begin with representing the input (BL) and the output (A)
waveforms in the form of signals as following:
𝐵𝐿(𝑡) = 0.9𝑟(𝑡 − 1.5) − 0.9𝑟(𝑡 − 3.5) − 0.9𝑟(𝑡 − 20.5) + 0.9𝑟(𝑡 − 22.5)
𝐴(𝑡) = 0.7575r(t − 1.5) – 0.717r(t − 3.5) − 0.033r(t − 5) + 0.107r(t − 19.1) − 0.507r(t − 20.5) − 0.5r(t − 21) + 0.8r(t − 22.5) + 0.1r(t − 24)
Now laplace transform of both the signals is taken and we got
Vol 06, Article 09641; October 2015 International Journal of VLSI and Embedded Systems-IJVES
http://ijves.com ISSN: 2249 – 6556
2010-2015 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat,
DOAJ, and other major databases etc.,
1624
Fig. 5. Waveforms showing the operation of Proposed SRAM Cell
𝐵𝐿(𝑠) = 0.9 ∗ 𝑒𝑥𝑝(−1.5 ∗ 𝑠)/(𝑠 ∗ 𝑠) − 0.9 ∗ 𝑒𝑥𝑝(−3.5 ∗ 𝑠)/(𝑠 ∗ 𝑠) − 0.9 ∗ 𝑒𝑥𝑝(−20.5 ∗ 𝑠)/(𝑠 ∗ 𝑠) + 0.9∗ 𝑒𝑥𝑝(−22.5 ∗ 𝑠)/(𝑠 ∗ 𝑠);
A(s) = 0.75 ∗ exp(−1.5 ∗ s)/(s ∗ s) − 0.717 ∗ exp(−3.5 ∗ s)/(s ∗ s) − 0.033 ∗ exp(−5 ∗ s)/(s ∗ s) + 0.107∗ exp(−19.1 ∗ s)/(s ∗ s) − 0.507 ∗ exp(−20.5 ∗ s)/(s ∗ s) − 0.5 ∗ exp(−21 ∗ s)/(s ∗ s)+ 0.8 ∗ exp(−22.5 ∗ s)/(s ∗ s) + 0.1 ∗ exp(−24 ∗ s)/(s ∗ s)
Then Convert all the sub systems having internal delay to state space model. State space representation provides
a convenient and compact way to model and analyze complex systems. Prescale the entire state space model to
improve accuracy of the system. Now convert the state space model to transfer function form. Thus, we get the
final transfer function as
8.879𝑒 − 016 𝑠^23 + 0.0005 𝑠^22 + 4.439𝑒 − 019 𝑠^21 − 8.643𝑒 − 016 𝑠^20 − 1.919𝑒 − 031 𝑠^19 − 1.101𝑒 − 031 𝑠^18 − 2.445𝑒 − 047 𝑠^17 + 1.13𝑒 − 062 𝑠^16 + 1.656𝑒− 079 𝑠^15 − 1.303𝑒 − 095 𝑠^14 + 9.678𝑒 − 113 𝑠^13 − 1.225𝑒 − 127 𝑠^12 − 1.475𝑒 − 144 𝑠^11 + 1.242𝑒 − 173 𝑠^10 + 1.531𝑒 − 190 𝑠^9
− − − − − − − − − − − − − − − − − − − − − − − − −
6.933𝑒 − 017 𝑠^23 + 1.028𝑒 − 015 𝑠^22 + 9.335𝑒 − 016 𝑠^21 + 9.261𝑒 − 016 𝑠^20
The poles of the system lie at
-13.9301
-0.4489 + 0.8703i
-0.4489 - 0.8703i
and multiple poles at origin.
The pole zero plot of the transfer function is shown in fig. 6. It can be seen that all the poles lie in the left half of
s plane
Vol 06, Article 09641; October 2015 International Journal of VLSI and Embedded Systems-IJVES
http://ijves.com ISSN: 2249 – 6556
2010-2015 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat,
DOAJ, and other major databases etc.,
1625
Fig. 6. Pole-zero plot of the proposed SRAM Cell
Natural frequency and the damping ratio of the system are
wn= 13.9299
0.9793
0.9793
zeta =1.0000
0.4584
0.4584
Hence, the system has two modes, one corresponding to real pole and other to a pair of complex conjugate
poles. The lower frequency mode at 𝑤𝑛 = 0.9793 𝑟𝑎𝑑/𝑠 is lightly damped (ζ=0.4584), while the higher
frequency mode at 𝑤𝑛 = 13.9299 𝑟𝑎𝑑/𝑠 is welldamped (ζ=1).
Fig.7 3D plot of the proposed SRAM cell transfer function
IV. SIMULATION RESULTS
The conventional SRAM, adiabatic SRAM without body bias and the proposed SRAM are tested by SPICE
simulation using a 0.18 μm standard CMOS process technology. Table I summarizes the energy dissipation values.
From this table, it has been found that energy dissipation of proposed SRAM is drastically reduced compared to
those of the conventional 6T-SRAM and adiabatic-SRAM without body bias.
-6 -5 -4 -3 -2 -1 0 1
x 1011
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Pole-Zero Map
Real Axis
Imagin
ary
Axis
-5
0
5
-5
0
50
1
2
3
4
5
6
x 1012
Vol 06, Article 09641; October 2015 International Journal of VLSI and Embedded Systems-IJVES
http://ijves.com ISSN: 2249 – 6556
2010-2015 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat,
DOAJ, and other major databases etc.,
1626
TABLE I
COMPARISON OF ENERGY DISSIPATION BETWEEN CONVENTIONAL, ADIABATIC AND
PROPOSED SRAM
SRAM
Average Power Dissipation
Conventional 6T
SRAM
3.366729e-005 watts
Adiabatic SRAM
1.545982e-006 watts
Proposed SRAM 9.217964e-009 watts
Table II summarizes the comparison of delay in various SRAM cell and it has been found that delay is minimum
in the proposed SRAM cell.
TABLE II
COMPARISON OF DELAY BETWEEN CONVENTIONAL, ADIABATIC AND PROPOSED SRAM CELL
SRAM
Delay (s)
Conventional 6T
SRAM
7.4229e-010
Adiabatic SRAM
1.8039e-010
Proposed SRAM 1.5442e-010
Fig. 8. shows the graphical representation of Average Power Dissipation of Conventional 6T SRAM, Adiabatic
SRAM without body bias and Proposed SRAM cell.
Fig. 8. Comparison graph of Average Power Dissipation of various SRAM cell
V. CONCLUSION
In this work, a body bias adiabatic SRAM has been presented. Adiabatic CMOS circuits, which adopt a gradually
rising and falling wave pulses and controlled switching current flow, can result in a considerable energy saving.
Simulation of the proposed SRAM cell has been done for 180nm CMOS technology. It has been shown that the
average power dissipation of the proposed SRAM reduces by a factor of 98% with no performance degradation.
The delay of the proposed SRAM also reduces 79%. The research being performed on the stability of proposed
SRAM using MATLAB and on the basis of location of poles which all lie in the left half of s plane and the
waveform showing operation of SRAM, we can conclude that the proposed SRAM have the correct logic function.
To investigate the stability, merely researching on location of poles is insufficient. Following the research in this
paper, the stability of proposed SRAM will be investigated using various stability plots. Corresponding research
results obtained in future will be reported in another paper.
33.6672
1.5459 0.67330
5
10
15
20
25
30
35
40
Average Power Dissipation (μW)
Conventional
Adiabatic SRAM
Proposed SRAM
Vol 06, Article 09641; October 2015 International Journal of VLSI and Embedded Systems-IJVES
http://ijves.com ISSN: 2249 – 6556
2010-2015 – IJVES Indexing in Process - EMBASE, EmCARE, Electronics & Communication Abstracts, SCIRUS, SPARC, GOOGLE Database, EBSCO, NewJour, Worldcat,
DOAJ, and other major databases etc.,
1627
REFERENCES
[1] Hideaki Komiyama, Yasuhiro Takahashi and Toshikazu Sekine, “Low-Power Adiabatic SRAM” Intelligent
Signal Processing and Communications Systems (ISPACS), Dec. 2011 IEEE.
[2] Jinshen Yang and Li Chen , “A New Loadless 4T SRAM Cell with a 0.18um CMOS Technology”, Electrical
and Computer Engineering, 2007 IEEE.
[3] Guoqiang Hang, “Adiabatic CMOS Gate and Adiabatic Circuit Design for Low-Power Applications”
Proceedings of IEEE,2005
[4] Aruna Rani and Poonam Kadam, “ Adiabatic Split Level Charge Recovery Logic Circuit”, International
Journal of Computer Applications 65(25):18-22, March 2013.
[5] Chun-Keung Lo and Philip C.H. Chan, “ Design of Low Power Differential Logic Using Adiabatic Switching
Technique”, 0-78034455-1998 IEEE.
[6] A. G. Dickinson and J. S. Dencker, “Adiabatic Dynamic Logic”, IEEE J. Solid-States Circuits., vol. 30, no.
3, pp. 311–315, April 1995.
[7] Shunji Nakata, “Adiabatic SRAM With A Shared Access Port Using A Controlled Ground Line And Step-
Voltage Circuit”, Circuits and Systems (ISCAS), Proceedings of 2010 IEEE.
[8] Y. Moon and D. K. Jeong, “An efficient charge recovery logic circuit,” IEEE J. Solid-States Circuits., vol.
31, no. 4, pp. 514–522, April 1996.
[9] Y. Takahashi, Y. Fukuta, T. Sekine, and M. Yokoyama, “2PAD CL: Two phase drive adiabatic dynamic
CMOS logic,” in Proc. IEEE Asia-pacific Cong. Circuits and Systems, Singapore, Dec. 4–7, 2006, pp. 1486–
1489.
[10] J. Chen, D. Vasudevan, E. Popovici, M. Schellekenst, P. Gillen, “Design and analysis of a novel 8T SRAM
cell for adiabatic and non-adiabatic operations”, Proc. IEEE Int.Conf. Electro., Circuits, and Syst., (ICECS 2010),
DAthens, Greek, Dec. 2010, pp.434–437.
[11] Er. Robin Mehta, Er. Amit Kumar, “ Sense amplifier approach for high speed SRAM Cell”, International
Journal of Scientific & Engineering Research, Volume 4, Issue 6, June-2013 840 ISSN 2229-5518.
[12] Y. Takahashi, Toshikazu Sekine, Michio Yokoyama, “ Low Power Adiabatic 9T SRAM”, Journal of
Circuits, Systems, and Computers, 20, January 2013.
[13] Springer “Control Design Techniques” Thoams Schwarz,S.J., COEN, SCU,2004.
[14] Hans-Petter Halvorsen, “LabVIEW MathScript” 2011.02.11