Derivative applications are a real gold mine of ...€¦ · Derivative applications are a real gold...

© 2013

Copyrights © Yole Développement SARL. All rights reserved.

Non Mainstream PackagingDerivative applications are a real gold mine of

technological innovationsv

1995

Sidebraze DIP

1996-2002

Plastic PDIP

1999 - today

SMT SOIC

& Die Down

2006

Stacked Die

QFN

~125 sq mm ~100 sq mm ~25 sq mm

6 & 6 mm

Source Freescale

Source MEMSiC

Source CEA-Leti

1995

Sidebraze DIP

1996-2002

Plastic PDIP

1999 - today

SMT SOIC

& Die Down

2006

Stacked Die

QFN

~125 sq mm ~100 sq mm ~25 sq mm

6 & 6 mm

Source Bosch Source EPWorks Source Lumileds

May 14, 2013

© 2013 • 2

MEMS

POWERLED

Focus on 3 topics with packaging challenges

© 2013


MEMS

Source VTI / MurataSource Microvision

© 2013 • 4

MEMS are definitively not standardized

devices!

• Gyroscopes

• Accelerometers

• Magnetometers

• Fusion sensor

combos & IMUs

• Pressure

-sensors

• TPMS

modules

• Oscillators/

Resonators

• RF-MEMS

switches

• FBAR/BAW

filters

• Micro-

mirrors

• Micro-

bolometers

• Ink-jet MEMS

modules

• Microfluidic &

Bio-chips

• Auto Focus,

Chemical

MEMS,

µspeakers,

scanning

mirrors, Si

µfluidics, RF

IDs,

µdisplays,

AOC MEMS,

Touchscreens

, Energy

Harvesting …

• Silicon

microphones

Voice/Sound

Pressure

monitoringMotion/

position

Projecting/

receiving

light

RF-related

functionsManaging

fluids

Emerging

MEMS

Sensing applications

© 2013 • 5

MEMS markets by application

(in US$M)

2012 2013 2014 2015 2016 2017 2018

Telecom $ 188M $ 210M $ 239M $ 265M $ 297M $ 329M $ 364M

Medical $1 835M $2 205M $2 688M $3 277M $4 021M $4 981M $6 304M

Industrial $ 874M $ 963M $1 069M $1 203M $1 339M $1 495M $1 676M

Defense $ 297M $ 335M $ 379M $ 421M $ 470M $ 525M $ 583M

Consumer $5 048M $5 752M $6 487M $7 216M $7 999M $8 833M $9 776M

Automotive $2 639M $2 760M $2 934M $3 115M $3 322M $3 503M $3 643M

Aeronautics $ 107M $ 115M $ 124M $ 134M $ 143M $ 152M $ 156M

$ 0M

$5 000M

$10 000M

$15 000M

$20 000M

$25 000M

$M

MEMS $M forecast per applicationMarch 2013

11,7%

22,8%

11,5%

11,9%

11,6%

5,5%

6,4%

© 2013 • 6

From MEMS to combos

• Microphones, accelerometers, gyroscopes and magnetometers: > 50% of the

MEMS units to be shipped in 2012:

– Inertial detection of movement from mobile phones to pacemakers to smart Munitions

– Microphone sweet spot in the mobile phone business, replacing the electric

condenser type of microphones

• All these devices are also about to be combined with other sensors and electronic

functions/processing in order to add more value:

– Multi-microphone arrays for noise cancellation

– Accelerometers + gyros + compasses are being combined (in the same SiP package and

in the near future in silicon SOC) in order to bring a higher level of functionality at even

lower costs

Source Wolfson Source KionixSource Sensor Dynamics / Maxim Source Yamaha

© 2013 • 7

Mobile Applications are Driving Demand Today

2 axis MEMS accelerometer to ASIC module

assembly (Courtesy of Freescale)

MEMS module assembly on laminate substrate

(Courtesy of Amkor)

• Smartphone shipments are growing fast and

while the mobile industry is progressively

turning into a sophisticated sensing platforms

• In 2012, more than 300 million smartphones,

each containing at least 4 to 8 MEMS sensors

per board have been shipped

This unprecedented demand is drastically

affecting how MEMS modules will be

designed, produced and packaged!

© 2013 • 8

Key Elements of a Packaged MEMS Module

Note: some elements described here can be optional or redundant depending

on the exact design choices made by each MEMS module manufacturer

Substrate(PCB laminate, Ceramic, Leadframe)

Die attach material

MEMS die

Wire-bond interconnect

Encapsulation(metal lead, molding compound, PCB)

ASIC die

Glob-top material

MEMS microphone module(Source Knowles Acoustics)

© 2013 • 9

• Since its early beginnings, the MEMS industry faced the issue of being a highly

fragmented market, with NO manufacturing standard clearly emerging

– However, the MEMS law is changing:

– For example, in the MEMS microphone packaging area:

The “MEMS Law” is Changing…

One MEMS = 1 Device = 1 Process = 1 Package

YES!

Standards do exist here:

BGA/LGA laminate PCB

substrate

SiP module assembly with wire-

bond interconnects of ASIC die

+ MEMS die

Metal lid / PCB cap for

encapsulation with integrated

shielding

‘Hole’ for air access in the PCB

substrate on top or bottom

Teardowns courtesy SystemPlus Consulting

© 2013 • 10

MEMS die$0,491 19,4%

ASIC die$0,438 17,3%

Assembly & Packaging$0,353 14,0%

Final test & calibration

$0,232 9,2%

Yield losses$0,094 3,7%

Cost of sales, G&A, R&D, Operational

margin$0,921 36,4%

Typical Automotive Accelerometer Cost Structure in 2010

MEMS die$0,123 19,8%

ASIC die$0,102 16,5%

Assembly & Packaging

$0,084 13,6%

Final test & calibration

$0,056 9,0%

Yield losses$0,020 3,3%

Cost of sales, G&A, R&D, Operational

margin$0,234 37,8%

Typical Consumer Accelerometer Cost Structure in 2010

Yole Developpement © April 2011

Example of Cost Structure Analysis - MEMS Accelerometers(MEMS / ASIC, FE / BE module assembly &Test)

• Packaging, assembly & test steps

– Accounts for 22-25% of the MEMS accelerometer module sales price

– Accounts for 35-45% of the MEMS accelerometer manufacturing price

ASP = $2.53ASP = $0.63

Yole Developpement © April 2011

COST will be an even more important parameter to control for “fusion

combo sensors”, which are now starting to be accepted on the market

(combining multiple motion sensing functionalities in one single SiP package)

© 2013 • 11

MEMS accelerometer in 3D WLCSP

package with TGV (Courtesy of VTI / Murata)

MEMS Sensor

ASIC

Evolution Example of Inertial MEMS Hermetic Packages

MEMS die

Ceramic package

Wire Bonding

MEMS accelerometer ceramic package(Courtesy of MEMSIC)

ASIC

Cap

MEMS Sensor

MEMS accelerometer plastic package with

Wafer-level capping (Courtesy of BOSCH)

PAST…

PRESENT!

FUTURE?

Bulky form factor

High cost

Reduced form factor

Flexible supply chain

Cost reduction

Ultimate size /

cost reduction

Improved

performance

TSV / WLP package will

provide the ultimate size

and cost savings in the

long run in most MEMS

packaging applications

© 2013 • 12

3-Axis Accelerometer with TSV Cost StructureSTMicroelectronics example

STMicro MEMS accelerometer chip with TSV

(Courtesy of System Plus Consulting)

• ST announced the implementation of TSV/WLP technology

concepts in their MEMS modules in order to further reduce

the MEMS/ASIC die size (by removing all of the surface area

reserved for I/O pads down to the backside of the

ASIC/MEMS wafer surface).

© 2013 • 13

Gold BondingST Microelectronics’ LIS3DH

Triple-Axis MEMS Accelerometer

• Component specificities:

– Very compact MEMS die: 2.1mm²

– ASIC stacked on top of MEMS cap

– Advanced ASIC technology node: 0.18um

• The Reverse Engineering of STM’s latest 3-axis accelerometer (LIS3DH)

shows a different sealing technique compared to what is usually done.

• ST uses gold sealing

– 4.7mm² for the previous 3-axis in the iPhone

– 2.1mm² for LIS3DH

© 2013 • 14

2011 MEMS Packaging versus IC Packaging Market

Global IC Packaging

value ~ $43B

97%

MEMS Packaging

value~$1.3B2.9%

2011 MEMS Packaging versus IC Packaging (in $B, including Final Test value)

Yole Developpement © March 2012

Global IC Packages

203B units98%

MEMS packages5.5B units

2.4%

2011 MEMS Packages versus IC Packages (package shipments in M units)


TOT ~ 210B units

TOT ~ $44B

© 2013 • 15

0

50

100

150

200

250

300

350

2010 2011 2012 2013 2014 2015 2016

186B units203B units

221B units241B units

263B units

286B units

312B units

4.7 Bu 5.8 Bu 7.3 Bu 8.9 Bu 10.6 Bu 12.2 Bu 14.1 Bu

MEM

S p

acka

ges

ship

men

ts (

in B

un

its)

MEMS Packages versus IC Packages Shipment forecast (in B units)


MEMS Package vs. IC Package Unit Growth

© 2013 • 16

Conclusions & Perspectives

• The number of MEMS and sensors going into mobile, consumer and

gaming applications is expected to continue to skyrocket

– As a result, OSAT and Wafer foundry players are getting more and more

interest in MEMS module packaging, as volume and complexity of MEMS SiP

modules is increasing dramatically. It implies:

IDMs needs to find second source partners and qualify some OSATs in order to

secure their supply chain

Standardization (coming from both foundries, OSAT, WLP houses or substrate suppliers)

is critical and necessary to implement in order to keep the packaging, assembly,

and test cost of MEMS modules under control

• There are many different players with different designs, and it’s not likely

we’ll see one solution adopted by all the players

© 2013


WLP for LED

© 2013 • 18

WLP for LEDs

Overview of Chip to Wafer LED WLP process

Source: Yole Développement/Hymite

Note: In this example, the LED chips are singulated before being

positioned onto the package wafer (“Chip to Wafer” packaging).

Solder / Metallization

Packaging wafer

Mirror

coating

Solder

Bump

Mirror

coating

Solde

r

Bump

LED wafer

LED dies

1) Wafer level preparation of

the bare package (cavity

etching, SiO2 insulation

layer, via/bump

interconnects, mirrors, etc.).

2) LED die separation & pick

and place positioning on the

package wafer.

3) Wafer level interconnect,

phosphor deposition,

encapsulation and optic

4) LED package separation

PhosphorWafer Level Optic

© 2013 • 19

WLP for LEDs

Wafer Level

Phosphor

Wafer Level

Encapsulation/

Optics

Wafer Level

BumpingElectrical Redistribution

WLP operations

for High-Power

LEDs

Wafer level coating of

reflective layer

Embedded Zener

diodes

Wafer to Wafer

BondingLED on package substrate

Patterned substrate for

low thickness under

LED

3D Silicon

Substrates

Packaging operations are not YET combined altogether in a single LED package

© 2013 • 20

Manufacturing Status of WLP

Leadframe-

Based

Packaging

Wafer Level Packaging Technologies

With Si Wafer Cap/Interposer (WLSP)

Packaging Type

Metallized

ceramic

HB LED with

silicon

submounts

True WLP

Wafer Level

Bumping/

Electrical

Redistribution

Wafer Level

Encapsulation/

Optics

Wafer Level

Phosphor

Wafer to Wafer

Bonding

Manufacturing

StatusHigh-Volume

Production

Very Small

ProductionR&D

Manufacturing status of WLP

Source: Lumileds - Hymite - ITRI - ChipMOS Patent - MicroChem

© 2013 • 21

Silicon Substrate for WLP

• Main drivers for Si LED WLP:– Excellent thermal properties → Si substrates have high thermal conductivity (> 150W/m.K),

further improved by the use of copper-filled Through Silicon Vias (TSV).

– Robustness/Reliability → Monolithic assembly with reduced wire interconnect and good CTE

match with GaN.

– Small form factors → Ultra-thin and compact packages

– High reflectivity cavity with mirror coating (> 90% reflectivity) → Improved performance.

– Wafer level manufacturing (phosphor, optic, etc.) & Wafer level testing

– Reduced cost → Wafer level manufacturing, isolation realized by oxidation (Si + O2 → SiO2).

– Possibility of manufacturing intelligent/smart LED modules.

• Main challenges:– Copper-filled TSVs for 3D electrical redistribution and heat dissipation are still expensive.

– Mechanical strength of Si could also induce difficulties.

Flip chip structure mounted on

a Si substrate

Source: Advanced

Photoelectronic Technology

Silicon Wafer Level Packaging

Source: NeoPacThe use of Silicon substrates remains marginal and is essentially

limited to companies using the Wafer Level Packaging (WLP)

process.

© 2013 • 22

Si players

6” Wafer 8” Wafer 12” WaferUnknown

Size

Other WLP Operations

Silicon Substrates

http://www.viseratech.com/English_index.htm

http://www.philipslumileds.com/

© 2013 • 23

Long-Term Vision of WLP

• Silicon substrate with

embedded ESD protection

and Through Silicon Vias

• Flip Chip (microbumping)

Wafer Level Packaging

a) Wafer level optics (lens)

b) Wafer level phosphor

c) Wafer bonding LED - Substrate

LED

b)

a)

c)

© 2013 • 24

Conclusions on LED

• Wafer Level Packaging has not been strongly deployed in the LED industry due to

associated technical challenges. We still estimate that:

– In the short-term ESD integration in Si substrate.

– In the long-term LED drivers could be integrated at the package level for IntelligentLighting.

– Ultimately, Wafer to Wafer manufacturing schemes for certain package types.

• Real production of HB LEDs with a mixed approach of “Wafer Level Packaging

(WLP) + Through Silicon Vias (TSV)” is just starting

– Taiwanese players such as TSMC/Xintec/Visera, Touch Micro Tech, Sibdi and South Korea-based LG Innotek.

• Additional players in the semiconductor and MEMS industry are seeking to enter

the field

– Leverage equipment and technology platforms for economies of scale.

© 2013


POWER

© 2013 • 27

Packaging for power Modules and high temperatureModule packaging - Definition

Heatsink

Thermal grease

Substrate

SBD IGBT

Baseplate

DBC

Busbar connection

Solder

Copper metallization

Plastic case

© 2013 • 28

Packaging for power Modules and high temperatureModule packaging - Definition

Heatsink

Thermal grease

Substrate

SBD IGBT

Baseplate

DBC

Busbar connection

Solder

Copper metallization

Plastic case

• Common failure in a power module is caused by thermal cycling.– Mismatching CTE make layers to detach one from the other.

– Some gel filling also cannot handle high temperature

Die attach

Interconnection

Gel filling

Substrates attach

In red: Common failure locations

© 2013 • 30

Packaging for power Modules and high temperatureTrends in power module packaging

Current solutionsWidely used by all players

Emerging techno’sAt mass production and

growing in market shares

Potential breakthroughAt R&D stage. Still too expensive

Pb/Sn alloy

Or SCA alloy

Silver micro powder

sintering

Al wire bonding

Al ribbon bonding

Copper wire

bonding

Baseplate + heatsink

AlSiC for long lifetime

Al2O3 for cost

Thermal exchange

improvements:

• Showerpower©(danfoss)

• Double sides cooling

• DBC to heatsink

(no baseplate)

• Micro-channel cooling

• Convection using Wide

band gap

Nano powder

sintering (no heating

and pressure for

attach process)

Foil sintering

Foil ultrasonic wedge

bonding

© 2013 • 31

The Final Word …

MEMS, LEDs, Power but

also CIS, PV … all these

derivative application areas

are a real gold mine of

technological innovations,

driven by different

challenges which we usually

meet in mainstream

packaging!...

Derivative applications are a real gold mine of ...€¦ · Derivative applications are a real gold...

Documents

Transcript of Derivative applications are a real gold mine of ...€¦ · Derivative applications are a real gold...