DEPFET Electronics

DEPFET Electronics

Ivan Peric, Mannheim University

DEPFET Electronics

Content

Gate / Clear steering chips: SWITCHERRequirementsSWITCHER2

Drawbacks

SWITCHER3Block diagramHV Switch & Level ShifterGeometryMeasurements Irradiation

Drain Readout ChipsRequirementsCURO reminderDCD

ArchitectureNoise, Speed, Power

Switcher

DCD

DEPFET Electronics

Readout Chips – Critical Parts

HV buffer

DEPFET current receiver

(regulated cascode)

ADC/comparator

Analog memory cell

Switchers

DCD/CUROLevel

Shifter

DEPFET Matrix

DEPFET Electronics

Readout Chips – Critical Parts

HV buffer

DEPFET current receiver

(regulated cascode)

ADC/comparator

Analog memory cell

Switchers

DCD/CUROLevel

Shifter

DEPFET Matrix

20pF in 5ns from 0 to 10 V- 40 mA current!

20pF

20pF

DEPFET Electronics

Readout Chips – Critical Parts

HV buffer

DEPFET current receiver

(regulated cascode)

ADC/comparator

Analog memory cell

Switchers

DCD/CUROLevel

Shifter

DEPFET Matrix

40pF

DEPFET Electronics

Regulated Cascode

A

40pF!

Small voltage change – 12.5uV

Fast response (~ 20ns)

DEPFET

RO Chip

Current noise

Signal current – 50nA ~ 100e

Current signal^^

DEPFET Electronics

Module

DEPFET Electronics

SWITCHER:REQUIREMENTS

DEPFET Electronics

SWITCHER Requirements

Small and thin(minimum material)

Small Power dissipation(no massive cooling in the inner region)

Switch voltages of up to ~10V(7V required for clear)

Rise/fall times of <10ns for a load of 20pF.Radiation tolerance to some 100kradBump bonding padsMinimal number of IO signals

(These must be routed along the narrow balcony)Programmable switching pattern

(Skip broken rows, read region with high occupancy more frequently)Many chips must be operated in parallel with no overhead

DEPFET Electronics

SWITCHER 2

DEPFET Electronics

Switcher 2

64 channels with 2 analog outputCan switch up to 25 Vused very successfully for all existing matrix setups

digital control ground + supply floatingfast internal sequencer (up to 80MHz)Daisy chaining of several chips (token out)

0.8µm AMS HV technology – bad radiation tolerance! Power dissipation:1mW/channel @ 30MHz (level shifter)

4.6 mm

4.8

mm

1 0 1 1

U = 20V = 30 MHz

20ns

20V !

Pads for daisy chain

control

inputs

2 x 64 outputs

with spare pads

Switching 20V @ 30MHz

DEPFET Electronics

SWITCHER 3

DEPFET Electronics

Switcher3 Requirements / Features

10V switching low voltage 3.3V transistorsneeds twin-well technology (AMS h35b4)capacitive coupling of digital and analog blocks

radiation hard design

~ 20pF gate/clear capacitance

fast signal edges: ~ 5 ns fall time

128 channels

Sequencer with non trivial switching sequencesLow powerbump pitch of 180 µm, allows pixel sizes down to 24 µm

DEPFET Electronics

HV Switch with Stacked Transistors (assume 3V per stage)

all OFF

9 V

all ON 9V

9V

9V

6V

3V

0V

0V

3V

6V

6V

6V

6V

all ON

0 V

all OFF 9V

6V

3V

0V

0V

0V

3V

3V

3V

3V

6V

9V

0V

9V

3V

6V

6V

9V

3V

6V

6V

0V

3V

0V

9V

3V

DEPFET Electronics

Level shifting by AC coupling – no DC current

Use an SRAM cell flipped by a transient voltageNo dc power consumption!

9V

out

‘SRAM’

3V

‘SRAM’

6V

‘SRAM’

‘SRAM’

0V

3V

6V

ResetReset

~200 fF

DEPFET Electronics

Switcher 3 Layout

full chip:5.8 x 1.24 mm2

upper part(rotated)

one HV switch with 80µm bump

pad

180µm pitch

128 output channels

DEPFET Electronics

Switcher 3 Layout Details

Sequencer RAM, row buffers, readout(M2-M4 not shown)

HV channel with 3+3 Switch transistors and 4 AC coupling stages (180x180µm, M4 not shown)

interdigitatedAC coupling caps

Ivan Peric, Mannheim

80µmopenin

g

DEPFET Electronics

Measurements

DEPFET Electronics

Short Pulses: Internal Strobe Generator

1ns

Delay=2 (3.5ns)

Delay=12 (5.5ns)

9V several pF load

DEPFET Electronics

Sequencer - Maximum Speed with Cload ~ 25pF

10ns

9V

DEPFET Electronics

SWITCHER3 Power Dissipation Summary

Consumption for 20pF, clocked at 20MHz, supplied with 3V (digital) and 9V(analog):

Active Chip:~ 18mW (digital)~ 45mW (analog)

Idle Chip:~ 18mW (digital)~ 0 (analog)

Sleeping chip (later, will use ‘hibernation’ mode to disable majority of digital part):

< 5mW (digital)~ 0 (analog)

DEPFET Electronics

0,0 0,1 0,2 0,3 0,4 0,50

20

40

60

80

100

120

140

160

Cu

rre

nt [

µA

]

Gate Voltage [V]

Irradiation of SWITCHER3 Rest Chip

X-ray irradiation up to ~600 kradNo (significant) threshold shift or leakage current for annular structures

0,0 0,1 0,2 0,3 0,4 0,50

10

20

30

40

50

Cur

rent

[µA

]

Gate Voltage [V]

600 krad

before

stacked ‘normal’annular NMOS

‘HV’ NMOS, normal layout

DEPFET Electronics

SWITCHER3 Summary

all parts of chip are working150MHz max speed45mW analog for 20pF load @20MHz (for the single active chip)18mW digital @20MHz8ns settling time from 0V to 9V on rising edge6.5ns settling time from 9V to 0V on falling edgeProgrammable Sequencer which allows complicated readout sequences

(200MHz)

Next Stepsirradiation of full chipcontinue long term stress test (no failures after 6 weeks)operation with DEPFET matrices

DEPFET Electronics

Drain Readout:REQUIREMENTS

DEPFET Electronics

Requirements for Drain Readout Chips

Basic ArchitectureCascode circuit to sense the tiny drain current.

The noise contribution of this cascode must be minimized.

Bus capacitance ~ 40pFCurrent subtraction

(signal / pedestal) Analog memory cells

Process the difference signal

Accommodate a drain pitch of 12µmWe address this by using bump bonding in DCD.

(double) row rate: ~ 20MHz. (This corresponds to 40MHz pixel row rate.)Noise charge: < 200 electronsPower: as low as possible while still reaching speed and noise requirements...Radiation tolerance: to some 100kradProcess Iped ~ 30µA, Isig ~ 6µA (i.e. 12000 Electrons at gq=0.5nA/e)

DEPFET Electronics

CURO

DEPFET Electronics

CURO Drain Current Readout Chip

0.25µm TSMC, mostly enclosed transistors

Current comparator finds hits

Current Difference and hit-flag stored in mixed FIFO

Fast Hit-Finder scans FIFO for up to 2 hits per cycle:analog currents to outA, outB

digital hit position stored in HIT-RAM

128 channels

Drawbacks:

Regulated cascode is too weak

Difficult shielding due to technology limitations – cross-talk

DEPFET Electronics

DCD

DEPFET Electronics

DCD features

UMC 0.18µm 1.8V technologySimilar FE part like CUROone >= 7bit ADC per channel

In reality, two independent ADCs work in parallelThey are implemented as algorithmic ADCs144X2 ADCs on final chip

Digital zero suppression – can be implemented in FPGA massive parallel high speed digital output @600MHz, 18 LVDS outputs

Bump bonding with pixel logic & ADC placed around padRadiation Hard Design (in analog part)NMOS in triple Well, guard ring around analog part

Expected power dissipation ~ 4.2 mW per column.

DEPFET Electronics

Test Chip DCD

Pixels are 110x180 µm2Input Matrix only 6 x 12 for nowbut can be easily extended to full size 8 x 18

DEPFET Electronics

Regulated Cascode: CURO vs. DCD

1V

low gm

1mA

0.3mA

30 nA noise for 40 pF input capacitance an rise time of 25ns

@ 1.24mW

DCD

high gm

Low voltage

lower noise

Improvers stability

CURO

Block scheme

DEPFET Electronics

Regulated Cascode

0 10 20 30 40 50 60 70 80 90 1000

1

2

3

4

5

Cascode Output Current

Ou

tpu

t Cu

rren

t/uA

Time/ns

1V25ns rise time

DEPFET Electronics

Current-Memory cell CURO vs. DCD

Non linear charge error

Linear geometry NMOS – poor rad. harness

Enclosed geometry – too high gm

Constant charge error

PMOS

Nearly linear U-I converter

24uA

12uA

24uA

CURO

DCD

DEPFET Electronics

Novel Current Memory Cell

150 200 250 300 350 400 4500,75

0,80

0,85

0,90

0,95

1,00

Memory cell output Voltage

Vol

tage

/V

Time/ns

420 422 424 426 428 430 432 434 436 438 4400,0

0,2

0,4

0,6

0,8

1,0

M. cell output voltage

Vol

tage

/V

Time/ns

10 ns rise time

60 nA noise

DEPFET Electronics

DCD Channel

Generate ADC+ memory cell control signals

ADC SteeringSignals

2 ADCs

ADC result calculation,

MUX

18 per column

sync for FPGA, Switcher

Serializer 3 x serout @ 600MHz

per column

2 x 18 lines

per pixel

SamplingIsig

RegulatedCascode

SamplingIsig + Iped

Clock Divider

Algorithmic ADC uses 4 current memory cells- Small Layout

- Low power operation – important for new technologies

- does not rely on transistor matching and

- allows rad-hard design

- pipeline architecture possible

- currently: 7 bit in 60ns or 9 bits in 80ns

- 2mW/channel

- 110 microns X 50 microns

600MHz

DEPFET Electronics

DCD Pixel Layout

bump pad with60µm opening

two 8 bit algorithmic

current mode ADCs working

interleaved

regulated cascode

test injectio

n

digital stuff(conservativ

e layout)

Size x: 180µmSize y: 110µm

DEPFET Electronics

DCD Summary

Test Chip has been submittedWe expect 80 ns drain readout with 40pF, 9-bit ADC accuracy bin size 30 nA,

noise ~ 60nAOr 60ns drain readout speed with 40pF, 7-bit bin size 120 nAExpected power dissipation ~ 4.2 mW per column

DEPFET Electronics

Thank you for attention!

DEPFET Electronics

Current-Mode ADC

Mux

Mux 22

Ck

8 periodes = 160ns

Sample

1mW

1mA

Sample

Sample

GCG GCGSwitcher

ADC1

ADC2

DEPFET Electronics

Current-Mode ADC

Mux

Mux 22

Ck

8 periodes

Sample

1mW

1mA

Sample

GCG GCGSwitcher

ADC1

ADC2

DEPFET Electronics

Current-Mode ADC

Mux

Mux 22

Ck

8 periodes

Sample

1mW

1mA

Sample

GCG GCGSwitcher

ADC1

ADC2

DEPFET Electronics

Current-Mode ADC

Mux

Mux 22

Ck

8 periodes

Sample

1mW

1mA

Sample

GCG GCGSwitcher

ADC1

ADC2

DEPFET Electronics

Current-Mode ADC

Mux

Mux 22

Ck

8 periodes

Sample

1mW

1mA

Sample

Sample

GCG GCGSwitcher

ADC1

ADC2

DEPFET Electronics

Current-Mode ADC

Mux

Mux 22

Ck

8 periodes

1mW

1mA

Sample

Sample

GCG GCGSwitcher

ADC1

ADC2

DEPFET Electronics

Current-Mode ADC

Mux

Mux 22

Ck

8 periodes

Sample

1mW

1mA

Sample

GCG GCGSwitcher

ADC1

ADC2

DEPFET Electronics

Current-Mode ADC

Mux

Mux 22

Ck

8 periodes

Sample

1mW

1mA

Sample

GCG GCGSwitcher

ADC1

ADC2

DEPFET Electronics

Current-Mode ADC

Mux

Mux 22

Ck

8 periodes

1mW

1mA

Sample

Sample

GCG GCGSwitcher

ADC1

ADC2