Slide 1

K. Nakajima1, S. Sato1, K. Kakushima2, P. Ahmet1, K. Tsutsui2,A. Nishiyama2, N. Sugii2, K. Natori1, T. Hattori1, H. Iwai1

1 Frontier Resarch Center, Tokyo Institute of Technology2 Interdisciplinary Graduate School of Science and Engineering

Dependence of Interface State Density on Three Dimensional Silicon Structure measured by Charge Pumping Method

Tokyo Institute of Technology

220th ECS Meeting

Slide 2

Outline

• Introduction– Three Dimensional Si Structure– Purpose of this work

• Characterization• Device Fabrication• Results and Discussions• Conclusions

Slide 3

Introduction: MOS devices with 3D channels

Nanowire FET

Si subBOX

Source

GateDrain Si Nanowire

Excellent short channel effect immunityby better gate control of the channel potential

MOSFETs with 3D channel enables futher device scaling

Si subBOX

Source

GateDrain

Source Drain

Gate

BOX

Source Drain

Gate

Si sub

Multi Gate FET

Planar bulk FET

Planar SOI FETMOS devices with 3D channels

Planar MOS devices

Slide 4

3D channels are defined by plasma etching with oxidation process: the surface consists of various crystallographic orientations.

Direct measurement of Dit with 3D channel is important

Wfin

BOXSub.

Hfin

(100)(110) Gate

Introduction: interface state density of 3D channel

Interface state density (Dit) is strongly dependent on surface orientations

Slide 5

Purpose of this Work-Direct measurement of Dit of 3D channels

Charge pumping methode on PIN diodeswith 3D Fin structures

-Geometric separation of the DitMeasurement of PIN diodes with diffrentFin width (same Fin height)

Hfin

Wfin Wfin+∆W Wfin+2∆W

Slide 6

Charge pumping (CP) method for Dit extraction

PIN Gated Diode

Vg=Vamp+Vbase: electrons are injected into the channel→ charge trapping at SiO2/Si

Vg=Vbase: holes are injected to recombine with thetrapped electrons → charge pumping current (Icp)

tr : rise timetf : fall time

Vgamp

Vbase

tr tfSi Sub.

n

IcpW Gate

BOXN+ P+

Trapezoidal pulse

e- h+

Vbase

Slide 7

A typical Icp obtained from CP method

0.0E+00

2.0E-09

4.0E-09

6.0E-09

8.0E-09

1.0E-08

1.2E-08

1.4E-08

-5 -4 -3 -2 -1 0 1 2

-5 -4 -3 -2 -1 0 1 2

14121086420

Vbase(V)

I cp(

nA)

Vamp = 3(V)f = 500(kHz)tr = 100(nsec)Vr= -0.05(V)

tf=100(nsec)200(nsec)300(nsec)400(nsec)

Maximum Icp value is corresponds to the Dit valueDifferent tf gives the distribution of Dit within the bandgap (Eg)

Vgamp

Vbase

tr tftr : rise timetf : fall time

Icp = fQcp = fqAGDit∆E

Slide 8

PIN diode fabrication

Si Sub.BOX

W

Si Sub.BOX

SiO2

Si Sub.BOX

WN+

Si Sub.BOX

WP+N+

Si Sub.BOX

WP+N+

Al

100

BOX

N+ P+

W

Fin PatterningStarting wafer：p type 140ohm-cmSOI wafer (100)-orientedSOI layer (70nm) / BOX layer (50nm)

Gate oxide film formation by a dry oxidation at 1000 oC for 10min.

W film deposition by RF sputtering

P implantation (Phosphorus, 30keV, 3×1014 cm-2)

BF2 implantation (Boron , 30keV, 3×1014 cm-2)

Activation annealing in N2 gas ambient at 800 oC for 5min.

Al contacts deposition by thermal evaporation (source and drain regions and back side )

Annealing in F.G. ambient at 300 oC to 440 oC by 20 oC steps for 30 min.

Si

BOX 50nm

Hfin70nm

Wfin80nm

W

100nm

Slide 9

1.00E+10

1.00E+11

1.00E+12

1.00E+13

0.28 0.29 0.30 0.31 0.32

1.00E+10

1.00E+11

1.00E+12

1.00E+13

-0.32 -0.31 -0.30 -0.29 -0.28

F.G. Annealing temperature dependence of Dit

E-Ei(eV)

1012

1011

1010

Optimum F.G. annealing temperature at 400 ~ 420oC; similar to SiO2/Si(100) case*

0.320.28 0.30-0.28-0.30-0. 32

As fabricated

420℃

300℃320℃340℃360℃380℃400℃

1013

Wfin=110nmVgamp=3VHfin=70nmD

it(cm

-2/e

V)

Wfin=110nm, Hfin=70nm

P. L. Castro et al., SOLID STATE SCIENCE, Vol. 118, No.2, pp. 280-286 (1971).

Slide 10

1.00E+10

1.00E+11

1.00E+12

0.28 0.29 0.30 0.31 0.32

1.00E+10

1.00E+11

1.00E+12

-3.20E-01 -3.10E-01 -3.00E-01 -2.90E-01 -2.80E-01

Dit dependence on Wfin

E-Ei(eV)

1012

1011

1010

Dit(

cm-2

/eV

)

With smaller Wfin, Dit increses, especially toward midgap region

Fin structure has higher Dit value than SOI planar case in any energy

0.320.28 0.30-0.28-0.30-0. 32

Vgamp=3V

F.G. anneal temparture：420oC

W=105nm

W=95nmW=100nm

W=90nm

Hfin=70nm

Planar SOI

Slide 11

Geometric separation of Dit

BOXSub.

Top surface (100)Dit,top

Side surface (110)Dit,side

known

Dit =Wfin x Dit,top + 2Hfin x Dit,side

Wfin+ 2Hfin

By assuming Dit at top (Dit,top) and the side surface (Dit,side), we can separate those contribution in the measured Dit using differnet Wfin PIN diodes

*Note, Dit,side includes the Dit of corners

Slide 12

1.00E+11

1.00E+12

0 50 100 150

1012

1011

Dit(

eV-1

cm-2

)

0 50 150 200Wfin(nm)

Hfin=70nm

Dit of side surface

Best fit gives values of 1.3x1010 cm-2/eV for top surface and 2.6x1011 cm-2/eV for side surface.

Separation of Dit from top and side surfaces

BOXSub.

Top surface (100)Dit,top~ 1.29x1010cm-2/eV

Side surface (110)Dit,side~ 2.61x1011cm-2/eV

Slide 13

Conclusions

Interface state density of Fin structure was measured by fabricating PIN diodes with charge pumping method

Optimum temperatrue for F.G. annealing is 400~420 oC, same as planar Si(100)

Narrorer Fin width results in large Dit

From Fin width dependency, Dit of 1.3x1010 cm-2/eV for top surface and 2.6x1011 cm-2/eV were extracted

Slide 14

Acknowledgments

This work has been supported by NEDO.

Thank you for your attention!

Slide 15

Slide 16

Slide 17

INDIRECTTECHNIQUES

DIRECTTECHNIQUES

MOS Capacitors

• LF-CV• HF-CV

• Conductance(without gate leakage)• DLTS

MOS Transistors

• Weak inversion• 1/f Noise

• Current DLTS• DCIV• Charge pumping

Interface characterization techniques

Classification of interface characterization techniques

Slide 18

Charge pumping method

Sub.

W Gate

p+

Sub.BOX

n+

Icp

e- h+

Planar bulk FET SOI FET

W Gate

n+ n+

e-

p-Sub.

Icp

e-

The PiN gated-diode allows direct measurement of CP current thanks to the p+ region which acts as a ‘substrate’ contact.

Slide 19

⊿Vg

tr tf

⊿Vg

tr tf

W Gate

n+ n+

e-

p-Sub.

Icp

e-

蓄積ソース/ドレインから電子がトラップ

反転基板へ電子がトラップ

Interface characterization techniques

Accumulation

Inversione- in traps to substrate

e- from source/drainto traps

Slide 20

1.00E+10

1.00E+11

1.00E+12

1.00E+13

0.28 0.29 0.30 0.31 0.321.00E+10

1.00E+11

1.00E+12

1.00E+13

-0.32 -0.31 -0.30 -0.29 -0.28

1010 W=110nm

0.320.28 0.30-0.28-0.30-0. 32

Vgamp=3V

1013

1012

1011

Dit(e

V-1

cm-2

)

420℃440℃

E-Ei(eV)

F.G. Annealing temperature dependence of Dit

Optimum F.G. annealing temperature at ~ 420oC

Slide 21

1.00E+11

1.00E+12

-0.32 -0.30 -0.28

1.00E+11

1.00E+12

0.28 0.30 0.32

Energy profile Dit(E) for a wide and long Planar SOI MOSFETs

Near the band edges - both conduction band and valence band -the Dit increases

Vgamp=3VL=60µm W=3.5µm

F.G. anneal temparture：420oC1012

1011

Dit(

eV-1

cm-2

)

-0.32 -0.30 -0.28 0.28 0.30 0.32

Slide 22

D. Schroder, “Semiconductor material and device characterization”, 3rd edition, Willey Interscience, 2006

(111)

(100)

Reference

D. Schroder, “Semiconductor material and device characterization”, 3rd edition, Willey Interscience, 2006