Department of Electronics and Communication Engineering...

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Department of Electronics and Communication

Engineering

Academic Year 2017-18

M.Tech in VLSI Design and Embedded Systems

First and Second Semesters

Scheme and Syllabus

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NEW HORIZON COLLEGE OF ENGINEERING

VISION

To emerge as an institute of eminence in the fields of engineering, technology and management in serving the industry and the nation by empowering students with a high

degree of technical, managerial and practical competence

MISSION

To strengthen the theoretical, practical and ethical dimensions of the learning process by fostering a culture of research and innovation among faculty members and students.

To encourage long-term interaction between the academia and industry through the

involvement of the industry in the design of the curriculum and its hands-on implementation

To strengthen and mould students in professional, ethical, social and environmental

dimensions by encouraging participation in co-curricular and extracurricular activities.

QUALITY POLICY

To provide services of the highest quality both curricular and co-curricular; so that our students can integrate their skills and serve the industry and society equally well at a

global level.

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CREDIT SCHEME FOR FIRST SEMESTER M.TECH VLSI DESIGN AND EMBEDDED SYSTEMS

Credit Marks

Course Course BoS Distribution Overall

S.No Code

Credits

L P T S CIE SEE Total

1 VLE11 Applied Mathematics SCI 4 0 0 0 4 50 50 100

2 VLE12 Digital VLSI Design ECE 4 1 0 0 5 75 75 150

3 VLE13 Advanced Embedded

ECE 4

0 0

1 5 50 50 100

Systems

4 VLE14x Specialization Elective-1 ECE 4 0 0 1 5 50 50 100

5 15NHG15x Global Elective-1 ECE 4 0 0 1 5 50 50 100

6 VLE16 Seminar ECE 1 50 50 100

Total 25 325 325 650

Specialization Electives –I

S.No Course Code Course S.No Course Course

Code

1 VLE141 VLSI Subsystem Design 3 VLE143 Software Technology for

Embedded Systems

2 VLE142 VLSI Process Technology 4 VLE144 SoC Design

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CREDIT SCHEME FOR SECOND SEMESTER M.TECH VLSI DESIGN AND EMBEDDED

SYSTEMS

Specialization Electives –2

S.No Course Code Course S.No Course Code Course

1 VLE 241 Low Power and High 3 VLE 243 Embedded Communication

Speed VLSI Design and Software Design

2 VLE 242 VLSI Testing and 4 VLE 244 Wireless Sensor Networks

Verification

Credit Marks

Course Course BoS

Distribution Overall

S.No Code

Credits

L

P T

S CIE SEE Total

1 VLE21 Analog Integrated Circuit

ECE 4

0 0

1 5 50 50 100

Design

2 VLE22 Real-time Operating

ECE 4

1 0

0 5 75 75 150

Systems

3 VLE23 Embedded Networking ECE 4 0 0 0 4 50 50 100

4 VLE24x Specialization Elective-2 ECE 4 0 0 1 5 50 50 100

5 15NHG25x Global Elective-2 (TBA) ECE 4 0 0 1 5 50 50 100

6 VLE 26 Seminar ECE 1 50 50 100

Total 25 325 325 650

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FIRST SEMESTER

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APPLIED MATHEMATICS

Course Code : VLE11 Credits :04

L:P:T:S :4:0:0:0 CIE Marks :50

Exam Hours :03 SEE Marks :50

Course Outcomes (CO):

To develop the ability to use concepts of Linear Algebra and Calculus of Variations for solving problems related to VLSI and Communication Engineering.

To understand the nuances of various partial differential equations and their solutions using mathematical transforms and graph theoretic algorithms as applied to VLSI and Communication Engineering.

Module 1

Eigen Value and Boundary Value Problems:

Eigen values and Eigen Vectors: Gerschgorian circle, Eigen values and Eigen vectors of

real symmetric matrix by Jacobi and Givens method. Solutions of Boundary Value

Problems by finite difference method. 9 Hrs

Module 2

Linear Transformation: Linear Transformation: Introduction to Linear Transformation, The matrix of Linear Transformation, Linear Models in Science and Engineering. Orthogonality and Least Squares: Inner product, length and orthogonality, orthogonal sets, Orthogonal projections, The Gram-Schmidt process, Least Square problems, Inner product spaces.

8 Hrs

Module 3

Calculus of variation: Concept of functional-Euler’s equation- functional dependence of first and higher order derivatives- functional on several dependent variables- iso perimetric problems.

9 Hrs

Module 4

Transform Methods:

Solution of one dimensional Heat, Wave and Laplace equation by method of suppuration of variable and Cylindrical polar co ordinates. D’Alemberts solution of Wave Equation, Laplace transform methods for one dimensional wave and heat equation.

9 Hrs

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Module 5

Graph Theory & Algorithms:

Computer representation of graphs and diagraphs, combinatorial optimization shortest

path problems complexity, complexity of algorithm. Dijkstra algorithm for shortest path,

shortest spanning tree & flow in networks. 9 Hrs

Text Books: 1. Erwin Kreyszig –Advanced Engineering Mathematics –Wiley publication–

10th

edition–2004

2. B. S. Grewal –Higher Engineering Mathematics –Khanna Publishers –40th

edition – 2007.

3. Dr. B.S. Grewal, “Numerical Methods in Engineering and Science”, Khanna Publishers, 1999

4. Dennis G. Zill , Michael R. Cullen–“Advanced Engineering Mathematics”, Jones and Barlett Publishers Inc. –5th edition–2012.

5. K.Sankar Rao - Introduction to Partial Differential Equations PHI Learning publisher

-2010

Reference Books:

1. Pervez Moin, Fundamentals of Engineering Numerical Analysis, Cambridge, 2010. 2. David. C. Lay, Linear Algebra and its applications, 3rd edition, Pearson Education,

2002. 3. S.S.Sastry, Introductory Methods of Numerical Analysis, PHI, 2005. 4. M K Jain, S.R.K Iyengar, R K. Jain, Numerical methods for Scientific and engg.

computation, New Age International, 2003.

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DIGITAL VLSI DESIGN

Course Code : VLE12 Credits : 05

L:P:T:S : 4:1:0:0 CIE Marks : 75

Exam Hours : 03 SEE Marks : 75


This course deals with the circuit design using MOS devices.

To understand the concepts of characterization and simulation of CMOS circuits. To apply the device knowledge in the design of combinational and sequential

circuits.

Module 1

Circuit characterization:Delay estimation, Logical effort and transistor sizing, Power

dissipation, Interconnect, Design margin, Reliability, Scaling. 8 Hrs

Module 2

Circuit simulation:A SPICE tutorial, Device models, Device characterization, Circuit

characterization, Interconnect simulation. 8 Hrs

Module 3

Combinational circuit design: Circuit families, More circuit families, Low-power logic design, Comparison of circuit families

9 Hrs

Module 4

Sequential circuit design: Sequencing static circuits, Circuit design of latches and flip-flops, Static sequencing element methodology, Sequencing dynamic circuits, Synchronizers.

10 Hrs

Module 5

Coping with Interconnect: Capacitive parasitics, Resistive parasitics, Inductive parasitics,

Advanced Interconnect Techniques, Networks-on-a-Chip. 9 Hrs

VLSI Design and Embedded Systems Lab -1

Lab Objectives:

To know and understand Verilog and design circuits using it.

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To study and verify the combinational and sequential logic circuits with various

levels of modeling and EDA Tools. To use any EDA tool to learn the embedded hardware design and PCB design. To familiarize different entity for the circuit diagram design. To employ ARM CORTEX M3 for embedded programming.

I VLSI Digital Design

(A) ASIC-Digital Design Flow 1. Write Verilog Code for the following circuits and their Test Bench for verification,

observe the waveform and synthesize the code with technological library(constraints to

be given). Do the initial timing verification with gate level simulation. 1.1 An inverter, Buffer and Transmission gate 1.2 Basic/universal gates 1.3 Flip flop-RS, D, JK, MS, T 1.4 Serial & Parallel adder 1.5 4-bit counter [Synchronous & Asynchronous counter]

(B) FPGA DIGITAL DESIGN

VLSI Front End Design programs:

Programming can be done using any complier. Down load the programs on FPGA/CPLD

boards and performance testing may be done usingpattern generator (32 channels and

logic analyzer )/ Chipscope pro apart from verification by simulation with any of the front

end tools.

1. Write Verilog code for the design of 8-bit i) Carry Ripple Adder ii) Carry LookAhead adder iii) Carry Skip Adder iv) BCD Adder & Subtracter

2. Write Verilog Code for 8-bit Array Multiplication (Signed and Unsigned) i) Array Multiplication (Signed and Unsigned) ii) Booth Multiplication (Radix-4)

3. Write Verilog code for 4/8-bit i) Magnitude Comparator ii) LFSR iii) Parity Generator

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iv) Universal Shift Register

4. Write Verilog Code for 3-bit Arbitary Counter to generate 0,1,2,3,6,5,7 and

repeats.

5. Design a Mealy and Moore Sequence Detector using Verilog to detect Sequence.

Eg 11101 (with and without overlap) any sequence can be specified.

6. Design a FIFO and LIFO buffers in Verilog and Verify its Operation.

7. Design a coin operated public Telephone unit using Mealy FSM model

with following

operations: i) The calling process is initiated by lifting the receiver. ii) Insert 1 Rupee Coin to make a call. iii) If line is busy, placing the receiver on hook should return a coin iv) If line is through, the call is allowed for 60 seconds at the 45th second prompt

another. 1 Rupee coin to be inserted, to continue the call.

v) If user doesn't insert the coin within 60 seconds the call should be terminated. vi) The system is ready to accept new call request when the receiver is placed on

the

hook.

vii) The FSM goes 'out of order' state when there is a Line Fault.

Note: Implementing the above designs on Xilinx/Altera/Cypress/equivalent based

FPGA/CPLD kits.

II Embedded Systems

1. Use any EDA (Electronic Design Automation) tool to learn the Embedded

Hardware Design and for PCB design. 2. Familiarize the different entities for the circuit diagram design. 3. Familiarize with the layout design tool, building blocks, component placement,

routings, design rule checking etc.

ARM-CORTEX M3

[Programming to be done using Keiluvision 4 and download the program on to a M3

evaluation board such as NXP LPC1768 or ATMEL ATSAM3U].

1. Write an Assembly language program to calculate 10+9+8+.........+1

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2. Write an Assembly language program to link Multiple object files and link them

together. 3. Write an Assembly language program to store data in RAM. 4. Write a C program to Output the "Hello World" message using UART. 5. Write a C program to Design a Stopwatch using interrupts. 6. Write an Exception vector table in C 7. Write an Assembly Language Program for locking a Mutex. 8. Write a SVC handler in C. Use the wrapper code to extract the correct stack frame

starting location. The C handler can then use this to extractthe stacked PC

location and the stacked register values.

Lab Outcomes:

Learn advanced technologies in the fields of VLSI design along with the

fundamental concepts.

Understand and design advanced VLSI based system and conduct experiments,

analyze and interpret results.

Use modern Electronic Design Automation(EDA) tools, software and equipments

to evaluate and analyze the systems in VLSI and Embedded design environments.

Design of Embedded System applications based on advanced microcontrollers.

Text Books / References:

1. Neil H.E. Weste, David Harris, Ayan Banerjee, “CMOS VLSI Design – A circuits and

systems perspective”, Third edition, Pearson education, 2005. 2. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated

Circuits – A design perspective”, Second Edition, Pearson education, 2005.

3. Sung-Mo Kang, Yosuf Leblebici, “CMOS Digital Integrated Circuits – Analysis and

Design”, Third edition, TMH, 2003.

4. Douglas A. Pucknell, Kamran Eshraghian, “Basic VLSI Design”,PHI, 2005.

ADVANCED EMBEDDED SYSTEMS


L:P:T:S : 4:0:0:1 CIE Marks : 50


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To expose the students to the fundamentals of embedded system design. To design and develop embedded hardware and firmware. To impart knowledge on ARM Cortex-M3 to enable students to acquire more

awareness on real time embedded applications.

Module 1

Typical Embedded System: Core of the Embedded System, Memory, Sensors and

Actuators, Communication Interface, Embedded Firmware, Other System Component,

Characteristics and Quality Attributes of Embedded Systems. 7 Hrs

Module 2

Hardware Software Co-Design and Program Modeling: Fundamental Issues in Hardware

Software Co-Design, Computational Models in Embedded Design, Introduction to Unified

Modeling Language, Hardware Software Trade-offs.

Embedded Hardware, Firmware Design and Development: EDA Tools, How to Use EDA

Tool, Schematic Design – Place wire, Bus, port, junction, creating part numbers, Design

Rules check, Bill of materials, Netlist creation, PCB Layout Design – Building blocks,

Component placement, PCB track routing. Embedded Firmware Design Approaches and

Embedded Firmware Development Languages. 10 Hrs

Module 3

ARM- 32 bit Microcontroller family: Cortex M3 BasicsArchitecture of ARM Cortex-M3,

Operation modes and states, Registers, Special Registers, Data type, Memory format,

Instruction Set Summary. 8 Hrs

Module 4

ARM-32 bit Microcontroller family: Interrupt Controllers, Exceptions and Programming:

Nested Vector Interrupt Controller, Interrupt behavior of ARM Cortex-M3, Cortex M3

Programming, Exceptions Programming, Advanced ProgrammingFeatures and Memory

Protection unit. 10 Hrs

Module 5

The Embedded System Development Environment: The Integrated Development

Environment (IDE), Types of Files Generated on Cross compilation,

Disassembler/Decompiler, Simulators, Emulators and Debugging, Target Hardware

Debugging, Boundary Scan, Case studies. 9 Hrs

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1. Shibu K V, “Introduction to Embedded Systems”, Tata McGraw Hill Education

Private Limited, 2009

2. “Cortex M3 Technical Reference Manual ,” by ARM 3. James K Peckol, “Embedded Systems – A contemporary Design Tool”, John Weily,

2008. 4. Joseph Yiu, “The Definitive Guide to the ARM Cortex – M3, Newnes Elsevier, 2008

VLSI SUBSYSTEM DESIGN


L:P:T:S : 4:0:0:1 CIE Marks : 50



To understand the design aspects of Adders, Multipliers and other subsystem circuits.

To analyze the functionalities of CMOS Memories and special purpose

subsystems.

Module 1

Datapath subsystem-Adders: Introduction, Addition/Subtraction, One/Zero Detectors, Comparators, Counters, Boolean Logical Operations. 8 Hrs

Module 2

Datapath subsystems -Others: Coding, Shifters, Multiplication, Division, Parallel-prefix

Computations. 8 Hrs

Module 3

Array subsystems: SRAM, DRAM, ROM, Serial Access Memories, Content-addressable

Memory, Programmable Logic Arrays. 9 Hrs

Module 4

Special purpose subsystems:Finite State Machine Design, Control Logic Implementation,

PLA control implementation, ROM control implementation. 9 Hrs

Module 5

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Special purpose subsystems:Packaging, Power Distribution, I/O, Clock, Analog Circuits,

ADC, DAC, RF Circuits 10 Hrs


1. Neil H.E. Weste, David Harris, Ayan Banerjee, “CMOS VLSI Design – A circuits and systems perspective,” Third edition, Pearson education, 2005.

2. Neil H.E. Weste, Kamran Eshraghian, “Principles of CMOS VLSI Design – A systems perspective,” Second edition, Pearson education Asia, 2002.

3. Jan M. Rabaey, Anantha Chandrakasan, B Nikolic, “Digital Integrated Circuits: A Design Perspective,” Second Edition, Pearson Education, 2003.

4. Douglas A. Pucknell, Kamran Eshraghian, “Basic VLSI Design,”PHI, 2005.

VLSI PROCESS TECHNOLOGY


L:P:T:S : 4:0:0:1 CIE Marks : 50



To define the different processes that are used for the manufacturing of VLSI chips

To apply the knowledge of the processes for the chosen designs

Module 1

Crystal Growth and Wafer Preparation: Introduction, Electronic-Grade Silicon,

Czochralski Crystal Growing, Silicon Shaping, Process Considerations. 8 Hrs

Module 2

Epitaxy: Introduction, Vapour-Phase Epitaxy, Molecular Beam Epitaxy, Silicon on

Insulators, Epitaxial Evaluation. Lithography: Introduction, Optical Lithography, Electron Lithography, X-ray Lithography,

Ion Lithography.

Reactive Plasma Etching: Introduction, Plasma Properties, Feature-Size Control and

Anisotropic Etch Mechanisms, Other Properties of Etch Processes, Reactive Plasma-

Etching Techniques and Equipment, Specific Etch Processes. 10 Hrs

Module 3

Dielectric and Polysilicon Film Deposition: Introduction, Deposition Processes,

Polysilicon, Silicon Dioxide, Silicon Nitride, Plasma-Assisted Depositions, Other Materials.

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Ion Implantation: Introduction, Range Theory, Implantation Equipment, Annealing,

Shallow Junctions, High-Energy Implantation.

Metallization: Introduction, Metallization Applications, Metallization Choices, Physical

Vapor Deposition, Patterning, Metallization Problems, New Role of Metallization.

10 Hrs

Module 4

VLSI Process Integration: Introduction, Fundamental Considerations for IC Processing,

NMOS IC technology, CMOS IC Technology, MOS Memory IC Technology, Bipolar IC

Technology, IC Fabrication. 9 Hrs

Module 5

Packaging of VLSI Devices: Introduction, Package Types, Packaging Design

Considerations. 7 Hrs


1. S. M. Sze, “VLSI Technology,” McGraw-Hill, Second Edition.

2. S.K. Ghandhi, “VLSI Fabrication Principles,” John Wiley Inc., New York, 1994, 2nd

Edition.

SOFTWARE TECHNOLOGY FOR EMBEDDED SYSTEMS


L:P:T:S : 4:0:0:1 CIE Marks : 50



To understand the concepts of Embedded C programming

To apply Unified Modeling Language for Embedded System To develop Web architectural framework for Embedded Systems

Module 1

Programming embedded systems: Embedded Program – Role of Infinite loop –

Compiling, Linking and locating –downloading and debugging – Emulators and simulators

processor – External peripherals – Toper of memory – Memory testing – Flash Memory.

8 Hrs

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Module 2

C and assembly: Overview of Embedded C - Compilers and Optimization - Programming

and Assembly –Register usage conventions – typical use of addressing options –

instruction sequencing– procedure call and return – parameter passing – retrieving

parameters – everything in pass by value – temporary variables. 9 Hrs

Module 3

Embedded program and software development process: Program Elements – Queues –

Stack- List and ordered lists-Embedded programming in C++ - Inline Functions and Inline

Assembly - Portability Issues - Embedded Java-Software Development process: Analysis –

Design- implementation – Testing –Validation- Debugging - Software maintenance.

9 Hrs

Module 4

Unified modeling language: Object State Behaviour – UML State charts – Role of

Scenarios in the Definition of Behavior – Timing Diagrams – Sequence Diagrams – Event

Hierarchies – Types and Strategies of Operations – Architectural Design in UML

Concurrency Design –Representing Tasks – System Task Diagram – Concurrent State

Diagrams – Threads. Mechanistic Design – Simple Patterns. 9 Hrs

Module 5

Web architectural framework for embedded system: Basics – Client/server model-

Domain Names and IP address – Internet infrastructure and Routing – URL – TCP/IP

protocols - Embedded as Web Client - Embedded Web servers - HTML - Web security -

Case study : Web-based Home Automation system. 9 Hrs

Reference Books:

1. David E.Simon: “An Embedded Software Primer,” Pearson Education, 2003 2. Michael Barr, “Programming Embedded Systems in C and C++,” Oreilly, 2003 3. H.M. Deitel , P.J.Deitel, A.B. Golldberg “ Internet and World Wide Web – How to

Program,” Third Edition , Pearson Education , 2001. 4. Bruce Powel Douglas, “Real-Time UML, Second Edition: Developing Efficient

Object for Embedded Systems,” 2nd edition ,1999, Addison-Wesley 5. Daniel W.lewis “Fundamentals of Embedded Software where C and Assembly

meet,” PHI 2002. 6. Raj Kamal, “Embedded Systems- Architecture, Programming and Design,” Tata

McGraw Hill, 2006.

SoC Design


L:P:T:S : 4:0:0:1 CIE Marks : 50


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To define and discuss the motivation behind SoC design. To appraise the challenges of SoC design.

To classify embedded memories. To formulate overall SoC design flow.

Module 1

Motivation for SoC Design - Review of Moore’s law and CMOS scaling, benefits of

system-on-chip integration in terms of cost, power, and performance. Comparison on

System-on-Board, System-on-Chip, and System-in-Package. Typical goals in SoC design –

cost reduction, power reduction, design effort reduction, performance maximization.

Productivity gap issues and the ways to improve the gap – IP based design and design

reuse.

9 Hrs

Module 2

System On Chip Design Process: A canonical SoC Design, SoC Designflow, waterfall vs

spiral, top down vs bottom up, Specification requirement, Types of Specification, System

Design Process, System level design issues, Soft IP vs Hard IP, IP verification and

Integration, Hardware-Software co-design, Design for timing closure, Logic design issues,

Verification strategy, On chip buses and interfaces, Low Power, Hardware Accelerators in

Soc. 10 Hrs

Module 3

Embedded Memories –Cache memories, flash memories, embedded DRAM. Topics

related to cache memories. Cache coherence. MESI protocol and Directory-based coherence.

8 Hrs

Module 4

Interconnect architectures for SoC: Bus architecture and its limitations. Network on Chip

(NOC) topologies. Mesh-based NoC. Routing in an NoC. Packet switching and wormhole

routing. 8 Hrs

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Module 5

MPSoCs: What, Why, How MPSoCs, Techniques for designing MPSoCs, Performance and

flexibility for MPSoCs design.

Case Study: A Low Power Open Multimedia Application Platform for 3G Wireless.

9 Hrs

Reference Books: 1. Sudeep Pasricha and Nikil Dutt, “On-Chip Communication Architectures: System

on Chip Interconnect,”Morgan Kaufmann Publisher, 2008.

2. Rao R. Tummala, Madhavan Swaminathan, “Introduction to system on package

sop- Miniaturization of the Entire System,” McGraw-Hill, 2008. 3. James K. Peckol, “Embedded Systems: A Contemporary Design Tool,” Wiley

Student Edition.

4. Michael Keating, Pierre Bricaud, “Reuse Methodology Manual for System on Chip

designs,” Kluwer Accademic Publishers, 2nd

Edition, 2008.

5. Sung-Mo Kang, Yusuf Leblebici, “CMOS Digital Integrated Circuits,” Tata Mcgraw-

Hill, 3rd Edition.

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SECOND SEMESTER

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ANALOG INTEGRATED CIRCUIT DESIGN


L:P:T:S : 4:0:0:1 CIE Marks : 50



To expose the students to the fundamentals of Analog IC designing. To design amplifier circuits for various applications. To impart knowledge on IC designing to enable students to acquire more

awareness on real time Analog ICs and its applications.

Module1

Single stage Amplifier: CS stage with resistance load, diode connected load, current

source load, triode load, CS stage with source degeneration, source follower, common-

gate stage, cascode stage, choice of device models. 9 Hrs

Module2

Differential Amplifiers & Current Mirrors: Basic differential pair, common mode

response, Differential pair with MOS loads, Gilbert cell. Basic current mirrors, Cascode

current mirrors, active current mirrors.

9 Hrs

Module3

Operational Amplifiers: One Stage OP-Amp. Two Stage OP-Amp, Gain boosting, Common

Mode Feedback, Slew rate, Power Supply Rejection, Noise in Op Amps.

9 Hrs

Module 4

Oscillators and Phase Locked Loops: Ring Oscillators, LC Oscillators, VCO, Mathematical

Model of VCO. Simple PLL, Charge pump PLL, Non-ideal effects in PLL, Delay locked loops

and application.

8 Hrs

Module 5

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Bandgap Refernces and Switched capacitor Circuits: General Considerations, Supply

Independent biasing, PTAT Current Generation, Constant Gm Biasing, Sampling Switches,

Switched Capacitor Amplifiers. 9 Hrs


1) “Design of Analog CMOS Integrated Circuits”, BehzadRazavi, TMH, 2008. 2) “Analysis and Design of Analog IC’s”, P.R.Gray, Hurst, Lewis and R.G.Meyer, John

Wiley, 5th

Edition, 2001

3) “CMOS Analog Integrated Circuit Design”,AllenHolberg, Oxford University Press,

2002 4) “Analog Integrated Circuit Design”, Carusone, Johns and Martin, John Wiley,2

nd

Edition, 2012

REAL TIME OPERATING SYSTEMS


L:P:T:S : 4:1:0:0 CIE Marks : 75



To understand the fundamental concepts of real-time systems. To provide an understanding of the principles behind the structure and operation

of real-time operating systems. To impart knowledge and skills necessary to design and develop embedded

applications by means of real-time operating systems.

Module1

Introduction to Real-Time Embedded Systems: Brief history of Real Time Systems, A

brief history of Embedded Systems. Issues in real time computing, Structure of a real

time system, Task classes.

System Resources: Resource Analysis, Real-Time Service Utility, Scheduling Classes, The

Cyclic Executive, Scheduler Concepts, Preemptive Fixed Priority Scheduling Policies, Real-

Time OS, Thread Safe Reentrant Functions.

9 Hrs

Module2

Processing: Preemptive Fixed-Priority Policy, Feasibility, Rate Monotonic least upper

bound, Necessary and Sufficient feasibility, Deadline – Monotonic Policy, Dynamic

priority policies.

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I/O Resources: Worst-case Execution time, Intermediate I/O, Execution efficiency, I/O

Architecture.

Memory: Physical hierarchy, Capacity and allocation, Shared Memory, ECC Memory,

Flash file systems. 9 Hrs

Module3

Multi-resource Services: Blocking, Deadlock and livestock, Critical sections to protect

shared resources, priority inversion.

Soft Real-Time Services: Missed Deadlines, QoS, Alternatives to rate monotonic policy,

Mixed hard and soft real-time services.

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Embedded System Components: Firmware components, RTOS system software

mechanisms, Software application components.

9 Hrs

Module4

Debugging Components: Exceptions assert, Checking return codes, Single-step

debugging, kernel scheduler traces, Test access ports, Trace ports, Power-On Self Test

and diagnostics, External test equipment, Application-level debugging. Performance Tuning: Basic concepts of drill-down tuning, hardware – supported profiling

and tracing, Building performance monitoring into software, Path length, Efficiency, and

Call frequency, Fundamental optimizations. 9 Hrs

Module5

High availability and Reliability Design: Reliability and Availability, Similarities and

differences, Reliability, Reliable software, Available software, Design tradeoffs,

Hierarchical applications for Fail-safe design.

Features of µCOS-II Real Time Kernel.

8 Hrs

VLSI Design and Embedded System Lab-2

Lab Objectives:

To design and verify analog VLSI circuits using Cadence tool.

Hands on exercise based embedded RTOS. To introduce the concepts of embedded networking design.

PART-A

VLSI DESIGN

I. Analog design Analog Design Flow 1. Design an Inverterwith given specifications*, completing the design flow mentioned

below: a. Draw the schematicand verify the following

i) DC Analysis

ii) Transient Analysis b. Draw the Layoutand verify the DRC, ERC

c. Check for RCX

d. Extract RC and back annotate the same and verify the Design e. Verify & Optimize for Time, Power and Area to the given constraint***

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2. Design a Single Stage differential amplifier circuit with given specifications*,

completing the design flow mentioned below:

a. Draw the schematic and verify the following

i) DC Analysis ii) AC Analysis iii) Transient Analysis

b. Draw the Layout and verify the DRC, ERC c. Check for RCX d. Extract RC and back annotate the same and verify the Design. 3. Design an op-amp with given specification* using given differential amplifier Common source and Common Drain amplifier in library** And completing the design flow mentioned below: a. Draw the schematic and verify the following

i) DC Analysis ii). AC Analysis

iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for RCX d. Extract RC and back annotate the same and verify the Design.

4. Design a 4 bit R-2R based DAC for the given specification and completing the design flow mentioned using given op-amp in the library**. a. Draw the schematic and verify the following

i) DC Analysis ii) AC Analysis iii) Transient Analysis

b. Draw the Layout and verify the DRC, ERC

c. Check for RCX

d. Extract RC and back annotate the same and verify the Design. * Appropriate specification should be given. ** Applicable Library should be added & information should be given to the Designer. *** An appropriate constraint should be given.

PART-B

EMBEDDED SYSTEMS

I. Embedded Programming Concepts (RTOS) 1. Create ‘n’ number of child threads. Each thread prints the message “I’m in

thread number …” and sleeps for 50 ms and then quits. The main thread waits for

complete execution of all the child threads and then quits. Compile and execute in Linux.

2. Implement the multithread application satisfying the following: i) Two child threads are crated with normal priority. ii) Thread 1 receives and prints its priority and sleeps for 50ms and then quits.

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iii) Thread 2 prints the priority of the thread 1 and rises its priority to above

normal and retrieves the new priority of thread 1, prints it and then quits. iv) The main thread waits for the child thread to complete its job and quits.

3. Implement the usage of anonymous pipe with 512 bytes for data sharing between

parent and child processes using handle inheritance mechanism.

4. Test the program below using multithread application

i) The main thread creates a child thread with default stack size and name ‘Child Thread’. ii) The main thread sends user defined messages and the message ‘WM_QUIT’

randomly to the child thread.

iii) The child thread processes the message posted by the main thread and quits when it receives the ‘WM_QUIT’ message. iv) The main thread checks the termination of the child thread and quits when the child thread complete its execution. v) The main thread continues sending the random messages to the child thread till the ‘ WM_QUIT’ message is sent to child thread. vi) The messaging mechanism between the main thread and child thread is

synchronous. 5. Test the program application for creating an anonymous pipe with 512 bytes of size

and pass the ‘Read Handle’ of the pipe to a second process using memory mapped

object. The first process writes a message ‘ Hi from Pipe Server’. The 2nd process reads

the data written by the pipe server to the pipe and displays it on the console. Use event

object for indicating the availability of data on the pipe and mutex objects for

synchronizing the access in the pipe.

6. Create a POSIX based message queue for communicating between two tasks as per the requirements given below:-

i) Use a named message queue with name ‘My Queue’. ii) Create two tasks (Task1 & Task2) with stack size 4000 &priorities 99 &

100 respectively. iii) Task 1 creates the specified message queue as Read Write and reads the

message present, if any, from the message queue and prints it on the console.

iv) Task 2 open the message queue and posts the message ‘Hi fromTask2’. Handle all

possible error scenarios appropriately.

II. Embedded Networking Concepts

(Programming to be done using ARM Processor on IDE Environmentand download the

program on to an evaluation board)

7. Program to demonstrate I2C interface on IDE Environment.

26

i) Serial EEPROM ii) Real Time Clock

8. Demonstration of serial communication, between kit and PC using IDE environment. Use

debug terminal to trace the program. 9. Program to understand interfacing through RTOS application using IDE Environment such as:

i) Create two tasks for blinking of two different LEDs at different timings. ii) Sending messages to mailbox by one task and reading the message from mailboxby another task. iii) Basic Audio Processing.

Lab Outcomes:

Design and Verify the AC, DC, Transient analysis of Analog VLSI circuits.

Understand the concepts of RTOs (Linux/µcos-II operating system ) Implement the embedded networking concepts using ARM Processor.


5. “Real-Time Embedded Systems and Components”, Sam Siewert, Cengage Learning India Edition, 2007.

6. “Real Time Systems”, C.M. Krishna, Kang, G.Shin, , McGraw Hill, 1997. 7. “Introduction to Embedded Systems”,Shibu K V, Tata McGraw Hill Education Private

Limited, 2009. 8. “MicroC/OS-II The Real-Time Kernel”, Jean J. Labrosse, CMP Books, Second Edition. 9. “Programming for Embedded Systems”, Dreamtech Software Team, Jhon Wiley, India

Pvt. Ltd., 2008.

EMBEDDED NETWORKING


L:P:T:S : 4:0:0:0 CIE Marks : 50



To expose the students to the fundamentals of Embedded Networking.

To impart knowledge on Control Area Network. To design systems based on CAN.

27

Module1

Embedded Network Requirements: Embedded networking, code requirements,

Communication requirements, Introduction to CAN open, CAN open standard, Object

dictionary Electronic Data Sheets & Device, Configuration files, Service Data Objectives,

Network management CAN open messages, Device profile encoder.

9 Hrs

Module2

CAN open configuration: Evaluating system requirements choosing devices and tools, Configuring single devices, Overall network configuration, Network simulation, Network

Commissioning, Advanced features and testing. 9 Hrs

Module3

Controller Area Network-Underlying Technology: CAN Overview, Selecting a CAN

Controller, CAN development tools. 9 Hrs

Module4

Implementing CAN open: Communication layout and requirements, Comparison of implementation methods, Micro CAN open, CAN open source code, Conformance test

and Entire design life cycle. 9 Hrs

Module5

Implementation issues: Physical layer, Data types, Object dictionary, Communication

object identifiers, Emerging objects, Node states. 8 Hrs

Text Books/Refrences: 1. Glaf P.Feiffer, Andrew Ayre and Christian Keyold “Embedded Networking with CAN and

CAN open”. Embedded System Academy, 1st

edition 2008.

2. Mohammad Farsi, Manuel Bernardo Barbosa, “CANopen: Implementation Made Simple”, Research Studies Press,1999. 3.Konrad Etschberger, “Controller area network : basics, protocols, chips and

applications”, IXXAT Press,1st edition, 2001. 4. Wolfhard Lawrenz, “ CAN System Engineering: From Theory to Practical Applications”,

Springer, 1st edition,1997.

28

LOW POWER AND HIGH SPEED VLSI DESIGN


L:P:T:S : 4:0:0:1 CIE Marks : 50



Explain the basic design concepts for low power VLSI circuits in CMOS technology. Apply the knowledge in low-power VLSI circuit analysis and simulation Learn the basics of VLSI design for high speed processing.

Module1

Introduction to low power VLSI design: Need for low power VLSI chips, Sources of power

dissipation on Digital Integrated circuits. Emerging Low power approaches, Physics of

power dissipation in CMOS devices.

Device & Technology Impact on Low Power: Dynamic dissipation in CMOS, Transistor

sizing & gate oxide thickness, Impact of technology Scaling, Technology & Device

innovation. 8 Hrs

Module2

Power estimation, Simulation Power analysis: SPICE circuit simulators, gate level logic

simulation, capacitive power estimation, static state power, gate level capacitance

estimation, architecture level analysis, data correlation analysis in digital signal

processing systems, Monte Carlo simulation. 9 Hrs

Module3

Probabilistic power analysis: Random logic signals, probability & frequency, probabilistic

power analysis techniques, signal entropy.

low power design circuit level: Power consumption in circuits. Flip Flops & Latches

design, high capacitance nodes, low power digital cells library. Gate reorganization, signal

gating, logic encoding, state machine encoding, pre-computation logic. 9 Hrs

Module4

Introduction to high speed digital design: Frequency, time and distance issues in digital

VLSI design. Capacitance and inductance effects.

High speed propertiesof logic gates: Historical development, power, speed and

packaging 9 Hrs

29

Module5

Clock distribution: Timing margin and clock skew issues. Low-impedance drivers and

clock distribution lines, Controlling crosstalk, Delay adjustments, differential distribution,

clock signal duty cycle issues. Clock oscillators: Using canned clock oscillators, Clock jitter.

9 Hrs


1. Kaushik Roy, Sharat Prasad, “Low-Power CMOS VLSI Circuit Design” Wiley, 2000 2. Gary K. Yeap, “Practical Low Power Digital VLSI Design”, KAP, 2002 3. Rabaey, Pedram, “Low Power Design Methodologies” Kluwer Academic, 1997 4. Howard Johnson and Martin Graham, “High Speed Digital Design” A Handbook of Black

Magic, Prentice Hall PTR, 1993.

5. William S. Dally & John W. Poulton, “Digital Systems Engineering”, Cambridge University Press, 1998. 6. Kerry Bernstein & et. Al., “High Speed CMOS Design Styles”, Kluwer, 1999. 7. Masakazu Shoji, “High Speed Digital Circuits”, Addison Wesley Publishing Company, 1996. 8. Jan M, Rabaey, et al, “Digital Integrated Circuits”, A Design Perspective, Pearson, 2003.

VLSI TESTING AND VERIFICATION


L:P:T:S : 4:0:0:1 CIE Marks : 50



To provide the fundamentals on testing of VLSI systems.

To impart knowledge on Testing process and equipment. To appraise test generation for Combinational and Sequential circuits

To design testable sequential circuits.

30

Module1

Introduction to Testing: Testing Philosophy, Role of Testing, Digital and Analog VLSI

Testing, VLSI Technology Trends Affecting Testing. 8 hrs

Module2

VLSI Testing Process and Test Equipment: How to Test Chips? Automatic Test

Equipment, Electrical Parametric Testing. Faults in Digital Circuits: Failures and Faults,

Modeling of Faults, Temporary Faults. 9 hrs

Module3

Test Generation for Combinational Logic Circuits: Fault Diagnosis of Digital Circuits, Test

Generation Techniques for Combinational Circuits, Detection of Multiple Faults in

Combinational Logic Circuits.

Testable Combinational Logic Circuit Design: The Reed-Mullar Expansion Technique,

Three-Level OR-AND-OR Design, Automatic Synthesis of Testing Logic, Testable Design of

Multilevel Combinational Circuits, Synthesis of Random Pattern Testable Combinational

Circuits, Path Delay Fault Testable Combinational Logic Design, Testable PLA Design.

9 Hrs

Module4

Test Generation for Sequential Circuits: Testing of Sequential Circuits as Iterative

Combinational Circuits, State Table Verification, Test Generation Based on Circuit

Structure, Functional Fault Models, Test Generation Based on Functional Fault Models.

Design of Testable Sequential Circuits: Controllability and Observability, Ad Hoc Design

Rules for Improving Testability, Design of Diagnosable Sequential Circuits, The Scan-Path

Technique for Testable Sequential Circuit Design, Level-Sensitive Scan Design, Random

Access Scan Technique, Partial Scan, Testable Sequential Circuit Design Using Non scan

Techniques, Cross Check, Boundary Scan. 9 Hrs

Module5

Built-In Self Test: Test Pattern Generation for BIST, Output Response Analysis, Circular

BIST, BIST Architectures. Testable Memory Design: RAM Fault Models, Test Algorithms

for RAMs, Detection of Pattern Sensitive Faults, BIST Techniques for Ram Chips, Test

Generation and BIST for Embedded RAMs. 9 Hrs

Text Books/References

1. Sridhar .T, “Designing Embedded Communication Software” CMP Books, 2003. 2. Comer.D, ”Computer networks and Internet”, Third Edition, Prentice Hall, 2001.5.

Joseph Yiu

31

EMBEDDED COMMUNICATION SOFTWARE DESIGN


L:P:T:S : 4:0:0:1 CIE Marks : 50



To provide the fundamentals of embedded communication systems To impart knowledge on

i. Device Management software. ii. Multi board communication software design

Module1

OSI Reference Model: Communication Devices – Communication Echo System – Design

Consideration – Host Based Communication – Embedded Communication System – OS Vs

RTOS. 9 Hrs

Module2

Software Partitioning: Limitation of strict Layering – Tasks &Module s – Module s and

Task Decomposition – Layer2 Switch – Layer3 Switch / Routers – Protocol

Implementation – Management Types – Debugging Protocols.

9 Hrs

Module3

Tables & other Data Structures: Partitioning of Structures and Tables – Implementation –

Speeding Up access – TableResizing – Table access routines – Buffer and Timer

Management – Third Party Protocol Libraries. 9 Hrs

Module4

Management Software: Device Management – Management Schemes – Router

Management – Management of Sub System Architecture – Device to manage

configuration – System Start up and configuration. 9 Hrs

32

Module5

Multi Board Communication Software Design: Multi Board Architecture – Single control

Card and Multiple line Card Architecture –Interface for Multi Board software – Failures

and Fault – Tolerance in Multi Board Systems – Hardware independent development –

Using a COTS Board – Development Environment – Test Tools. 8 Hrs

Text Books/References

1. Sridhar .T, “Designing Embedded Communication Software” CMP Books, 2003. 2. Comer.D, ”Computer networks and Internet”, Third Edition, Prentice Hall, 2001.5.

Joseph Yiu

WIRELESS SENSOR NETWORKS


L: P: T: S : 4:0:0:1 CIE Marks : 50



To understand the needs of Wireless Sensor Networks in Communication

Systems.

To expose the students into the signal processing approach to Wireless Sensor

Networks.

To expose the students into the information theoretic approach to Wireless

Sensor Networks.

Module1

Information-theoretic Bounds on Sensor Network Performance: Introduction, Sensor

Network Models - The Linear Gaussian Sensor Network, Digital Architectures -

Distributed Source Coding, Distributed Channel Coding, End-to-end Performance of

Digital Architectures, The Price of Digital Architectures, Bounds on General Architectures.

9 Hrs

33

Module2

In-Network Information Processing in Wireless Sensor Networks and their Sensing

Capacity:Introduction, Communication Complexity Model, Computing Functions over

Wireless Networks: Spatial Reuse and Block Computation, Wireless Networks with Noisy

Communications: Reliable Computation in a Collocated Broadcast Network - The Sum of

the Parity of the Measurements, Threshold Functions, Towards an Information Theoretic

Formulation, Large-Scale Detection Applications, Sensor Network as an Encoder,

Information Theory Context, Sensing Capacity of Sensor Networks, Extensions to Other

Sensor Network Models. 9 Hrs

Module3

Detection in Sensor Networks: Centralized Detection, The Classical Decentralized

Detection Framework, Decentralized Detection in Wireless Sensor Networks, Detection

under Capacity Constraint, Wireless Channel Considerations, Correlated Observations,

Attenuation and Fading, New Paradigms, Extensions and Generalizations, Distributed

Estimation under Bandwidth and Energy Constraints -Distributed Quantization-

Dimensionality Reduction for Distributed Estimation, Distortion-Rate Analysis. 9 Hrs

Module4

Distributed Learning, Graphical Models and Fusion in Wireless Sensor Networks:

Introduction, Classical Learning, Distributed Learning in Wireless Sensor Networks,

Distributed Learning in WSNs with a Fusion Center, Distributed Learning in Ad-hoc WSNs

with In-network Processing, Graphical Models, From Sensor Network Fusion to Graphical

Models, Message Censoring, Approximation, and Impact on Fusion, The Effects of

Message Approximation, Optimizing the Use of Constrained Resources in Network

Fusion.

9 Hrs

Module5

Randomized Cooperative Transmission in Large-Scale in WSNs and Application

Dependent Shortest Path Routing in Ad-Hoc Sensor Networks: Introduction, Transmit

Cooperation in Sensor Networks, Randomized Distributed Cooperative Schemes,

Performance of Randomized Cooperative Codes, Analysis of Cooperative Large-scale

Networks Utilizing Randomized Cooperative Codes, Major Classifications, Fundamental

SPR, SPR for Mobile Wireless Networks, SPR for Ad-Hoc Sensor Networks. 8 Hrs

34

Text book: 1. Ananthram Swami, Qing Zhao, Yao-Win Hong, and, Lang Tong (Editors), “Wireless

Sensor Networks – Signal Processing and Communications Perspectives,” 1st

Edition, Wiley India Private Limited, New Delhi, India, 2014.

References: 1. W. Dargie, and, C. Poellabauer, “Wireless Sensor Networks: Theory and Practice,”

1st

Edition, Wiley India Private Limited, New Delhi, India, 2012. 2. K. Sohraby, D. Minoli, and, T. Znati, “Wireless Sensor Networks: Technology,

Protocols, and Applications,” 1st


3. J. Zheng, A. Jamalipour, “Wireless Sensor Networks: A Networking Perspective,”

1st

Edition, Wiley India Private Limited, New Delhi, India, 2012. 4. H. Karl, and, A. Willig, “Protocols and Architectures for Wireless Sensor

Networks,” 1st


AD-HOC WIRELESS NETWORKS

Course Code : 15NHG255 Credits : 05

L:P:T:S : 4:0:0:1 CIE Marks : 50



To expose the students to the fundamentals of ad-hoc wireless network. To give

an insight of various Mac Protocols.

To understand the Route set up and maintenance through varied Routing

Protocols.

To understand Transport and Security Solutions for ad-hoc wireless networks. To introduce energy management for ad-hoc networks. To understand the concept of sensor networks.

Module1

Ad hoc Wireless Networks: Introduction, Issues in Ad hoc Wireless Networks, Ad hoc

Wireless Internet.

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MAC Protocols for Ad hoc Wireless Networks: Introduction, Issues in Designing a MAC

Protocol, Design Goals of MAC Protocols, Classification of MAC protocols, Contention-

Based Protocols, Contention-Based Protocols with Reservation Mechanisms, Contention-

Based Protocols with Scheduling Mechanisms, MAC Protocols that Use Directional

Antennas. 10 Hrs

Module2

Routing Protocols for Ad Hoc Wireless Networks: Introduction, Issues in Designing a

Routing Protocol for Ad hoc Wireless Networks; Classification of Routing Protocols; Table

Driven Routing Protocols; On-Demand Routing Protocols, Hybrid Routing Protocols,

Hierarchical Routing Protocols and Power-Aware Routing Protocols 9 Hrs

Module3

Transport Layer Protocols for Ad hoc Networks: Introduction, Issues in designing a

Transport Layer Protocol; Design Goals of a Transport Layer Protocol; Classification of

Transport Layer Solutions; TCP over Transport Layer Solutions. Security Protocols for Ad hoc Networks: Issues and Challenges in Security Provisioning,

Network Security Attacks, Key management and secure routing adhoc wireless networks.

9 hrs

Module4

Energy Management in Ad hoc Wireless Networks Introduction, Need for Energy Management in Adhoc Wireless Networks, Classification of Energy Management Schemes, Battery Management Schemes, Transmission Management Schemes, System

Power ManagementSchemes. 8 hrs

Module5

Wireless Sensor Networks:

Introduction,

Sensor

Network

Architecture,

Data

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Dissemination, Data Gathering, MAC Protocols for Sensor Networks, Location Discovery,

Quality of a Sensor Network, Evolving Standards, Other Issues. 8 Hrs


1. C. Siva Ram Murthy & B. S. Manoj: Ad hoc Wireless Networks, 2nd Edition, PearsonEducation, 2011.

2. Ozan K. Tonguz and Gianguigi Ferrari: Ad hoc Wireless Networks, John Wiley, 2007. 3. Ad- Hoc Mobile Wireless Networks: Protocols & Systems, C.K. Toh ,1 ed. Pearson

Education. 4. Wireless Sensor Networks - C. S. Raghavendra, Krishna M. Sivalingam, 2004, Springer. 5. Wireless Ad- hoc and Sensor Networks: Protocols, Performance and Control –

Jagannathan Sarangapani, CRC Press.

37

Basic MOS Device Physics: General considerations, MOS device models.

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