DeleonibusPresentation

8/3/2019 DeleonibusPresentation

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INSTITUTE FOR ENERGY EFFICIENCY

Santa Barbara, California, December 2, 2011

More MOORE and MORE THAN MOORE MEETING FOR 3D

S.Deleonibus,CEA-LETI, MINATEC Campus,

17 rue des Martyrs , 38054 Grenoble Cedex 09 France.

Tel : 33 (0)4 38 78 59 73 ; Fax: 33 (0)4 38 78 51 83; email: [email protected]


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CEA. All rights reserved

S.Deleonibus CEA-LETI December 2011 | 2

CEA LETI organization

15,000 Employees

3 billion Budget

15,000 Employees

3 billion Budget

French Nuclear Agency

TechnologicalResearch

FundamentalResearch

ElectronuclearEnergy Res.

Defense

3,200 Researchers

3,200 Researchers

New technology forEnergy &

Nanomaterials

Software orientedsystem

Micro NanoTechnology &

integration in System

1,600 Researchers

1,600 Researchers

* Grenoble

* Grenoble

* Saclay


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LETI: Mission and Focus

Basic ResearchPublications

Applied Research

Patents

Pilot LinePrototypes

Mass ProductionProducts

A single mission :

Create innovation

& transfer it to industry

A clear focus :-nanotechnologies, with critical mass in Si

Advanced devices for new applications


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LETI in a few numbers - 2010

Microelectronics

Microsystems

Biology & Health

Photonics

Wireless & Smart devices

Energy & Environment

200 and 300mm Si capabities8,000 m clean roomsContinuous operation

1 600 researchers1 000 permanent LETI staff

300 M budget> 73% from contract~ 40 M CapEx

350 new patents in 2010Portfolio > 1,500 patents32 start-ups


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Since 2005: A complete set of research platforms

interacting daily with R & D platforms worldwide(ST Crolles, IBM Albany, )

CEA LETI (1600 CEA researchers)collaborating

in MINATEC campus (>4000 researchers)

300mmCMOS Integration

& adv. modules

200mmCMOS new concepts

& Beyond CMOS

More Than Moore200mm

NanoscaleCharacterization

Design

MicroTechsfor bio

Education

Incubation

AdvancedResearch

100-200mm


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Outline

Introduction : Trends and Hot Topics in Nanoelectronics

Nanoelectronics scaling and use of the 3rddimension to continue Moores law.

Interfacing the Multiphysics World (More Than Moore)thanks to functional diversification

Building new systems and their packagingwith a 3D tool box at a wafer level.

Conclusions


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Semiconductor Market applications successive waves

Source : Semico Research Corp. May 2004 IPI Report

Quality of life, Social, Environment, Health, Energy,associated to ICT


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Currently, 3 % of the world-wide energy is consumed by the ICT

infrastructure

which causes about 2 % of the world-wide CO2 emissions

comparable to the world-wide CO2 emissions by airplanes or of the world-wide CO2 emissions by cars

ICT: 10% of electrical energy in industrialized nations 900 Bill.. kWh / year = Central and South Americas

The transmitted data volume increases approximately by a factor of 10

every 5 years

Source: TU Dresden

Ecological Footprint of ICTsreported by Intergovernmental Panel Climate Change(IPCC)

For ICTs, keep in mind:P = P

stat+ P

dynP

stat= V

ddxI

offand P

dyn=CV

dd

2 f


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Scaling: a success storythanks to innovation

1,00E+00

1,00E+01

1,00E+02

1,00E+03

1,00E+04

1,00E+05

1,00E+06

1,00E+07

1,00E+08

1,00E+09

1,00E+10

1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018

Date

Numberoftra

nsistorsperchip

100m

10m

1m

0,10m

10 nmCriticalDimensio

n

4004

8080

8086 80286

i386

i486Pentium

Pentium II

Pentium IIIPentium IV

Itanium

1k4k

16k

64k

256k

1M4M

16M

64M128M

256M512M

1G2G

4G

micro

proc

essors

dyna

mic m

emories(D

RAM)

contacts plugs (3 lev met)

vias plugs ,CMP(4 lev met)

FSG(6 lev met)

damascene(5 lev met)

Cu (7 lev met)

Cu+H(M)SQ (9 lev met)

polymers

+ALD (10 lev met)

ULK(11 lev met)

poly gate

polycide

1 billionOffice

PC

MainFrame

C.T.V.

VCRDefense

HomePC

PortableInternet

Convergence

10 millions

STI, salicide

DigitalCamera

HiK +metal gate

1,00E+00

1,00E+01

1,00E+02

1,00E+03

1,00E+04

1,00E+05

1,00E+06

1,00E+07

1,00E+08

1,00E+09

1,00E+10

1958 1963 1968 1973 1978 1983 1988 1993 1998 2003 2008 2013 2018

Date

Numberoftra

nsistorsperchip

100m

10m

1m

0,10m

10 nmCriticalDimensio

n

4004

8080

8086 80286

i386

i486Pentium

Pentium II

Pentium IIIPentium IV

Itanium

1k4k

16k

64k

256k

1M4M

16M

64M128M

256M512M

1G2G

4G

micro

proc

essors

dyna

mic m

emories(D

RAM)

contacts plugs (3 lev met)

vias plugs ,CMP(4 lev met)

FSG(6 lev met)

damascene(5 lev met)

Cu (7 lev met)

Cu+H(M)SQ (9 lev met)

polymers

+ALD (10 lev met)

ULK(11 lev met)

poly gate

polycide

1 billionOffice

PC

MainFrame

C.T.V.

VCRDefense

HomePC

PortableInternet

Convergence

10 millions

STI, salicide

DigitalCamera

HiK +metal gate

Moores law: 2Xdevices/year

Electronic Device Architectures for the Nano-CMOS Era

From Ultimate CMOS Scaling to Beyond CMOS DevicesEditor: S.Deleonibus, Pan Stanford Publishing, Oct 2008


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Three major product families(ITRS aware of CMOS scaling limits)

High Performance (HP) t=CV/I

Connection to power network

Low Operating Power (LOP) Intermittent Nomadic Function

Low Stand-by Power (LSTP) Pstat= VddxIoff Permanent Nomadic Function

Nomadic consumer and professional products:largest market share continuously increasing

Pdyn=CVdd2f

Ptot=Pstat+ Pdyn


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More, More than, Beyond Moore

Tomorrows top added value markets

ITRS 2009 & 2011

High growth with More than Moore technologies:they require expertise in all technical domains and in-

depth knowledge of the targeted markets


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EUV ( = 13.5nm)

60% reflectivity for several hundreds of Si / Mo stacksw roughness precision < 3

Placement of mirror and mask

Photoresist

from S.A. Campbell, The Science and Engineering of Microelectronic

Fabrication, Oxford University Press 2001 Engineering Test Stand (VNL/EUV-LLC)

>100 M$100Wph !!


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System made of 13,000 electron

beams working in parallel (MAPPER)(1)

Key numbers 22nm node:

HVM pre-alpha

#beams and data channels 13,000 110

Spotsize: 25 nm 35 nm

Beam current: 13 nA 0.3 nA

Datarate/channel 3.5 Gbs 20 MHz

Acceleration voltage 5 kV 5 kV

Nominal dose 30 C/cm2 30 C/cm2

Throughput @ nominal dose 10 wph 0.002 wph

Pixel size @ nominal dose 3.5nm 2.25 nm

Wafer movement Scanning Static

Electron source

Collimator lens

Aperture array

Beam Blanker array

Beam Deflector arrayProjection lens array

Condensor lens array

Beam Stop array

Electron source

Collimator lens

Aperture array

Beam Blanker array

Beam Deflector arrayProjection lens array

Condensor lens array

Beam Stop array


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1mMAPPER single column tool. Upgrade to

13,000 beam for 10WPH

Interface totrack1m

MAPPER single column tool. Upgrade to13,000 beam for 10WPH

Interface totrack

Interface totrackCluster 100WPH

System made of 13,000 electron

beams working in parallel (MAPPER)(2)


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Hot Topics in MOSFET technology

Introduction of HiK and metal gate allows continued scaling and relaxesSiO2 gate leakage current related issues

- Ig added to SCE, DIBL, subthreshold leakage(LETI IEDM 2002, Intel IEDM 2005)

Statistical dopant variability

- number of dopants in the active area decreases with scaling

- random distribution of channel dopants

Poissons law. Standard deviation:

S.Deleonibus et al. ESSDERC 1999

Major interest for Low

Doped channels

21

=

Volume

Ndoping

0.01

0.1

1

10

100

1000

104

0.01 0.1 1

N/N

Nombred'impurets

Lg (m)

Statistical fluctuations of

threshold voltage: 150 mV decay

for VT=200mV( Lg=25nm) !!


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Outline


Nanoelectronics scaling and use of the 3rddimension to continue Moores law.



Conclusions


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32nm Low Power FDSOI Undoped channels

C.Fenouillet Beranger et al., IEDM 2007, VLSI Symp 2010

V.Barral et al., IEDM2007

VDD=1V Ioff=6pA/m

0.248m2 SNM (1.2V)=140mV0.179m2 SNM (1.2V)=230mV

6T SRAM

10 nm BOx8 nm TSi 10 nm BOx8 nm TSi

Range = 4 !

0000

+5+5+5+5

----5555

1 917

25

33

41

49

57

65

73

81

89

97

105

113

121

129

137

Wafer #

-10

-5

0

5

10

SOIThickness

De

viationtotarget()

SOI Thickness

Max

Mean

Min

XUT+/- 5 - SOI thickness deviation

1 917

25

33

41

49

57

65

73

81

89

97

105

113

121

129

137

Wafer #

-10

-5

0

5

10

SOIThickness

De

viationtotarget()

SOI Thickness

Max

Mean

Min

XUT+/- 5 - SOI thickness deviation

300mm wafers


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0.5

1

1.5

2

2.5

3

10 20 30 40 50 60

AVt

(mV

.um

)

Gate length L (nm)

FinFETs

Planar FDSOI

Wfin

=10nm

UTBSOILETI

square : Vd=50mV

circle : Vd=1V

Wfin

=20nm

Wfin

=15nmW

fin

=20nm

[14]

[13]

[1]

[12]

[13]

[15]

[15]

[16]

0

20

40

60

80

100

120

-105 -8

7-69

-51

-33

-15 0 15 33 51 69 87 10

5

Vt=34.5mV

Vt=24.5mV

AVt=0.95mV.mCoun

t

Vt shift Vt (mV)

0

20

40

60

80

100

120

-105 -8

7-69

-51

-33

-15 0 15 33 51 69 87 10

5

Vt=34.5mV

Vt=24.5mV

AVt=0.95mV.mCoun

t

Vt shift Vt (mV)

Best trade-off between VT variations and gate length scalingcompared to bulk MOSFETs and FinFETs

L=25nm

W=60nm

(Vt=Vt/2 to compare measurements on pairsand on arrays of transistors in the literature)

O.WeberO.WeberO.WeberO.Weber et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008et al., IEDM 2008WL

AVtVt =

Record-high VT matching performance

FDSOI Undoped channels vs.FinFET


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Multi VT solutions for SOC design

UTBOX + Back bias ; Gate stack engineering

0

0,1

0,2

0,3

0,4

0,50,6

0,7

0,8

0,9

0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9

VTP (V)

VTN(V)

HfO2/TiN

HfO2/Al203/TiN

HfO2/Al203+/TiN

HfSiON/TiN5

HfSiON/Al203+/TiN

HfSiON/TaAlN/TaN

HfSiON/TaN/TaAlN

HfSiON/TiN10

HfSiON/TiN

VT tuning by gate stack engineering

F.Andrieu et al. , VLSI 2010 Honolulu

O.Faynot et al., IEDM 2010 San Francisco, invited talk

BOX = 10nm and VBB/ Ground Plane

N and PMOS: VT modulation of200mV


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Merits of FDSOI

Reachable Scaling rules

(TSi, TBOx)

Delay vs. Power x Delay

22% improvement/bulk (20nm)

O.Faynot et al, IEDM 2010, invited talk

L.Clavelier et al, IEDM 2010, invited talk


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Thin Films Devices

Relaxing optimizationscaling rule

by architecture

TSi= Lg

TSi= 1 to 2 Lg

PlanarDouble-gate

Planar or Finfet

Trigate/nanowire

tsource

Gate

tsource

Gate

Gate

sourcet

Gate

SourceL

w

ThinSOI

Bulk or thick SOI

TSi= Lg

w

TSi=2.5nm

Strain global & local

Lg=10nm

Barral et al.

IEDM2007

Andrieu et al

VLSI2006

Bernard et al

VLSI 2008

Dupr et al.

IEDM 2008

Ernst et al.

IEDM 2008

Jahan et al.

VLSI2005

Vinet et al.EDL 2005

4.8 nm

3.4 nm

4.8 nm

3.4 nm


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Si/Si0.8Ge0.2superlatticeepitaxy on SOI

Anisotropicetchingof these layers

Isotropicetchingof SiGe or Si

HfO2 (3nm)TiN (10nm)Poly-Si (200nm)

Gate depositions

S/D implantationSpacer formationActivation annealSalicidation

BOX

SiSiGe

SiSiGe

SiSiGeSiN

BOX BOX BOX

Gate

BOX

Gate

Gate etching

StandardBack-End

of-LineProcesses

500 nm

Source Drain

Gate

Top view of our device

Nanowires

Stacked Multichannels and MultiNanowires

Top-Down approach: device fabrication


24/49



0

1

2

3

4

5

6

0 1 2Layout width (a.u.)

Con

du

ctance

(a

.u.)

1 nanowire

planar

0

1

2

3

4

5

6


Con

du

ctance

(a

.u.)

1 nanowire

3 nanowires

0

1

2

3

4

5

6


Conduc

tance

(a

.u.)

Finfet

Tunable width

See for details:

T. Ernst et al, IEDM06,08 SSDM07, ICIDT08

E. Bernard et al. VLSI08, ESSDER07C. Dupr et al, IEEE SOI Conference 07

Layout width1 2

vvv

0

1

2

3

4

5

6


Con

du

ctance

(a

.u.) 3 multi

- channels(MC)

WW

pitch

Design flexibility to tunethe conductance


Top-Down approach


25/49




Top-Down approach

LETI: Dupr et al. IEDM 2008, San Francisco(CA)Ernst et al., Invited talk IEDM 2008, San Francisco(CA)

Bernard et al, VLSI Symposium 2008 HonoluluK.Tachi et al., IEDM 2010, San Francisco

LETI top down approach forLow Power and High performance

10-12

10-10

10-8

10-6

10-4

10-2

-2 -1.5 -1 -0.5 0 0.5 1 1.5 2

DrainCu

rrentID(A/m)

Gate Voltage VG

(V)

VD=1.2VV

D=1.2V

NWFET

P N

VD=50mV

ION

=6.5mA/m

IOFF

=27nA/m

SS=68mV/decDIBL=15mV/VV

T=0.5V

C.E.T.=1.8nm

VD=50mV

ION

=3.3mA/m

IOFF

=0.5nA/m

SS=65mV/decDIBL=7mV/VV

T=-0.62V

-CV/I outperforms Planar in loaded environment

-Improved voltage gain (8GHz) wrt Planar

-Gate separation possible

-Transport properties in small nanowires


26/49



Pervasion of Nanowire technology

20nm

Poly SiSiO2Si3N4SiO2

3D NANDFlash Memories

Q=870 resonatorGauge width = 80 nm

15 nm oscillator

Zeptogram mass resolution

Mass detection

60

70

80

90

100

110

120

130

0 2000 4000 6000 8000 10000 12000

Time (s)

Conductance(nS)

pH 7

pH 4pH 5

pH 6

pH 3

pH

60

70

80

90

100

110

120

130

0 2000 4000 6000 8000 10000 12000

Time (s)

Conductance(nS)

pH 7

pH 4pH 5

pH 6

pH 3

pH

Metaln-doped Si Hole ElectronPassivation

Buffer solution

at pH


27/49



Tunnel FET Operation principle

N & P operation modes

A single TFET device can operate

either in n or p channel mode

N mode : VSD>0 & VGD>0 P mode: VDS


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SOI TFETs co-integrated with CMOSFETs

L=100nm; T=300K

P mode: VDS0

Experimental demonstrationof Tunnel FET operations:

F.Mayer et al., IEDM 2008,

C.LeRoyer et al., ULIS 2009

SOI TFETw. LDDn

BOx

S D

GP modeN mode

LDDHDD

50nm

NiSi NiS

NiSi

Sour

HDD

Gate

tSi

TiNHfO2

Poly

LG

1st spacer

2nd spacer

NiSi

SiN protection lay

Drain

LDDHDD

50nm

NiSi NiS

NiSi

Sour

HDD

Gate

tSi

TiNHfO2

Poly

LG

1st spacer

2nd spacer

NiSi

SiN protection lay

Drain


29/49



TFET for Ultra Low Power outperforms CMOSOffset/drain reduces Ioff(ambipolar current)

LETI: Mayer et al, IEDM 2008

Intel: U.E. Avci et al, VLSI Tech Symp 2011

EPFL: K. Boucart & A. M. Ionescu, ESSDERC 2006TUM: M. Schlosser et al. IEEE TED, Jan. 2009

Multigate improves Ion


30/49



CoCo--Integrating Heterogeneous orientation or materialsIntegrating Heterogeneous orientation or materials3D sequential process3D sequential process

(100)

FirstFirst heterogeneousheterogeneous orientation in 3D Siorientation in 3D Si sequentialsequential integrationintegration

EnabledEnabled by use of waferby use of wafer bondingbonding byby keepingkeeping lowlow thermal budgetthermal budget

(110)

0.0 0.2 0.4 0.6 0.8 1.00

50

100pMOS

Reference TiN/ HfO2/ Si (100)

TiN/HfO2/Si(110)

eff

,hole(cm

2/V.s)

Eeff (MV/cm)

P.Batude et al., Best student Paper Award, IEDM 2009

Ge

-4T SRAM

- cold end process(bonding).

Opportunities for other SC(Ge,III-V,...)

- improved layout (40% area SRAM cell)-dynamically controlled VT:

improved RNM and SNM


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Tsi 10nm

Tsi ~10 nm

LG~50 nm

THFO2 2.5 nmTiN

LG~50 nm

Sequential 3D: towards nanoscale devices

First demonstration of 3D sequential structuredown to LG 50 nm

P.Batude et al, 2011 VLSI Tech Symp

P.Batude et al., IEDM 2011, Invited talk


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-2 -1 0 10.00

0.01

0.02

0.03Top FET

Bottom FET

EOT= 1.45nm

EOT= 1.15nm

Ca

pacitance(F

/m

2)

Gate Voltage VG(V)

BOX

HfOHfO22= 2.5nm= 2.5nm

Specific interest of low temperature process

The low temp. process (600C) leads to a reduced EOTExplained by a reduction of interfacial oxide growthP.Batude et al, 2011 VLSI Tech Symp

Sequential 3D: Potential and Demonstrated ApplicationsSequential 3D: Potential and Demonstrated Applications


33/49



~ 1 node gain withsame design rules for

Front end levels

top

GeOI pMOS

2m

nMOSGate

nMOS

Source

pMOS

Gate

pMOSSource

bottom

SOI nMOS

top

GeOI pMOS

2m

nMOSGate

nMOS

Source

pMOS

Gate

pMOSSource

bottom

SOI nMOS

Y-H. Son et al, VLSI 07, Jung et al, IEDM 2006

Nanoelectronics &Photonicsapplications withSi-Ge Co-integration

SRAM on top SOIlogic, I/Os, analogon bottom bulk

SRAMs FLASH

Sequential 3D: Potential and Demonstrated ApplicationsSequential 3D: Potential and Demonstrated Applications

High density logic applicationsHigh density logic applications

Highly miniaturizedHighly miniaturized

CMOS imagers pixelsCMOS imagers pixels

Heterogeneous integrationHeterogeneous integration 3D memories3D memories

P. Coudrain et al, IEDM 08,

P. Batude et al,VLSI09P.Batude et al., IEDM 2009, Best Student Paper Award

3D Xb M t k d L i t d NV


34/49



Logic + Stacked NVM:

High bandwith,Reduced Power consumption,

Reconfigurability

ex: 32 nm node : > 1TB/s per 1mm2

Resistive switchesToshiba, Stanford Univ.: K.Abe et al, ICICDT 2008

3D-Xbar Memory stacked on Logic: towards NV

Logic

proven in 2D with

Magnetic Tunnel Junctions,

FeRAM Tohoku Univ., Hitachi:S.Matsunaga et al., Appl.Phys. Express(2008);

ROHM

Advanced Devices and Systems


35/49



MoreMoore

MorethanMoore

Dual channel

xsSOI(N)/ Ge(P)

Advanced Devices and Systems

Future Vision

UTBOX

22nm 16nm

sSOI

2010 20132009 2014 2016

FDSOI

11nm

Std SOI

HP options

Nanowire

3D Nanowires

3D stacked devices3D

Logic

2012 2015

3D

III-V/Ge Heat sink C

Memory storing(SRAM, NVM) -

ZDRAM

3D stacked Mixed functions:

NV Logic +sensors/polymers

X bar

3D Sensing/Actuation

Bio, Mechanical &Chemical

(functionalization,

NEMS, Single

electronics, RF,

opto, )

Diversified Logic(association to Memory,Passives, Sensors,)

Beyond CMOS(e-wavesconfinement, Spinelectronics)

Si

FeFe

Si

FeFe

Low stress,HiD

Carbone

lec

tron

ics

(CN

T,G

rap

hene,

Dia

mon

d)

Transfer to Industry Development

< 11nm

Opportunities for other materials on Silicon


36/49



2.1x1060.721.4212.9554008500GaAs

4

2,7

5,0@77K

0.6

0,60

0,86

vsat(107cm/s)

1x1012cm-2

(1x1015)

10-27

2x1016

6X1011

2x1013

2x1010

ni(cm-3)(m*em*h/m

2)T3/2

exp(-Eg/2kT)

0.1716.91.885077000InSb

Semi-metal

5.71000104-105104-105Graphene

(CNT) sp2

5.7

13.9

16

11.9

Rel. K

5.47

0.74

0.66

1.12

Eg(eV)

200018002200C-Diamondsp3

530012 000InGa0.47As0.53

59.919003900Ge

1415001400Si

sth (W/m/K)p(cm2V-1s-1)

n(cm2V-1s-1)

Material

2.1x1060.721.4212.9554008500GaAs

4

2,7

5,0@77K

0.6

0,60

0,86

vsat(107cm/s)

1x1012cm-2

(1x1015)

10-27

2x1016

6X1011

2x1013

2x1010

ni(cm-3)(m*em*h/m

2)T3/2

exp(-Eg/2kT)

0.1716.91.885077000InSb

Semi-metal

5.71000104-105104-105Graphene

(CNT) sp2

5.7

13.9

16

11.9

Rel. K

5.47

0.74

0.66

1.12

Eg(eV)

200018002200C-Diamondsp3

530012 000InGa0.47As0.53

59.919003900Ge

1415001400Si

sth (W/m/K)p(cm2V-1s-1)

n(cm2V-1s-1)

Material

Highest n but Worst n/p!!

Well established high quality material(>40yrs experience) Oxidizable !

Silicon compatibleAvailable in all fabsGaAs lattice constant matching

Opto/Power RF applicationsGe compatibleHP N channel

Highest th

Most compact logic,

Interconnect

High short channel

effect immunity

Passive layer combine

w BOx

(thermal shunt)

Poor short channel

effect immunity

BTBT

TFET/W

Opportunities for other materials on SiliconElectronic Device Architectures for the Nano-CMOS Era

From Ultimate CMOS Scaling to Beyond CMOS Devices

Editor: S.Deleonibus, Pan Stanford Publishing, July 2008


37/49



Outline


Nanoelectronics scaling and use of the 3rd

dimension to continue Moores law.



Conclusions

NEMS scaling laws Is it worth scaling?


38/49



NEMS scaling laws. Is it worth scaling?

k3 [rough estimate]energy consumption

k-4mass responsivity

k-1resonant frequency

kstiffness

k3mass

Scaling ruleParameter

twlMeff

3

3

l

tweff

20 lt

Mf

eff

eff

effeff M

f

M

f

2

00 =

=

2

2

1MaxeffP xE

txMax and

- resolution increases- sensitivity decreases (SBR,SNR) => arrays, actuation,- figures of merit pressure and vacuum quality dependent

( )20/10 DReff

Q

Mm =

SNRP

SDR

act

noise 1=

ML Roukes et. al. APL (2005)

Nanowire used for mass detection


39/49



Nanowire used for mass detection

- First 200 mm wafers with 3.5 millions NEMS

- Association Nanowire/Resonator ; Cantilever arrays

CMOS compatible

Capacitive actuation & detection Capacitive actuation & piezo-resistive

detection with nanowires

Thermo-elastic actuation& piezo-resistive detection.

15 nm oscillator

Hzzgm /5.0

Q=870 resonator

Gauge width = 80 nm

LETI: T.Ernst et al., IEDM 2008, Invited talk

L. Duraffourg et. al, APL 92, 174106 (2008)

E Mille et al, Nanotechnology, 165504, (2010)

NEMS array

M&NEMS co integrated devices platform


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M&NEMS co integrated devices platformfor 3D sensing

i

P.Robert et al, 2009 IEEE SensorsD.Ettelt et al, 2011 Transducers

3-axis accelerometerR/R


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NEMS switch

from AB. Kaul et al., Nano Letters 6(5) 942-947 (2006)

high speed

rf

from Q.Li et al.,IEEE Nano 6(2) 256-262 (2007)

bistable

memory

high on/off low powerlogic

from D. Tsamados et al. Solid-State Elec. 52 1374 (2008)

O li


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Outline


Nanoelectronics scaling and use of the 3rd

dimension to continue Moores law.



Conclusions

System On Wafer: Heterogeneous co-Integrated Systems


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Heterogenous Integration On Silicon

80 m diameter TSV

imagers packaging

1 m diameter

High AR TSV stacked ICs

12m1m

Si

Si

12m1m

Si

Si

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Copper/Copper bonding

Oxide/Oxide bonding

Wafer level packaged MEMS

Packaging is taken into account

at the 3D wafer level

y g g y(Parallel 3D)

Embedded passives

(Passives, filters, spin

torque osc,)

Stacked Memories +

Logic, Sensors,,

Optical Interconnects

Energy source

converterMEMS

Stacked ICs

Cooling

option

Commercial products

- image on board VGA camera,- mixed nodes & modes,

- high density TSV

Cross talks:-delay, matching,

-power dissipation

(global temp. increase,

hot spots, reliability, )

Multiphysics

New Progress Laws

- application specific

Viabe

lttechnol

ogy

MEMS+ICs

tack

Ultraflat3D

Chipstac

king(TSV)

ActiveSili

coninterp

oser

3D Integration: from imagers to advanced 3D ICs


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S.Deleonibus CEA-LETI December 2011 | 44Image-on-Board

Active Silicon interposer

Die to Die Copper pillars

Die to substrate

copper pillars

Thinned wafer(~100 m)

Diam 60mThick 120 m

Via Last TSV(Aspect Ratio 2-3)

g g

Memory, Processors,Memory, Processors,Memory, Processors,Memory, Processors, ImagersImagersImagersImagers

withwithwithwith highhighhighhigh densitydensitydensitydensity TSV, NEMSTSV, NEMSTSV, NEMSTSV, NEMS

3D-IC

Metal1

TSV~3m Thin Si~15m

TSV~3m Thin Si~15m

3D highdensity

withTSV

2001

2008

VGA cameras (300kpixels)

withTSV

2001

2008

2001

2008

VGA cameras (300kpixels)

STSTSTST LETI collaborationLETI collaborationLETI collaborationLETI collaborationStack structure

170m

30m

120m

80m

400m

Pitch 120m

Pitch 50m

Stack structure

170m

30m

120m

80m

400m

Pitch 120m

Pitch 50m

Mixed Signal

Digital/Analog STSTSTST LETI collaborationLETI collaborationLETI collaborationLETI collaboration

Photonics Integration on Silicon.


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The building blocks.

Grating coupler

Waveguide

In-plane coupler

Optical modulator

MUX & DEMUX

Laser source

Optical switch

Photodetector

LETI: L.Fulbert ESSDERC 2011, Invited talk

Application DriversGreat focus on packaging & integration


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COMPUT

ING

&STORAG

E

Application Drivers

MOBIL

E

MO

BILE

WIRELESS

WIRELESS HEAL

TH

AUTOMOTIV

E

CONSUME

R

CONSUME

R

FormForm FactorFactor

CostCost

PerformancePerformanceNokia N82, 5Mpixel

Video capture,coding, transmission

Ultra small TVTuner , Sharp

One Chip SetTopBox(STM)

Computer controlusing thoughts

Quad Core Intel

Intel's Teraflop Chip

128 GB SSD, Toshiba

Full tranceiver onChip, Antenna+RF+

Baseband, Leti

Conclusion :Nanoelectronics CMOS from


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Co c us o a oe ect o cs C OS oDevices to Systems Perspectives

Si CMOS: Nanoelectronics Base platform beyond ITRS

Durable Low Power solutions:health, environment, quality of life, energy, IST,

Low Power consumption: major challenge (sub 1V VDD CMOS).

=> Device/ system architecture optimization:

Thin Films Gate All Around nanowires, low slopes,layout, 3D

=> Opportunities for new materials on Silicon

(Ge, revised low BG III-V, Carbon,) to co-integrate from LSTP to HP.

Heterogeneous 3D co-Integration on Si, Low Power: Monolithic/Sequential 3rddimension in device. New active materials Reconfigurability with NVM ; NV Logic

System On Wafer: 2 to 3D heterogeneity functions & chips


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Thank you for your attention

Merci de votre attention


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Electronic Device Architectures for the Nano-CMOS Era

From Ultimate CMOS Scaling to Beyond CMOS Devicesedited bySimon Deleonibus (CEA-LETI, France)Cloth July 2008 978-981-4241-28-1

Discusses the scaling limits of CMOS, the leverage brought by

new materials, processes and device architectures (HiK andmetal gate, SOI, GeOI, Multigate transistors, and others), thefundamental physical limits of switching based on electronicdevices and new applications based on few electrons operation

Weighs the limits of copper interconnects against thechallenges of implementation of optical interconnects

Reviews different memory architecture opportunities throughthe strong low-power requirement of mobile nomadic systems,due to the increasing role of these devices in future circuits

Discusses new paths added to CMOS architectures based onsingle-electron transistors, molecular devices, carbon nanotubes,and spin electronic FETs

Available at Amazon.com or

any good bookstores.

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