Defect mitigation and root cause studies in ,0(&V4 nm half...

Defect mitigation and root cause studies in IMEC's 4 nm half-pitch chemo-epitaxy DSA flow

Hari Pathangia*, Boon Teik Chana, Hareen Bayanaa, Nadia Vandenbroecka, Dieter Van Den Heuvela,Lieve Van Looka, Paulina Rincon-Delgadilloa, Yi Caob, JiHoon Kimb, Guanyang Linb, Doni Parnellc,

Kathleen Nafusd, Ryota Harukawae, Ito Chikashie, Venkat Nagaswamie, Lucia D’Urzof, RoelGronheida, Paul Nealeyg

a IMEC, Kapeldreef 75, B-3001 Leuven, Belgium b EMD Performance Materials Corp., 70 Meister Avenue, Somerville, NJ 08876, USA

c Tokyo Electron Europe Limited, Kerkenbos 10-15 Unit C, 6546 BB Nijmegen, The Netherlandsd Tokyo Electron America, Inc., 2400 Grove Boulevard, Austin, TX 78741, USA

e KLA-Tencor Corporation, 1 Technology Drive, Milpitas CA 95035, USAf Entegris® GmbH, Hugo-Junkers-Ring 5, Gebäude 107/W, 01109 Dresden, Germany

g Institute for Molecular Engineering, University of Chicago, 5747 South Ellis Avenue, Jones 217, Chicago, IL 60637, USA

ABSTRACT

High defect density in thermodynamics driven DSA flows has been a major cause of concern for a while and several questions have been raised about the relevance of DSA in high volume manufacturing. The major questions raised in this regard are: 1. What is the intrinsic level of DSA-induced defects, 2. Can we isolate the DSA-induced defects from theother processes-induced defects, 3. How much do the DSA materials contribute to the final defectivity and can this be controlled, 4. How can we understand the root causes of the DSA-induced defects, their kinetics of annihilation and finally, 5. Can we have block co-polymer anneal durations that are compatible with standard CMOS fabrication techniques (in the range of minutes) with low defect levels. This manuscript addresses these important questions andidentifies the issues and the level of control needed to achieve a stable DSA defect performance.

Keywords: Directed self-assembly, chemo epitaxy, LiNe flow, defect reduction, defect metrology, DSA materials

1. INTRODUCTIONThe golden ages of pure lithography-enabled scaling down of microelectronic circuits are well behind our backs. Directed self-assembly (DSA) has been proposed as a promising complementary patterning option1 for keeping thescaling alive in the coming years, while ensuring an economic benefit to the silicon industry. Various research/industrial groups around the globe have successfully demonstrated DSA processes using block co-polymers to generate line-spacepatterns and arrays of holes with much smaller resolution than the capability of the current lithographic nodes2,3. Severalfigures of merit have been identified and put forward as major checkpoints to assess the relevance of DSA processes for high-volume manufacturing environment; defectivity, roughness, placement accuracy, repeatability, cost of development and implementation being the important ones.

The decision point for DSA insertion into a technological node/integration scheme is not far away. One of the main factors that could make or break the show for DSA to be adopted by the IC manufacturers/production fabs is the level of defects.

Alternative Lithographic Technologies VII, edited by Douglas J. Resnick, Christopher Bencher,Proc. of SPIE Vol. 9423, 94230M · © 2015 SPIE · CCC code: 0277-786X/15/$18

doi: 10.1117/12.2085889

Proc. of SPIE Vol. 9423 94230M-1

Downloaded From: http://proceedings.spiedigitallibrary.org/ on 03/23/2015 Terms of Use: http://spiedl.org/terms

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Defects can be induced by various factors: non-ideal assembly (external and/or on-wafer) conditions, DSA material(s)-induced defects, non-DSA processes related defects (e.g. etch processes) and additionally in most cases, a cross-interaction of the above factors. One of the main challenges is to be able to identify/isolate the impact of the above factors on the different defect types we see after DSA. Figure 1 shows a schematic representation of the 14 nm half-pitch LiNe flow implemented at imec. In our previous work, we have shown that the defect density after pattern transfer in a 14 nm half-pitch LiNe flow can be reduced4 up to 200 cm-2. This manuscript will further this towards more aggressive defect reduction strategies. More importantly, we discuss in detail about the process/material contributions to the different kinds of defects observed and a further modeling of DSA defect evolution by using a design of experiments (DoE) statistical model.

Figure 1: A schematic representation (not to scale) of the 14 nm half-pitch LiNe flow implemented at imec.

2. MATERIALS AND METHODS 2.1 Materials

Cross-linkable poly(styrene) (XPS, AZEMBLY™ NLD128), hydroxyl-terminated poly(styrene-random-methyl methacrylate) (P(S-r-MMA)-OH) brush (AZEMBLY™ NLD127), and poly(styrene-block-methyl methacrylate) (PS-b- PMMA, AZEMBLY™ PME312) BCP with L0 = 28 nm, were synthesized by Merck Performance Materials and were used as received. ArF immersion photoresist AIM5484 used for pre-pattern exposure was purchased from JSR Micro. Organic solvent RER650 used for edge bead removal of DSA materials and brush rinsing was obtained from Fujifilm and the photoresist strip chemistry, Orgasolv STR 301TM was obtained from BASF.

2.2 Process flow

The process used for this experiment is based on our previously reported method for the fabrication of chemical nanopatterns3. All processing was performed at imec on a TEL CLEAN TRACK™ LITHIUS ProZ™ system. Pre-pattern with a pitch of 84 nm were exposed using an ASML NXT:1950i scanner at 1.35NA using quadrupole illumination (XY polarized, NA= 1.35, σo=0.87, σi=0.72). A SiN antireflective coating (ARC) layer of 13 nm was deposited by chemical vapor deposition (CVD) on p doped 300 mm Si substrate. The XPS film, with a target thickness of 7 nm, was spun and annealed at high temperature for 5 min under a N2 atmosphere.



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After resist coating and exposure using vendor recommended settings for post-apply bake (PAB), post-exposure bake (PEB), and development, lines and spaces of 84 nm pitch and critical dimension (CD) of 38 nm were obtained. O2 and Cl2 plasma etch was used to trim the resist to target 17 nm CD and to remove the XPS in the trenches. The remaining resist was stripped at room temperature with Orgasolv STR 301. The P(S-r-MMA)-OH brush was spun and annealed for 5 min at 250°C in a N2 atmosphere. Non-reacted brush material was rinsed with RER650. The PS-b-PMMA BCP was coated on the chemical patterns and annealed at a specific temperature in a N2 atmosphere. The duration and the temperature of the anneal depended on the nature of the study conducted and is mentioned in the results and discussion section wherever relevant relevant. Defect inspection was done in KLA-Tencor’s 28xx platform and a subsequent scanning electron microscope (SEM) review was performed in KLA-Tencor’s eDR7xxx platform.

2.3 Metrology

For defect inspection and source identification, the tool utilized in this study is a broadband plasma optical inspection system (28xx). This is a widely adopted tool for both R&D and production monitoring inspection applications. The initial setup of the tool (wavelength, apertures, modes etc.) was done based on the results of a proprietary offline simulation methodology from KLA-Tencor, which uses a Rigorous Coupled Wave Analysis (RCWA) method to solve the EM simulation. Directed Self Assembly, being a new generation lithography process, the critical defects of interest (such as dislocation and 1-period flat bridges post-Si etch ) were first studied by simulations to determine the optimal optical settings to maximize signal. The recipe was then verified and further optimized to maximize sensitivity to all defects of interest whilst suppressing potential noise sources. The methodology for the DSA of DSA experiment used in this manuscript is exactly the same as described in an earlier publication5, except that this methodology is now extended up to the final pattern transfer (Si etch). The methodology for the DoE of DSA experiment is as follows: All the wafers as described in the experimental space shown in Figure 2 were processed following the LiNe flow (with appropriate splits and process changes as applicable). The wafers were subjected to optical defect inspection and SEM review after Si etch and defect density Paretos were plotted. The total defect density and the densities of the individual defect modes like dislocations, 1-period flat bridges, residues were fed as inputs for the statistical model in JMP11® software.

Figure 2: The experimental space explored by the design of experiment (DoE) – described in Section 3.3 showing the

four parameters tested.

3. RESULTS AND DISCUSSION 3.1 Defect monitor

A weekly defect monitor exercise is run as a part of the defect understanding project. 1 focus exposure matrix (FEM) wafer and 1 uniform wafer (CDU) at the best focus-dose condition are run through the PoR LiNe flow processing conditions. The FEM wafer is processed until PMMA removal (as shown in Figure 1) and the CDU wafer is processed until Si etch.



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The CDU wafer is subjected to optical defect inspection before XPS coat (to establish the incoming defectivity), after trim etch, resist strip, NUL rinse, PMMA removal and Si etch and subjected to SEM review after Si etch. The FEM wafer is subjected to an optical scatterometer-based grating qualification study (after PMMA removal) to quantify the degree of order in the post-DSA line space gratings, as reported earlier6. The result from the FEM wafer inspection is used to identify/confirm the optimal pre-pattern exposure conditions in order to maintain good guide pattern fidelity resulting in good DSA performance. An example of the result from the FEM wafer inspection is shown in Figure 3a. Figure 3b shows the defect monitor results from the year 2014. This monitor data acts as the baseline for all our defect reduction studies to benchmark the defect level changes that result from intended material/process improvements and tool/process drifts. The root causes of most of the excursions in Figure 3b have been identified as process and/or tool drifts and variability in the DSA material batches. A detailed analysis/description of this monitor data is beyond the scope of this manuscript and hence shall not be discussed here.

(a) (b)

Figure 3: A typical FEM wafer measurement showing the right process window in terms of the pre-pattern exposure condition (green = good assembly in terms of grating quality and red = bad assembly).

To increase the ease of comprehension through the rest of the manuscript, especially for the non-regular DSA readers, Figure 4 shows SEM images of typical defects we encounter in our flow that can be broadly classified into 3 kinds. While dislocations (Figure 4a) are certainly known to be defects created during the BCP anneal (even though at times, they might be induced by external factors, like particles) we have data that indicate a possible link between the annealing process/DSA material composition and the 1-period flat bridges. The other defects, like the residues, at this stage we believe are most probably caused by non-DSA processes, like the resist strip, dry etch steps etc. A more detailed description of all the individual defect modes and their possible root causes will follow in a later section.

(a) (b) (c)

Figure 4: SEM images of most typical defects observed in our DSA flow - (a) Dislocations, (b) 1-period flat bridge and (c) Residues with topography.

3.2 Defect Metrology Sensitivity

As pointed out earlier, we perform our final optical defect inspection and SEM review after pattern transfer. We have already shown that performing defect inspection after pattern transfer increases the inspection sensitivity by about 10 times4. We have also established that the dark field mode recipe we use for our inspection is extremely effective in capturing the very flat small bridges spanning just 1 period, which means they are roughly 14x14 nm2 in dimension.4



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Nevertheless, it is important to ensure that we have a good defect capture rate, especially for the DSA relevant defects, like dislocations. This is especially important as the defect capture rate, even after pattern transfer, can be extremely sensitive to various parameters like etch depth of the patterns, their sidewall profile etc. Also, the morphology of the dislocation defects is very unique compared to more conventional lithography induced defects and the absence of a topographical/chemical contrast in these defects imposes a big challenge for defect inspection tools to capture them with good sensitivity.4

To estimate the capture rate of dislocations, we make use of the programmed defects available on the reticle. A matrix of 200 programmed defects with a CD bias (shown in Figure 5), ranging from 2 nm to 20 nm in steps of 2 nm was used for this study. The programmed defects can induce dislocations due to the local CD change and since these coordinates are known, we could image all the reticle-defined locations using a SEM to verify how many of them actually resulted in a dislocation. We observed that the BCP assembly in our flow heals any CD variation as long as the CD bias is less than or equal to 35% of its L0. In a typical die, the defect inspection recipe captured 16 of the dislocations (confirmed after SEM review of the inspection coordinates) among the programmed defects, while the SEM based verification revealed a total of 21 dislocations. This resulted in a 76% capture rate of dislocations after pattern transfer into the Si substrate. Furthermore, it was observed that the S/N ratio of the programmed defects that were captured by the inspection tool was greater than 1.3 and mostly in the region between 1.8 and 2.8, which is indicative of reliable capture of such defects. Additionally, it was observed that only very small dislocations (usually, spanning <4 periods) could not be captured with our inspection recipe (Figure 6). We expect that this could possibly be mitigated by going to a more powerful defect inspection platform like the KLA Tencor’s 29xx series. Nevertheless, the capture rate of 76% for dislocations adds to the confidence level of our inspection recipe and thereby substantiates the relevance of the observations/conclusions discussed in this paper.

(a) (b)

Figure 5: (a) A schematic representation of the mask layout of the programmed defects (CD bias). Each point represents the center of the programmed defect location on the x-y space on the wafer. From left to right, the CD bias increases

from 2-20 nm in 2 nm steps. The points marked as ‘D’ are the programmed defects that resulted in a dislocation (confirmed with SEM review). (b) A contour map of the signal to noise (S/N) ratio of the programmed defects as

measured in the inspection tool.

Figure 6: Typical SEM images of the small dislocations that were not captured by the inspection recipe.



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3.2 DSA of DSA

Directed self-assembly in its root is considerably different from usual lithographic techniques, in the nature and in the number of the steps involved. Hence, while discussing the defect distribution in directed self-assembly flows, it is of utmost importance that we isolate and understand the possible root cause(s) of the various defect modes, especially because defects that have a similar morphology to defects from older/other lithographic schemes could very well be caused by a different mechanism. A very good example of this can be the flat 1-period bridges that we see after pattern transfer. This will be clarified later in the section.

In an attempt to understand the root causes of our defects, a defect source analysis (DSA) of KLA-Tencor of our DSA flow was performed. The experimental approach (shown in Table 1) is very similar to our previous exercise as reported in5, except in this case, we extend the DSA of DSA all the way up to Si etch process. The defect Pareto of the control wafer that was inspected and reviewed only after Si etch is shown in Figure 7. Figure 8 shows the results of the DSA of DSA experiment. The total defect density measured at each step is plotted. At each process step, the defect contribution from all the previous step(s) (common) and the defects that are added exclusively from the said step (adders) can be distinguished by this approach. The defects that were classified as adders at each process steps were imaged using a review SEM to get a visual on the type of defects created by each process step. Figure 8 also shows typical examples of the adder defects at each process step.

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Si etch I/R I/R Table 1: Experimental split matrix showing the DSA of DSA methodology. N = not inspected, I = optical defect inspection,

R = SEM review and I/R = optical inspection AND review.

Figure 7: Final defect Pareto of the control wafer (after Si etch).



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We observed that the defects formed during the XPS coat step remain the majority contributors, certainly until Si etch and even after pattern transfer, the step contribution from the XPS layer is the maximum, albeit small. About 91% of the total defects at the XPS layer were so called “bright spots”, which are caused by incompatibility between the XPS material and the under-layer due to local surface energy changes. This can be mitigated by surface treating the under-layer, for example with a plasma exposure or by treating it with a specific brush to increase the coating compatibility. On the other hand, custom-modifying the XPS material itself to coat it on specific under-layer(s) is also a viable option. Figure 9 also shows the optical polarity distribution of the XPS coating defects and examples of each kind. After XPS coat, resist strip and NUL process steps were found to be the major defect contributors. A big majority of defects captured after pre-pattern exposure were found to be SEM non-visibles. Only about 6% of the defects were found to be bridges and an equal amount were residues (Figure 8). About 40% of the adders after the trim etch process were found to be etch-induced residues (Figure 8), while the rest was SEM non-visible. The adders after the resist strip (Figure 8) process were observed to be mostly line bridging (40%) and ~20% particles/residues, which all contribute a non-ideal chemical pattern. The adder defects from the NUL process step present in the form of 18% bright and 16% dark spots, which are mainly interruptions in the neutral backfill region and a small 6% particle/residues contribution.

Figure 9: Sample optical patches and corresponding SEM images of the bright and dark defects after XPS coat.



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A big majority of adder defects after Si etch process cannot be truly and fully interpreted as defects induced during the etch process. This we believe is mainly because the defect inspection recipe for all intermediate process steps (until NUL process) uses a brightfield aperture mode, while the recipe after pattern transfer uses a darkfield aperture mode. These choices were so made to obtain the best capture rate at the respective process stages. We know that the darkfield aperture mode recipe offers a significantly higher sensitivity than the previous inspection recipes. Hence, comparing the step defect contribution before and after pattern transfer is not exactly fair. This hypothesis can be verified by inspecting the wafers at all the process steps with the same optical settings. Unfortunately, that was not an option as the non-ideal optical settings did not give us dependable inspection results. However, a closer look at the common defects between the final Si etch step and the 3 major contributing steps (XPS, resist strip and NUL) provides a phenomenological proof to the above hypothesis. Table 2 summarizes the statistics and images of the common defects. We observed that in all the 3 cases, about half of the common defects were dislocations and a third of them were 1-period bridges. Do note that these two defect modes account for about 54% of the total defect density after Si etch (with a very sensitive inspection recipe) and a majority of the common defects at the three intermediate steps (with lesser sensitivity). Given that dislocations cannot be possibly induced during the Si etch process (after BCP anneal), this could hint that if the inspection sensitivity of all the steps were similar, we could expect to see a bigger contribution of the initial DSA processing in the final defect levels.

Table 2: Defects distribution showing the common defects between XPS coat, resist strip and NUL process respectively with the Si etch process with sample SEM images.

3.3 DoE of DSA

In the previous section, we established the major defect contributors in terms of the process steps. For gaining a deeper insight into the other variables that contribute to the final defect density and their possible interaction with one another, a thorough D-optimal design of experiment (DoE) was performed. The experimental parameters that were tested include, pre-pattern exposure dose (this determines the CD of the guide stripe), BCP anneal time, BCP anneal temperature and Si etch duration (this determines the etch depth into the Si substrate). Si etch depth was added as one of the variables to include the effect of the inspection sensitivity with changing etch depth in a controlled manner. The exact experimental space explored is shown in Figure 2. Data analysis to arrive at a predictive model was performed in JMP 11. The final model was optimized by an iterative process for a minimal t factor. A screenshot showing the goodness of fit and t factor is shown in Figure 10 for the model discussed here. The experimental results of total defect densities and the density of the majority defect modes (residues, 1-period flat bridges and dislocations in that order) were fed into the DoE as inputs for the model. Do note that the defect Pareto for this study is different from the one presented in the previous section. This is due to a different batch of the BCP material based on the feedback from the learning of the DSA of DSA.



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The results of the model are summarized in Figures 11-14. The main conclusions of the DoE are as follows: total defect density has and inverse correlation with the pre-pattern exposure dose (guide CD) and BCP anneal temperature and a direct correlation with the Si etch time (etch depth). BCP anneal time, however shows a clear minimum at 250 minutes. The fact that the total defect density decreases with the guide CD should be considered along with the observation that this could be an effect of the trend we see for the residues (Figure 12) and that the residues are the majority defects for the material batch we used in this study. This is especially important as both dislocations and 1-period flat bridges have a very strong quadratic guide CD dependence. The effect of the BCP anneal temperature, however is a bit more straight-forward to understand. It could be expected that increasing the anneal temperature (within the decomposition range of the BCP system) helps the system to reach equilibrium faster. The increase in total defect density with increasing etch depth however could be due to two causes; one being an increase in the metrology sensitivity with increasing etch depth and two being more etch-induced defects being created with a longer etch duration or due to a mixture of both causes. While, it is apriori difficult to separate these two effects, further experiments are on-going to decouple the effect of change in the metrology sensitivity with the increasing etch depth.



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Figure 12: DoE model for the evolution of residues with topography

Predictive models for dislocations are shown in Figure 13 and for 1-period flat bridges in Figure 14. The first observation for the dislocations model is that their density is extremely sensitive to the guide CD. As soon as we tread away from the optimal pre-pattern exposure dose (~18 mJ cm-2) in either direction, there is a steep increase in the density of dislocations. This naturally comes from the incommensurability of the BCP’s L0 with the CD of the guide pattern. Another important conclusion from this model is that the anneal duration required to achieve zero dislocations density is dependent on the anneal temperature. For an anneal temperature of 250 OC (our previous PoR), the model predicts ~200 minutes to get rid of all dislocations. On the other hand, at 255 OC (our current PoR and the condition of the champion defect wafer of this experiment, zero dislocations density could be (theoretically) achieved in little less than an hour. Also, important to note that the model does not include the effect of the Si etch duration (within the tested range) in predicting the dislocations density (due to absence of a good correlation), implying that as long as the etch is deep enough to get enough inspection sensitivity, dislocations are always captured with the same sensitivity and that the etch process does not induce dislocations, which should not be a surprise to us.



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Figure 14: DoE model for predicting the density of 1-period flat bridges

The model for the 1-period flat bridges also presents us with important learning points, especially when viewed along with that of the dislocations. It is clear that the 1-period bridges also have a clear guide CD dependence, but the exact opposite trend of the dislocations. This could be an ominous sign for DSA line/space flows as this might hint towards a compromise between the 2 major DSA-relevant defect modes, namely dislocations and 1-period bridges, a compromise that will not improve the desirability of DSA for yield sensitive high volume manufacturing.



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Fortunately, we have established that the chemical composition (in other words surface energy and/or preferential behavior) of the DSA material(s) can be tuned independent from these process parameters to lower/spike-up the density of these 1-period bridges (results presented in the next section). This highlights two very important conclusions - One: For a successful DSA defect reduction approach, one should consider this strong interaction between the material(s) and process parameters as both these factors have a major impact on the DSA defect density. This could truly be considered as the take-home message from all the studies presented in this manuscript. The second conclusion is rather the flip side of the previous statement being: the variability in terms of the defect relevant material properties become quite important and should be carefully controlled and monitored to achieve a stable and low DSA defect performance. The same holds true for the level of process control (in addition to materials control) needed, which is fortunately not difficult to achieve in a semiconductor fab.

Getting back to the DoE model, it is evident that the 1-period bridges could be annihilated by increasing the BCP anneal time and temperature. This strongly suggests that these bridges (at least a part of them) could be induced during the BCP phase separation, like dislocations. Additionally, for both the 1-period bridges and the residues, a minimum is predicted between 200-250 minutes, very similar to the prediction of the total defect density. Further studies (with the same material batches) are planned to confirm the truth of this prediction.

3.4 Effect of the brush material

As described in the previous section, we present an example of using the material composition to intentionally modify the relative distribution of individual defect modes. The PoR LiNe flow uses a neutral back-fill brush to enable perpendicular orientation the PS and the PMMA blocks landing on the back-fill region (Figure 1). As the hydrophobicity (in other words, the neutrality) of the brush material is altered, we observed that the process window in terms of the registration defects (like dislocations) and the relative densities of 1-period flat bridges can be modulated quite dramatically. As seen in Figure 15, for the same BCP system and similar processing conditions, going from a lower to higher hydrophobic brush material, the densities of dislocations and bridges can be modified. This case-study strongly proves the importance for co-optimizing the process parameters for a given set of materials used in a particular flow. Additionally, this establishes the need for low variability in the DSA materials for a stable and low defect performance.

Figure 15: Trend showing the changes in the densities of dislocations and 1-period flat bridges as a function of the chemical composition of the brush. The % of SEM images (field of views) with defects was calculated based on

reviewing 1300 SEM images across 13 dies across the wafer for each brush composition.

3.5 Defect Step-down in 2014

The learning from the DSA of DSA and the DoE of DSA experiments were used to demonstrate a successful defect step-down through the year 2014 (Figure 16). In January, our golden defect process resulted in a 200 cm-2 defect levels, mainly contributed by uniformity improvement in the Si etch process.



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The golden defect process in June 2014 resulted in ~110 defects cm-2 combining the optimized etch process and an optimized coat methodology of the DSA materials, namely XPS, NUL and BCP and by getting rid of the redundant soft bake steps before the anneal bake in each layer.

In September 2014, we demonstrated a golden defect process of 48 cm-2. This was achieved mainly by using the optimal batch of DSA materials and by increasing the anneal temperature from 250 OC to 255 OC. In October 2014, we demonstrated the current golden defect process of 24 defects cm-2 by combining all the above optimizations with a new and optimized Si etch platform that gave better after-etch profiles. It should be noted that the dislocations capture rate of 76% was measured for this new etch depth and profile. The defect Pareto of the current golden defect process is shown in Figure 17. The residues spanning multiple periods still remain to be a major contributor to the total defectivity, followed closely by 1-period bridges and dislocations. It should be noted that our final defect density of 24 cm-2 includes both the DSA and non-DSA relevant defects. It is important to note that this reduction in the defect levels is coupled with a stark reduction in the anneal duration required to reach the golden defectivity performance. The current golden performance is 2.5 hours at 255 OC. Further efforts to reduce the BCP anneal duration to more CMOS compatible time scales is are on-going.

Figure 16: Trend showing the golden defect performance of the 14 nm half-pitch LiNe flow through 2014 and the corresponding reduction in anneal duration from 12 hours to 2.5 hours.



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4. CONCLUSIONS We have demonstrated a golden defect performance of 24 defects cm-2 in the 14 nm half-pitch LiNe flow. This was aided by an all-round optimization of many processes, including Si etch process, spin-coat step of the DSA materials, fine-tuning of the BCP anneal conditions and most importantly, using the optimal batch of the bloc co-polymer. We have also established that we currently have a capture rate of 76% for dislocations during our optical defect inspection after pattern transfer. This helps us in determining the confidence levels in our metrology. From the DSA of DSA experiment, we have shown that the XPS coat and NUL process steps are the major contributors for the dislocations and the 1-period flat bridges. More importantly, the DSA of DSA showed that the root cause(s) for all the DSA relevant defect modes we see after pattern transfer could be identified in one or the other intermediate process step. No fundamental limitation for DSA defect reduction was observed.

The most important inference from this manuscript is the importance of understanding the contribution of the DSA materials to the final defect levels. The ability to tune the chemical composition (in other words, surface energy/preferential behavior) of the DSA materials provides us with a unique opportunity to tune the defect levels in a DSA flow to a minimum. In other words, it is of utmost importance to monitor and control the variability in the defect relevant material parameters for a stable defect performance. Understanding the relevance and co-optimizing the process conditions and the material properties can be deemed as vital in understanding DSA defect root causes and mitigating them. It is in this regard that exercises like the DoE presented in this manuscript give valuable and dependable insight towards achieving single digit and probably lower DSA defect levels. As a conclusion, we have demonstrated that DSA defect densities can be reduced with an aggressive all-round approach involving materials and process improvements to a level where DSA could become more and more relevant for the end-users. More importantly, we have shown different strategies to identify and isolate the different root causes of the various defect modes observed in our DSA flow. This understanding is critical to maintain a stable and low defect performance in DSA flows.



REFERENCES

[1] Hinsberg, W. D., Cheng, J., Kim, H.-C., Sanders, D., "Self-assembling materials for lithographic patterning: overview, status, and moving forward," Proc. SPIE, Vol. 7637, 76370G-1 (2010).

[2] Wong, P., Bencher, C., Bao, X.-Y., Chang, L.-W., "Block copolymer directed self-assembly enables sublithographic patterning for device fabrication," Proc. SPIE, Vol. 8323, 832303-1 (2012).

[3] Kim, S. O., Solak, H. H., Stoykovich, M. P., Ferrier, N. J., de Pablo, J. J., Nealey, P. F., "Epitaxial self-assembly of block copolymers on lithographically defined nanopatterned substrates," Nature, 424, 411-414 (2003).

[4] Gronheid, R. et al., “Defect reduction and defect stability in IMEC's 14nm half-pitch chemo-epitaxy DSA flow”, Proc. SPIE, Vol. 9049, 904905-1 (2014).

[5] Rincon, P.A. et al., “Defect source analysis of directed self-assembly process (DSA of DSA)”, Proc. SPIE, Vol. 8680, 86800L1-9 (2013).

[6] Gronheid, R. et al., “High Throughput Grating Qualification for Rating Directed Self-Assembly Pattern Performance using Optical Metrology”, Journal of photopolymer science and technology, Vol. 26, No. 2, 147-152.



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