Defect Localization Using Physical Designand Electrical Test Information

Zoran Stanojevic

Dept. of ElectricalEngineering

Texas A&M UniversityCollege Station TX 77843

Tel: (979) 862-6610Fax: (979) 847-8578

Email: zoran@cs.tamu.edu

Hari Balachandran

Texas Instruments, Inc.Mixed Signal Products

Dallas TXTel: (214) 480-7602Fax: (214) 480-7676Email: harib@ti.com

D. M. H. Walker

Dept. of Computer ScienceTexas A&M University

College Station TX 77843Tel: (979) 862-4387Fax: (979) 847-8578

Email: walker@cs.tamu.edu

Fred Lakhani

SEMATECHYield Management Technology

2706 Montopolis DriveAustin TX 78741

Tel: (512) 356-7011Fax: (512) 356-7640

Email: fred.lakhani@sematech.org

Sri Jandhyala

Texas Instruments, Inc.Mixed Signal Products

Dallas TXTel: (214) 480-7598Fax: (214) 480-7676Email: srij@ti.com

Abstract

In this work we describe an approach of usingphysical design and test failure knowledge to localizedefects in random logic. We term this approachcomputer-aided fault to defect mapping (CAFDM).An integrated tool has been developed on top of anexisting commercial ATPG tool. CAFDM was ableto correctly identify the defect location and layer inall 9 of the chips that had bridging faults injected viaFIB. Preliminary failure analysis results onproduction defects are promising.

Keywords

Defect diagnosis, testing, failure analysis, faultdiagnosis, fault localization, defect localization, faultisolation, defect isolation

1. Introduction

Fault localization or fault isolation is the process ofidentifying a region within an integrated circuit (IC)that contains a circuit fault, such as a short or opencircuit. This region must be small enough that thedefect causing the fault can be found and analyzed.This is very important for debugging new products,ramping yields, identifying test escapes andreliability problems in customer returns, andresolving quality assurance (QA) part failures. Thisproblem is made more difficult by more interconnectlayers and increased layout density, which oftenpreclude a direct view of a defect site. This makesapplication of traditional defect localization methods.The International Technology Roadmap forSemiconductors projects the complexity of faultisolation to grow by 142 times over the next 15 years[1].

Current state-of-the-art practice for localizingdefects in logic circuits is to use a stuck-at faultdiagnosis approach. A set of passing and failing

vector outputs is captured, typically at wafer test, andfed into the diagnosis system. The diagnosis producesa ranked list of nets on which a stuck-at fault bestexplains the observed failure patterns. A list oflogically equivalent nets is also provided. Anexample of logical equivalence is that a stuck-at-1fault on an input to an OR gate is logically equivalentto a stuck-at-1 fault on the OR gate output. Stuck-atdiagnosis tools are commercially available as part ofan automatic test pattern generation (ATPG) system,such as Mentor Graphics FastScanTM

and IBMTestBenchTM. The list of suspect nets can bevisualized in the chip layout database using a toolsuch as Knights Technology LogicMapTM

[2][3].Since even individual nets can be large, the idea caseis that a “hit” was seen in wafer inspection, in that adefect was observed near one of the suspect nets.This location can then be examined with a scanningelectron microscope (SEM). This procedure is shownin Figure 1. Unfortunately such inspectioninformation is only available for a small fraction ofall chips. The result is that the SEM search time foreven a few nets can be quite lengthy, dominatingtotal fault isolation time. A further challenge is thatsince signal nets often run only on interior layers,delayering must be performed prior to the inspectionof a given layer. This delayering process can removethe sought-after defect, and precludes the applicationof additional test vectors to aid the search process.

Bridging faults are the most common faultybehavior caused by defects. However, stuck-at faultsare not a very good model for bridging faults [4]. Asa result, the stuck-at diagnosis can produce poorresults, in that the real faulty nets are far down the listof suspects and so are never examined due toresource constraints, or they are not on the list at all.As a result, a significant fraction of the time thediagnosis fails. This wastes failure analysis labresources, reduces the rate of yield learning, and canmake QA quite difficult since typically there are onlya small number of failed devices to examine.

Sample Diefor FA

ElectricalTest Data

InlineData

FIB, EDX etc.Physical

Failure Analysis

Diagnosis DefectKnowledge

Base

Experience

LikelySource

Design & Test Data

SEM Isolationof Defects

Run DiagnosticTestSuspect Nets

hours

hours,days

minutes

Figure 1. Current Defect Sourcing Approach

The solution approach used in this work iscomputer-aided fault to defect mapping (CAFDM).Rather than replace the mature stuck-at diagnosisinfrastructure, our goal is to combine this testinformation with physical design information toreduce the SEM search area. As shown in Figure 2,we use physical design information to identifylocations and layers within the circuit where shortand open circuit faults can occur. This information isused to filter and improve the suspect net listprovided by stuck-at diagnosis. The result is that themature stuck-at diagnosis infrastructure is used, whileits primary disadvantages are overcome. The projectmetrics are shown in Table 1. The metrics areinterrelated in that by using layer and locationinformation to reduce the search area, we also reducethe fault isolation time and failure rate.

In the remainder of this paper we describe theCAFDM approach and our experimental results.Section 2 describes previous work on defectdiagnosis. Section 3 presents the CAFDM approach.Section 4 describes experimental results and Section5 concludes.

2. Previous Work

Several methods have been suggested to improvediagnosis of bridging faults using the stuck-at faultmodel. A vector that detects a bridging fault also

detects an associated stuck-at fault [5]. Compositesignatures can be constructed for each potentialbridging fault by the union of the four associatedsingle stuck-at signatures. However this techniqueresults in an unacceptable rate of misleadingdiagnoses. An improvement is to use only realisticfaults, and better match restriction [6], which wasdemonstrated experimentally [7]. Using severaldifferent fault models can improve the diagnosisresults [8]. These improved approaches require theconstruction of a large fault dictionary. In particular,it is often a requirement that one of the bridged netsbe included in the dictionary in order to achieve asuccessful diagnosis. Since there are hundreds ofthousands of nets in today’s large industrial circuits,the dictionary construction can be very expensive.

Table 1. Project Metrics

Description Baseline Goal

Failed Diagnosis 30% <15%Physical Layer Ranking No YesPhysical Location Ranking No YesSmall Suspect List (< 10) 80-95% 90-99%Average Localization Time Days Hours

Sample Diefor FA

ElectricalTest Data

InlineData

FIB, EDX, etc.Physical

Failure Analysis

Diagnosis DefectKnowledge

Base

Experience

LikelySource

Design & Test Data

DiagnosticTest

SEM Isolationof Defects

CAFDM onSuspects

Reduced Suspects w/Locations, Layers

Figure 2. CAFDM modification of existing faultdiagnosis approach

The best bridging fault diagnosis results can beachieved by modeling the bridging fault behavior atthe circuit level, and using layout information toidentify adjacent nets that could be involved in abridge [9]. The drawback is the need for a completelydifferent diagnostic infrastructure, such as a bridgingfault simulator [10]. The separate infrastructuresubstantially increases the cost of diagnosis.

3. Computer-Aided Fault toDefect Mapping

In CAFDM we assume that with the addition ofbridging faults we can accurately model the behaviorof most faults, and that the addition of physicaldesign information will reduce the search areasufficiently to achieve small SEM search time.

3.1. Fault Extraction

The initial CAFDM implementation is shown inFigure 3. A fault extractor identifies the critical areaswhere short circuits could occur on the suspect nets,including their locations and layers. We only extractshort circuits since open circuits can be modeledreasonably well with the stuck-at fault model.

Design Data

Fault Extractor

FaultSimulation

FaultInjection

Test Vectors

Simulated FaultSignatures for Suspects

SignatureMatching

TechnologyDescription

Ordered list of short faultsuspects w/ locationregions and layers

Stuck-Atsuspects

Bridge fault listw/layer, location

Netmatching

Generate newfault list

Figure 3. CAFDM Implementation

Previous work on fault extraction has tended tofocus on accuracy of the critical areas associated witheach fault [11][12]. However these approaches aretoo slow to extract bridging faults for a largeindustrial circuit in a reasonable amount of time. Onechallenge is that hierarchical techniques [11] workpoorly on the essentially random routing in an ASIC-style logic design. In addition for the purposes offault diagnosis it is more important to identifypotential bridging faults rather than to accuratelypredict their probability.

To solve this problem, we have developed a newfault extractor, FedEx, with a goal of extracting alltwo-node bridging fault sites that are possible for amaximum defect size. This is similar to the goal ofthe AMD fault extractor [13]. The maximum defectsize is chosen to be large enough to so that Fedexenumerates all likely bridges.

FedEx uses a scanline approach to circuit andfault extraction. The geometry is sorted in decreasingy coordinate. A horizontal scanline is passed downover the geometry. As geometry intersects thescanline, it is inserted into associated data structuresand nets are extracted. Since devices are not involvedwith bridging faults, they are not explicitly extracted.However to ensure separate nets, active areas are splitby the gate layer.

As extracted geometry leaves the scan line, it isplaced into a trailing window, and critical areascomputed between nets, using rectilinearapproximations. These approximations are accurateto within about 20%. Each bridging fault site includesthe layer, bounding box of the critical area, andweighted critical area. There can be multiple sitesbetween a pair of nets, due to the finite size of theanalysis window. The critical area weighting is doneusing the 1/x3

defect size distribution, so that whendivided by the chip area, the weighted area is therelative probability of failure. In its prototypeversion, FedEx can extract 500K transistors of logicin about one hour of CPU time and 350MB ofmemory on an engineering workstation. We expectsubstantially higher performance with furtheroptimizations.

3.2. Fault Diagnosis

For each chip being diagnosed, FastScan uses a set ofpassing and failing vectors to generate a set ofsuspect nets. This typically takes less than one minuteon million-transistor designs on a typical workstation.The Verilog net names must then be translates tolayout net names. The design methodology mustprovide this mapping. These nets are then matchedagainst the bridging fault list to identify the list ofpotential bridging faults.

The potential bridging faults and stuck-at faultsare injected into the netlist one at a time andsimulated with the test vectors. The Wired-AND,Wired-OR, and Wired fault models are used, sinceany one might best model the fault behavior. TheWired model propagates an X condition on thebridged nodes if they are driven to opposite values.

The Hamming distance (the number of bitpositions in all vectors that differ) between thesimulation output and the tester output is computed,and sorted in increasing order of distance. We choseHamming distance rather than number of vectormatches to achieve higher resolution. An X output(from a Wired fault) has a distance of 0.5 from atester 0/1 output. Only the smallest Hammingdistance for each bridging fault model is recorded.The result is a ranked list of suspects. For bridgingfaults the layer and location information for all thefault sites between that net pair are given.

For faults with the same Hamming distance,further ranking is done using the weighted criticalarea, with faults with larger critical area being rankedfirst, since they are more likely to occur. Rather thanranking first by Hamming distance and then criticalarea, it may be more appropriate to use a weightedcombination of metrics, so as to rank based onexpected search time. Rather than modify theranking, all this information is provided to the userand left to their judgement. The ranked list ofsuspects is then used to perform the SEM search.

Limiting the number of reported suspects requiresdiscarding matches below some threshold. For ourprototype implementation we did not discard anysuspects, leaving it to the user to ignore suspects thatwere poor matches to the measured data. This alsoallowed them to stop searching if there was a largejump in Hamming distance from one suspect to thenext.

3.3. Stuck-At Diagnosis Failure

One problem with using stuck-at diagnosis to filterthe possible suspect nets is that it can fail. Thishappens when the fault behavior is not a good matchto the stuck-at model. The result is that the real faultynets may not be on the reported suspect nets. Thissituation occurs in 10% or more of faulty chips. Inour CAFDM methodology, this results in theHamming distance of all the stuck-at and bridgingfault suspects exceeding a user-defined threshold.This situation could also occur if the simulated faultmodels are not a good match for the fault behavior,which is a failure for our approach. An example iswhen multiple faults are present in the chip.

We can handle the case of stuck-at diagnosisfailure by using a backconing procedure. For each

faulty output, the logic cones are identified, that is,all the nets for which there is a circuit path to theoutput. All the potential bridging faults to these netsare identified. This procedure is repeated for allfaulty outputs in all vectors. These bridging fault listsare intersected to find the potential bridges in whichone side or the other has a circuit path to all faultyoutputs. The idea is that this bridge can potentiallyexplain all faulty outputs. The resulting fault list isused as input to the fault simulation proceduredescribed in the previous section. The backconingprocedure should be used only when stuck-atdiagnosis fails since the backconing procedure takesadditional time, and the potential bridging fault list islarger than that obtained from stuck-at diagnosis.

4. Experimental Results

A case study using the CAFDM software was carriedat out at Texas Instruments (TI), Mixed SignalProducts Division, Dallas TX. The target chip fordiagnosis was a streaming audio controller. It is a1M-transistor, mixed-signal design, implemented in a250-nm technology. This design has about 500Ktransistors of digital logic and a small amount ofanalog circuitry, and the remainder memory arrays.The die size is 3.75 mm by 3.75 mm. The digitallogic uses a full scan design, which permits FastScandiagnosis. There are 26 953 labeled nets subject todiagnosis. Since the memory arrays are diagnosedseparately, they are removed for FedEx analysis.

Using a maximum defect size of 2.25 microns,FedEx extracted 2.8M bridging fault sites. Of thesethere are 1.6M unique bridging pairs. The averagecritical area for each fault site is 5 µm2, smaller onthe diffusion and poly layers, and larger on the uppermetal layers, due to their long parallel runs. Thelargest area is 0.64 mm2, which occurs on metal4 onthe global reset line, which itself has 93,376 bridgingpairs. This large critical area is caused by the fact thatthe area is computed as the bounding box containingall critical areas in that region between the net pair atthe maximum defect size. Thus an L-shaped criticalarea will have a bounding box with an area muchlarger than the actual critical area. The weightedcritical area is computed using the actual critical areashapes. We chose not to report more complex criticalarea shapes so as to avoid overwhelming the userwith data. In practice the user will navigate to asuspect net location intersected by the critical areabounding box.

4.1. Controlled Experiments

A set of controlled and production experiments wereconducted. A focused ion beam (FIB) was used in the

controlled experiments to inject bridging faults atknown locations into 13 chips and determine howwell the CAFDM software performed in identifyingthe locations. All faults were injected on the metal4layer. For the production experiment, 10 chips thatfailed wafer scan test were analyzed with CAFDMand one sent to failure analysis.

It was not possible to directly measure diagnosistime since the FIBed defect locations were knownand equipment limitations prevented automaticnavigation to the predicted locations in theproduction chip. We use the predicted fault site areaas a surrogate for search time.

The results of the controlled experiments aresummarized in Table 2. Only 9 chips are listed sinceone chip failed its scan chain test, and three chipserroneously had the FIB injected into a scan chainnode. These can be diagnosed using binary searchwith the SEM. In the table the first column identifiesthe chip. The second column lists how many of thebridged nets (nodes) appear on the FastScan stuck-atfault list, and their rank on the list. For example, forFIB3, only one of the bridged nets appears on thesuspect list at position #6. The third column lists thebridged net ranking after CAFDM. The fourthcolumn lists the critical area bounding box.

Table 2. FIB Experiment Results

FIB3

FIB4

FIB6

FIB13

FIB10

FIB7

FIB8

FIB11

Chip

one node (#6)

two nodes (#4, #12)

two nodes (#1, #2)

one node (#1)

one node (#1)

two nodes (#1, #20)

two nodes (#16, #21)

none

bridge (#1)

bridge (#1)

bridge (#1)

bridge (#1)

bridge (#1)

bridge (#1)

FastScanTM CAFDM

bridge (#1)

FIB1 one node (#1) bridge (#1)

Search Area

27 µm2

263 µm2

54 µm2

4 µm2

86 µm2

57 µm2

61 µm2

400 µm2

bridge (#1) 91 µm2

In eight chips, at least one of the bridged netsappears on the stuck-at suspect list. All of these chipswere successfully diagnosed by CAFDM, with thereal bridge being ranked #1 on the suspect list, with avery close match to actual chip behavior. In seven ofthose chips the #2 suspect was a much worse matchand would not even be considered for diagnosis. Inthe eighth chip the top two suspects had the samesmall Hamming distance. The critical area of the realbridge was much larger than the other bridge, and sothe real bridge was ranked #1. In all samples theWired-AND bridging model gave the best results.Neither of the bridged nets appeared in the stuck-atsuspect list for chip FIB6. Backconing successfullyidentified the bridge.

We are interested in how CAFDM reduces theSEM search area. The potential bridges to the stuck-at suspects for FIB3 are highlighted in Figure 4. Thearrow points to the bridge location. As can be seen,the suspect nets extend over too large an area tosearch by SEM. Figure 5 highlights the top-rankedbridged nets found by CAFDM. The cross in themiddle of the figure is the bridge location. One net isabout 3 mm long, and would take a while to searchby SEM. But since the two nets are adjacent in only asmall region, the critical area is only 263 µm2, about5 fields of view in the SEM. It is also predicted to beon metal4. So location and layer information greatlyreduce the search area.

Figure 4. FIB3 potential bridging fault nets

In the controlled experiment, CAFDM was ableto achieve all of our metrics. We assume the searchtime would be very small due to the small searcharea. However these experiments were on FIBedbridges that have low resistance, and are wellmodeled by one of our fault models. Results for realdefects are unlikely to be as good.

4.2. Production Experiments

The production experiments were conducted on10 devices that failed wafer scan test. These devicespassed all other wafer tests. Out of the 10 devices, 3fail only under maximum voltage conditions and arebeing reserved for later analysis. CAFDM analysiswas performed on the remaining 7 devices, predictinga small search area.

Figure 5. FIB3 CAFDM predictedand actual bridging fault location

Figure 6. CHIP4 potential bridging fault nets

CHIP4 was selected for failure analysis. In thisdevice two bridges were ranked as the top candidates,explaining most failing vectors while othercandidates explained no failing vectors. The bridgedlines are shown in Figure 6. The first bridge ispredicted to be on the metal2 or metal3 layers, whilethe second bridge is predicted to be on the metal1 orpoly layers. As can be seen, the search region is smallenough to perform physical failure analysis (PFA)within hours.

Figure 7. Defects observed at fault site

Figure 8. Close-up of gate-diffusion defect

Failure analysis of CHIP4 was promising, butinconclusive. A misunderstanding and deprocessingproblems resulted in some metal layers beingremoved before they could be completely inspected.Thus it could not be determined if any defect waspresent in the predicted locations on some of thepredicted layers. However as Figure 7 shows, defectswere observed in a nearby gate, with close-ups inFigures 8 and 9. These were not at the predictedlocations or on the predicted layers, but it is veryunlikely for independent defects to be near thepredicted fault site. So we believe that these defectsare associated with the observed faulty behavior. Weplan on performing failure analysis on the remainingdevices to gain a better understanding of CAFDMperformance on production defects.

Figure 9. Close-up of material observed on diffusion

5. Conclusions and Future Work

In this work we have described a computer-aidedfault to defect mapping (CAFDM) approach to defectdiagnosis, that combines physical design andelectrical test information to localize the fault andthus reduce diagnosis time. We were able to achieveour project metrics on our controlled experiments andinitial results from our production experiments arepromising. More production experiments are neededto fully evaluate the CAFDM approach.

Our experience has identified severalimprovements that need to be made to CAFDM toachieve project metrics in a production environment.One is to include the dominant bridging fault model.A recent sutdy [14] showed that 53% of all bridgingfaults behaved as dominant faults. This can also beseen in that half of the stuck-at diagnoses in the FIBexperiments identified only one of the bridged nets asa suspect. In a dominant fault, the dominant net willnot be identified as suspect. An open question iswhether more complex, and more costly models, suchas voting models, are required to achieve sufficientdiagnostic accuracy on most bridges.

Another improvement is to reduce the per-chipCAFDM diagnosis time. Most nets are small, and sohave few bridging faults that must be simulated. Butsome of the suspect nets in our production sampleshave hundreds of potential bridges, and simulating allof these can take 5-10 CPU hours. The solution weare pursuing is to modify the netlist so that thebridging behaviors look like stuck-at faults, and thestuck-at diagnosis engine can accurately ranksuspects. This has the advantage that bridging andstuck-at behaviors are considered simultaneously.The pattern fault capability of TestBench avoids theneed for netlist modification, since it can model manybridging fault behaviors.

Acknowledgments

This work was funded by International Sematechunder project DRTB002 and by an internship forZoran Stanojevic in the Design and Test TechnologyGroup, Mixed Signal Products, Texas Instruments,Inc. This work benefited from the advice and supportof Craig Force of Texas Instruments, and SagarSabade, a Texas A&M student interning at TI.

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