Deep Challenges.

7/29/2019 Deep Challenges.

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The Deep Sub-Micron ChallengeThe Deep Sub-Micron Challenge

Microscopic Problems Wiring Load Management

Noise, Crosstalk Reliability, Manufacturability

Complexity: LRC, ERC Accurate Power Prediction Accurate Delay Prediction

etc.

Everything Looks a Little Different

Macroscopic Issues Time-to-Market

Millions of Gates High-Level Abstractions Reuse & IP: Portability

Predictability

etc.

and Theres a Lot of Them!

DSM 1/DSM

?


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Dens ity Acc e s s Time

(Gb its /c m2) (ns )

DRAM 8.5 10

DRAM (Lo g ic ) 2.5 10

S RAM (Cac he ) 0.3 1.5

Density Max. Ave. Powe Clock Rate

(Mgates/cm2) (W/cm2) (GHz)

Custom 25 54 3

Std. Cell 10 27 1.5

Gate Array 5 18 1

Single-Mask GA 2.5 12.5 0.7

FPGA 0.4 4.5 0.25

Design at a CrossroadDesign at a Crossroad

Silicon technology trackingSilicon technology tracking MooresMoores LawLaw

Die Area: 2.5x2.5 cmVoltage: 0.6 - 0.9 V

Technology: 0.07 m

15 times denser

than today

2.5 times power

density

5 times clock rate

Silicon in 2010Silicon in 2010


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Design at a CrossroadDesign at a Crossroad

Silicon technology trackingSilicon technology tracking MooresMoores LawLaw

1970 1980 1990 2000 2010

Year

1 Gbits 0.15-0.2m

256 Mbits0.25-0.3m

4 Gbits0.15m

64 Mbits0.35-0.4m

16 Mbits 0.5-0.6m

1 Mbits1.0-1.2m

4 Mbits 0.7-0.8m

256 Kbits

1.6-2.4m

64 Kbits

1010

109

108

107

106

105

104

Numberofbitsperchip

MicroprocessorPower(MIPS)

1000.0

100.0

10.0

1.0

1980 1985 1990 1995 2000

Year

P7

P6

Pentium486

386

286

64 Gbits

0.08m*

Encyclopedia2 hrs CD Audio30 sec HDTV

Encyclopedia

2 hrs CD Audio30 sec HDTV

Human memoryHuman DNA

Human memoryHuman DNA

BookBook

PagePage

Courtesy of David Eaglesham, Lucent


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Power DissipationPower Dissipation

0

10

20

30

40

50

60

70

Watts/cm

2

Surpassed Hot-Plate PowerSurpassed Hot-Plate Power

Density in 0.6Density in 0.6 m CMOSm CMOS

Courtesy Intel

Pentium

(R)486

386

PentiumPro (R)

0

1

10

100

1,000

10,000

1985 1990 1995 2000 2005 2010

Icc(amps)

100-2,000amps100-2,000amps

Due to 30%Vdd scaling


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Challenges in Deep-Challenges in Deep-SubmicronSubmicron DesignDesign

qq Device scalingDevice scaling Scaling of the voltageScaling of the voltage

The leaky transistorThe leaky transistor

Short- and long-term reliabilityShort- and long-term reliabilityqq Interconnect scalingInterconnect scaling

CapacitanceCapacitance

ResistanceResistance InductanceInductance


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Transistor ScalingTransistor Scaling

(velocity-saturated devices)(velocity-saturated devices)


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DSM devices: Evolution ofDSM devices: Evolution of IIdsatdsat

Data taken from 16 papers (IBM,TI, Bell Labs, Motorola, Intel, AMD)

Demonstrates a relatively constant Idsat

from Ldrawn

of 0.25 to 0.09 m

[Sylvester, Keutzer, 98]

0.08 0.12 0.16 0.20 0.24200

300

400

500

600

700

800

200

300

400

500

600

700

800

NMOS

PMOS

Idsat

(A/m)

Drawn Channel Length (m)


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Evolution of Power DensityEvolution of Power Density

Source: Sakurai97


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Scaling the Supply VoltageScaling the Supply Voltage

0 0.05 0.1 0.15 0.20

0.05

0.1

0.15

0.2

Vin

(V)

Vout

(V)

Minimum Feature Size (micron)10

-11

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

SupplyV

oltage

(V)

Scaling forced by reliabilityScaling forced by reliability

and power considerationsand power considerations

Scaling limited by gainScaling limited by gain

and thermal noiseand thermal noise


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Projected Evolution inProjected Evolution in IIoffoff

0

2

4

6

8

10

12

250 180 130 100 70 50

Technology Node

Off-curre

nt(25C)

0

2

4

6

8

10

12

250 180 130 100 70 50

Technology Node

Off-curr

ent(25C)


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Power & Delay Dependence on VPower & Delay Dependence on VDDDD & V& VTHTH

Courtesy Sakurai97


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Power-Delay vs Energy-Delay Product


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Reduced VReduced VDDDD/V/VTT ratioratio

Reduces PredictabilityReduces Predictability

[Sakurai&Kuroda]


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DSM Reduces PredictabilityDSM Reduces Predictability

Degradation of IV characteristics of NMOS transistorDegradation of IV characteristics of NMOS transistor

due to hot-electron effects [McGaughy88]due to hot-electron effects [McGaughy88]


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Silicon-on-InsulatorSilicon-on-Insulator

ttSiSi < 50< 50 nmnmGate

Buried Oxide (BOX)

P Substrate

tBOX

tOX

OxideOxide tSi n+n+

qq Extension beyond Bulk CMOSExtension beyond Bulk CMOS

Scaling LimitScaling Limit

qq Performance ImprovementPerformance Improvement

Reduced Junction CapacitanceReduced Junction Capacitance

Absence of Reverse-Body EffectAbsence of Reverse-Body Effect

qq Soft Error Rate (SER) ImprovementSoft Error Rate (SER) Improvement

qq Reduced leakage (low-power)Reduced leakage (low-power)

qq Latch-Up EliminationLatch-Up Elimination

qq Ease of Device IsolationEase of Device Isolation

qq Potentially Reduced WaferPotentially Reduced Wafer

Fabrication CostFabrication Cost


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IBMIBM 64b64b PowerPCPowerPCqq Bulk CMOS Base DesignBulk CMOS Base Design

0.12 m0.12 m LLeffeff, 6LM (Cu), 6LM (Cu)

450 MHz, 22 W @ 1.8 V450 MHz, 22 W @ 1.8 V

qq PD/SOI TechnologyPD/SOI Technology

0.12 m0.12 m LLeffeff , 6LM (Cu), 6LM (Cu)

550 MHz, 24 W @ 1.8 V550 MHz, 24 W @ 1.8 V

(D. H. Allen et al., ISSCC, 1999)

CMOS6S2 CMOS7S CMOS7S SOICore Clock Frequency 350 MHz 450 MHz 550 MHz

L1 Cache 64KB-I + 64KB-D 128KB-I + 128KB-D 128KB-I + 128KB-D

L2 Directory N/A 104 x 16 K 104 x 16 K

Supply Voltage 2.5 V 1.8 V 1.8 V

Transistors 12 M 34 M 34 M

Die Size 162 mm2 139 mm2 139 mm2

Power 34 W 22 W 24 W

Leff(nFET) 0.18 m 0.12 m 0.12 m

TOX 5.0 nm 3.5 nm 3.5 nm

Metalization 5 Layers AL 6 Layers Cu 6 Layers Cu

Contacted M2 M4

Pitch

1.26 m 0.81 m 0.81 m


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Alternatives to planar CMOS:Alternatives to planar CMOS:

Vertical transistorsVertical transistors

qq Some early types of vertical structures discussed since 1980sSome early types of vertical structures discussed since 1980s

qq Separates performance-scaling from packing-scalingSeparates performance-scaling from packing-scaling

qq

RequireRequire

manufacturablemanufacturable

process with low parasiticsprocess with low parasitics

Gate Gate

Source

Drain


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Dual-Gate BerkeleyDual-Gate Berkeley FinFETFinFET (1999)(1999)

SiO2

Closer to planar technology Proven operation for NMOS and PMOS down to 18 nm Can be scaled down to 10 nm Suppresses short-channel effects! [Huang, IEDM99]


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Berkeley PMOS FINFET (Berkeley PMOS FINFET (LgLg = 45= 45 nmnm))

S = 69 mV/decade Highest reported PMOS Drive Current

[Huang, IEDM99]


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The Interconnect ChallengeThe Interconnect Challengeqq With increases in performance and integrationWith increases in performance and integration

density, wire parasitics gain dominancedensity, wire parasitics gain dominance

qq The wire combines capacitance, resistance, andThe wire combines capacitance, resistance, and

inductanceinductance

qq Wire parasitics impact performance, energyWire parasitics impact performance, energy

dissipation and reliabilitydissipation and reliability

transmitters receivers


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Interconnect DistributionInterconnect Distribution

10 100 1,000 10,000 100,000

Length (u)

Noofn

ets

(LogSc

ale)

Pentium Pro (R)

Pentium(R) IIPentium (MMX)

Pentium (R)

Pentium (R) II

Source

:Intel


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The Ideal Wire Scaling ModelThe Ideal Wire Scaling Model

While transistor delay

scales as 1/S!

The RC DilemmaThe RC Dilemma


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Constant Resistance ScalingConstant Resistance Scaling

Scaling would increase R (Scaling would increase R ( SS33))

historically aspect ratio has increased to compensatehistorically aspect ratio has increased to compensate


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Will Interconnect Dominate Delay?Will Interconnect Dominate Delay?

qq # logic levels decreasing# logic levels decreasing

(architecture)(architecture)

qq Min. gate size shrinkingMin. gate size shrinking

qq ParasiticsParasitics increase due toincrease due to

scalingscaling

qq Increasing RC delay withIncreasing RC delay with

chip sizechip size

delay

Year

1

0.25

0.5

88 94 00

gate delay

delay due to

sizing and buffering

interconnect delay

From Aykut Dengi

1996 ICCAD tutorial


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Or Will Its Impact Decrease?Or Will Its Impact Decrease?

0

10

20

30

40

5060

70

80

90

100110

120

0

10

20

30

40

5060

70

80

90

100110

120

2-input NAND, FO = 2, W/L = 16

0.250.180.130.1

Delay

(ps)

Process Generation (m)

Gate delayStage delay [Keutzer98]

Shorter local wire length, transistor sizing, and low-k dielectricsShorter local wire length, transistor sizing, and low-k dielectrics


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Interconnect ProjectionsInterconnect Projections

Low-k dielectricsLow-k dielectrics

qq BothBoth delay and power are reduceddelay and power are reducedby droppingby dropping

interconnect capacitanceinterconnect capacitanceqq Types of low-k materials include: inorganic (SiOTypes of low-k materials include: inorganic (SiO22),),

organic (organic (PolyimidesPolyimides) and) and aerogelsaerogels (ultra low-k)(ultra low-k)

qq The numbers below are on theThe numbers below are on the

conservative side of the NRTS roadmapconservative side of the NRTS roadmap

Generation 0.25

m

0.18

m

0.13

m

0.1

m

0.07

m

0.05

m

Dielectric

Constant

3.3 2.7 2.3 2.0 1.8 1.5

F C i GNDF C it t GND t


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From Capacitance-to-GND toFrom Capacitance-to-GND to

InterwireInterwire CapacitanceCapacitance

fringing parallel


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CrosstalkCrosstalkW S

Ca CaCv

Ground Plane

T

H

Cc Cc

Neighboring wires switch,

coupling to a quiet line

Quiet line sees a undesired

voltage spike

Crosstalk can lead to:- Logic faults (especially in dynamic circuits)

- Voltage overshoot (stress, forward-bias PN junctions)

Voltage spike, Vx Cc / Ctotal Vx is a complex function of

- Driver strength

- Fan-out capacitance

- Wiring resistance


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Delay DegradationDelay Degradation

Cc- Impact of neighboring signalactivity on switching delay

- When neighboring lines switch

in opposite direction of victim

line, delay increases

Miller EffectMiller Effect

- Both terminals of capacitor are switched in opposite directions

(0 Vdd, Vdd 0)

- Effective voltage is doubled and additional charge is needed

(from Q=CV)


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Structured and Predictable InterconnectStructured and Predictable Interconnect

S

S SV V S

G

S

SV

G

V

Example: Dense Wire Fabric (DWF) [Khatri, DAC99]Trade-off:

Cross-coupling capacitance 40x lower, 2% delay variation

Increase in area and overall capacitance


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The Impact ofThe Impact of ResistivityResistivity

CN-1 CNC2

R1 R2

C1

Tr

Vin

RN-1 RN

0 0.5 1 1.5 2 2.5 3 3 .5 4 4.5 50

0.5

1

1.5

2

2.5

t ime (n sec)

voltage(

V)

x= L/10

x = L/4

x = L/2

x= L

0 0.5 1 1.5 2 2.5 3 3 .5 4 4.5 5

0

0.5

1

1.5

2

2.5

t ime (nsec )

voltage(

V)

x= L/10

x = L/4

x = L/2

x= L

Diffused signalDiffused signal

propagationpropagation

Delay ~ LDelay ~ L22

The distributedThe distributed rcrc-line-line

U i C I t tU i C I t t


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Using Copper as InterconnectUsing Copper as Interconnect

MaterialMaterial

With cladding and other effects,

Cu ~ 2.2 mW-cm vs. 3.5 for Al(Cu)40% reduction in resistance

Yields 12% performanceimprovement over an aluminum

process in a PowerPC design

Electromigration improvement;100X longer lifetime (IBM, IEDM97)

Electromigration is a limiting

factor beyond 0.18 mm if Al isused (HP, IEDM95)

Transistor SEM


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The Global Wire ProblemThe Global Wire Problem( )outwwdoutdwwd CRCRCR693.0CR377.0T +++=

ChallengesChallenges

qq No further improvements to be expected after theNo further improvements to be expected after the

introduction of Copper (introduction of Copper (superconductingsuperconducting, optical?), optical?)

qq Design solutionsDesign solutions

Use of fat wiresUse of fat wires

Insert repeaters but might become prohibitive (power, area)Insert repeaters but might become prohibitive (power, area)

Efficient chipEfficient chip floorplanningfloorplanning

qq Towards Towards communication-basedcommunication-based design design

How to deal with latency?How to deal with latency?

Is synchronicity an absolute necessity?Is synchronicity an absolute necessity?

Architect re M st E ol e to FitArchitecture Must Evolve to Fit


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Architecture Must Evolve to FitArchitecture Must Evolve to Fit

the Landscapethe Landscape

20 Clocks

90,000

tracks

Local, parallel operationsLocal, parallel operations

High bandwidthHigh bandwidth

Low latency &Low latency &

Low powerLow power

Global operationsGlobal operations

Low bandwidthLow bandwidth

High latency &High latency &High powerHigh power

Source: Bill Dally, Stanford


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Interconnect: # of Wiring LayersInterconnect: # of Wiring Layers

# of metal layers is steadily increasing due to:

Increasing die size and device count: we need

more wires and longer wires to connecteverything

Rising need for a hierarchical wiring network;local wires with high density and global wires withlow RC

substrate

poly

M1

M2

M3

M4

M5

M6

Tins

H

WS

= 2.2

-cm

0.25 m wiring stack

Minimum Widths (Relative)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

1.0 0.8 0.6 0.35 0.25

M5

M4

M3

M2

M1

Poly

Minimum Spacing (Relative)

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

1.0 0.8 0.6 0.35 0.25

M5M4

M3

M2

M1

Poly

Resistance and the PowerResistance and the Power


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Distribution ProblemDistribution Problem

Pentium

(R)486386

Pentium

Pro (R)

0

1

10

100

1,000

10,000

1985 1990 1995 2000 2005 2010

Icc(amps)

100-3,000amps

VDD

X

I

I

R

R

VDD - V

V

V

pre

RI dropRI drop



40/45


Distribution ProblemDistribution Problem

Source: Simplex

Requires fast and accurate peak current predictionRequires fast and accurate peak current prediction

Heavily influenced by packaging technologyHeavily influenced by packaging technology

BeforeBefore AfterAfter


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InductanceInductance

qq

Transmission line effectsTransmission line effectscause overshooting andcause overshooting and non-non-

monotonic behaviormonotonic behavior

qq Wave propagation putsWave propagation puts

minimum boundminimum bound on delayon delay

and may require terminationand may require termination

qq Only to be considered whenOnly to be considered when

thethe rise and fall timesrise and fall times of theof the

signal are comparable to thesignal are comparable to the

time-of-flight of the line, andtime-of-flight of the line, andwhen thewhen the resistanceresistance of theof the

wire is small (< 5Zwire is small (< 5Z00))Clock signals in 400 MHz IBM Microprocessor

(measured using e-beam prober) [Restle98]


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Dealing with InductanceDealing with Inductance

Bus linesV

dd

GND

Inductance hard to analyze accuratelyInductance hard to analyze accurately

Structural design approaches might be more appropriateStructural design approaches might be more appropriate

DEC approach in Alpha 21264 use entireDEC approach in Alpha 21264 use entire planes of metal asplanes of metal as

referencesreferences ((VVdddd and GND) to reduce inductance by controlling theand GND) to reduce inductance by controlling the

return pathreturn path

- Loss of routing density, added metal layers reduce yield &- Loss of routing density, added metal layers reduce yield &

raise costsraise costs

Another industry approach usesAnother industry approach uses shield wiresshield wires every ~ 3 signal linesevery ~ 3 signal lines

in a dense arrayin a dense array


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Inductive Noise -Inductive Noise - LdiLdi//dtdt

PentiumPro

Pentium

486

3861.E+00

1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+061.E+07

1.E+08

1.5 0.8 0.35 0.18 0.1

di/dt

inAU

di/dt noiseincreases

Source: Intel


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Inductive Noise -Inductive Noise - LdiLdi//dtdt

CHIPSUPPLY

Bonding

Wire

Board

Wiring

Cd

Decoupling

Capacitor

+

-

qq DecouplingDecoupling

capacitance problemcapacitance problem

becoming extremebecoming extreme DEC 21164: 128DEC 21164: 128

nFnF of on-chipof on-chip

decouplingdecoupling

DEC 21264: addDEC 21264: addflip-chipflip-chip decouplingdecoupling

capacitor chipcapacitor chip

qq Mostly solvable byMostly solvable by

advances inadvances in

packagingpackagingtechnology and noveltechnology and novel

timing approachestiming approaches


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SummarySummaryqq Deep-Deep-submicronsubmicron effects impact reliability,effects impact reliability,

performance, and power dissipationperformance, and power dissipation

qq The major device challenge: low-voltage, non-leakyThe major device challenge: low-voltage, non-leaky

designdesign

qq Interconnect starts playing a dominant roleInterconnect starts playing a dominant role

capacitivecapacitive: the increasing impact of: the increasing impact of interwireinterwire capacitancecapacitance resistive: global wire delay and power distributionresistive: global wire delay and power distribution

inductive: mostly supply noise, but transmission line effectsinductive: mostly supply noise, but transmission line effects

are emergingare emerging

qq Requires a new generation of fast and accurateRequires a new generation of fast and accurateanalysis toolsanalysis tools

qq But most of all But most of all novel design methodologies andnovel design methodologies and

concepts producing predictable or insensitive designconcepts producing predictable or insensitive design

Deep Challenges.

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