Dec.pdp 1.Pdp 1 Programmed Data Processor 1.1961.102664957

8/3/2019 Dec.pdp 1.Pdp 1 Programmed Data Processor 1.1961.102664957

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PROGRAMMEDDATA PROCESSOR-1MANUAL

DIGITAL EQUIPMENTCORPORATIONMaynard Massachusetts


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Programmed Data Processor - I

Copyr igh t 1961 by Dig i ta l Equipment Corporat ion


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TABLE OF CONTENTS

I. INTRODUCTION ........................... 4Central ProcessorMemory SystemInput-Output

I I. PROGRAMMING PDP-1 .................. 6Number Systemlnstruction FormatIndirect AddressingOperating SpeedsManual Controlslnstruction List

Ill. ST ANDARD AN D OPT IONALEQUIPMENT ............................... 22

Standard EquipmentOptional Equipment

IV. PROGRAM LIBRARY ..................... 30V. APPENDIX .................................32

Abbreviated lnstruction ListNumerical lnstruction ListAlphanumeric Codes


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I. INTRODUCTIONTh e Programmed Data Processor (PDP-1) is a high speed, solidstate digital computer designed to operate with several types ofinput-output devices, with no internal machine changes. It is asingle address, single instruction, stored program computer withpowerful program features. Five-megacycle circuits, a magneticcore memory, and fully parallel processing make possible a compu-tation rate of 100,000 additions per second (about 2.5 times thespeed of most large computers in use today, and more than 100 timesthe speed of magnetic drum computers). The PDP-1 is unusually

versatile. It is easy to install, operate and maintain. Conventional110-volt power is used, neither air conditioning nor floor reinforce-ment is necessary, and preventive maintenance is provided for bybuilt-in marginal checking circuits.PDP-1 circuits are based on the designs of DEC's highly success-ful and reliable System Modules. Flip-flops and most switchesuse saturating transistors. Primary active elements are Micro-Alloy and Micro-Alloy-Diffused transistors.The entire computer occupies only 17 square feet of floor space.It consists of four equipment frames, one of which is used as theoperating station.

CENTRAL PROCESSORTh e Central Processor contains the control, arithmetic and mem-ory addressing elements and the memory buffer register. The wordlength is 18 binary digits. Instructions are carried out in multiplesof the memory cycle time of five microseconds. Add, subtract,deposit, and load, for example, are two-cycle instructions requiring10 microseconds. Multiplication, by subroutine, requires 325micro-seconds on the average. Program features include: single addressinstructions, multiple step indirect addressing and logical arith-metic commands. Console features include: flip-flop indicatorsgrouped for convenient octal reading, six program flags for auto-matic setting and computer sensing and six sense switches for man-ual setting and computer sensing.

MEMORY SYSTEMThe coincident-current, magnetic core memory holds 4096 wordsof 18 bits each. Up to eight additional memory units of the samecapacity may be readily added to the machine; a memory fieldswitch instruction built into PDP-1 will then select the correctmemory module. The read-rewrite time of the memory is fivemicroseconds, the basic computer rate. Driving currents are auto-matically adjusted to compensate for temperature variations


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A Standard DEC System Module used in PDP-1

between 50 and 110 degrees Fahrenheit. The core memory storagemay be supplemented by up to 24 magnetic tape transports.INPUT-OUTPUT

PDP -1 is designed to operate a variety of input-output devices.Standard equipment consists of a punched tape reader with a readspeed of 400 lines per second, an alphanumeric typewriter foron-line operation in both input and output and a punched tapepunch (alphanumeric or binary) with a speed of 63 lines persecond. Optional external equipment includes: compatible mag-netic tape (75 inches per second, BCD or binary) ; 16-inch cathoderay tube for graphic or tabular displays; light pen input; lineprinter (150 or 600 lines per minute); punched cards (input andoutput a t speeds of 100 cards per minute); and a real time clock.All in-out operations are performed through the In-Out Registeror through High Speed Input-Output Channels.

Of particular interest is the ease with which new, and perhapsunusual, external equipment can be added to PDP-1. Space is pro-vided for additional gates to, and buffers from, the In-Out Register.The in-out system is sufficiently simple so that little control cir-cuitry is needed for additional devices. New input-output instruc-tions can be implemented easily at the Input-Output InstructionControl Panel.The PDP-1 is also available with the optional Sequence BreakSystem. This is a 16-channel automatic interrupt feature whichpermits concurrent operation of several in-out devices. A one-channel Sequence Break System is included in the standardPDP-1.


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11. PROGRAMMING PDP-1The Central Processor of PDP-1 contains the Control Element,the Memory Buffer Register, the Arithmetic Element, and theMemory Addressing Element. The Control Element governs thecomplete operation of the computer including memory timing, in-struction performance and the initiation of input-output commands.The Arithmetic Element, which includes the Accumulator and theIn-Out Register, performs the arithmetic operations. Th e MemoryAddressing Element, which includes the Program Counter and theMemory Address Register, performs address bookkeeping andmodification.The powerful program features of PDP-1 include:

Multiple step indirect addressingBoolean operationsTwelve variations of arithmetic and logical shifting, operat-ing on 18 or 36 bitsFifteen conditional instructions (expandable by combiningto form the inclusive OR of the separate conditions)Three different subroutine calling instructionsCombinable housekeeping instructionsIndex and Index-Conditional instructionsExecute instructionLoad-immediate instructions

Six independent flip-flops, called "program flags," are availablefor use as program switches or special in-out synchronizers. Twospecial instructions, Multiply Step and Divide Step, are includedin the Instruction List. Multiply and divide subroutines usingthese instructions operate in about 325 and 440 microsecondsrespectively.NUMBER SYSTEM

The PDP -1 is a "bed point" machine using binary arithmetic.Negative numbers are represented as the 1's complement of thepositive numbers. Bit 0 is the sign bit which is ZERO for positivenumbers. Bits 1 o 17 are magnitude bits, with Bit 1being the mostsignificant and Bit 17 being the least significant.

The actual position of the binary point may be arbitrarily as-signed to best suit the problem in hand. Two common conventionsin the placement of the binary point are:Th e binary point is to the right of the least significantdigit; thus, numbers represent integers.The binary point is to the right of the sign digit; thus, thenumbers represent a fraction which lies between *I.


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P R O G R A M C O U N T E R

I

M E M O R Y A D D R E S SI. ry6 P R O G R A M

F L AG S

I N S T R U C T I O NR E G I S T E R

R E G I S T E R

ACCUMULATOR

~ 11 I I N - O U T R E G I S T E R

S W I T C H E S

TYPEWRITER T A P E P U N C HC O N T R O L A N D C O N T R O L

PDP-1 System Block DiagramThe conversion of decimal numbers into the binary system for useby the machine may be performed automatically by subroutines.Similarly the output conversion of binary numbers into decimals isdone by subroutine. Operations for floating point numbers arehandled by interpretive programming. The PDP-1 Compiler-Assembler System provides for automatic insertion of the routinesrequired to perform floating point operations and number baseconversion.

INSTRUCTION FORMATThe Bits 0 hrough 4 define the instruction code; thus there are32 possible instruction codes, not all of which are used. The instruc-tions may be divided into two classes:

Mem ory reference instructionsAugmented instructions


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In the memory reference instructions, Bi t 5 is the indirect addressbit. The instruction memory address, Y, is in Bits 6 through 17.These digits are sufficient to address 4096 words of memory.

PDP-1 I n s tr u c t i o n F o r m a t

t-

I N S T R U C T I O N M E M O R Y A D D R E S S , Y

The augmented instructions use Bits 5 through 17, to specifyvariations of the basic instruction. For example, in the shift instruc-tion, Bit 5 specifies direction of shift, Bit 6 specifies the characterof the shift (arithmetic or logical), Bits 7 and 8 enable the registers(01 = AC, 10 = 10, and 11= both) and Bits 9 through 17 specifythe number of steps.INDIRECT ADDRESSING

I I

A memory reference instruction which is to use an indirect ad-dress will have a ONE in Bit 5 of the instruction word. The originaladdress, Y, of the instruction will not be used to locate the operand,jump location, etc., of the instruction, as is the normal case. Instead,it is used to locate a memory register whose contents in Bits 6through 17 will be used as the address of the original instruction.Thus, Y is not the location of th e operand but the location of thelocation of the operand. If t he memory register containing the in-direct address also has a ONE in Bit 5, the indirect addressing pro-cedure is repeated and a third address is located. There is no limitto the number of times this process can be repeated.

E-L3Z-5

I

OPERATING SPEEDS

0 ' 1 ' 2 1 3 ' 4

Operating times of PDP-1 instructions are multiples of the mem-ory cycle of 5 microseconds. Two-cycle instructions refer twice tomemory and thus require 10 microseconds for completion. Examplesof this are add, subtract, deposit, load, etc. The jump, augmentedand combined augmented instructions need only one call on memoryand are performed in 5 microseconds.In-Out Transfer instructions that do not include the optionalwait function require 5 microseconds. If the in-out device requiresa wait time for completion, the operating time depends upon thedevice being used.

I I I I I I6 ' 7 ' 8 1 9 1 1 0 ' 1 1 1 1 2 1 1 3 1 1 4


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Each step of indirect addressing requires an additional 5 micro-seconds.MANUA L CONTROLS

The Console of PDP-1has controls and indicators for the use ofthe operator. All computer flip-flops have indicator lights on theConsole. These indicators are primarily for use when the machinehas stopped or when the machine is being operated one step at atime. While the machine is running, the brightness of an indicatorbears some relationship to the relative du ty factor of tha t par-ticular flip-flop.Three registers of toggle switches are available on the Console.These are the Data Field-Instruction Field-Address (18 bits), theTest Word (18 bits), and the Sense Switches (6 bits). The first twoare primarily used in conjunction with the operating push buttons.The Sense Switches are present for manual intervention. The use ofthese switches is determined by the program.

Operating Push ButtonsStart The computer will start. The first instructioncomes from the memory location indicated inthe Field and Address Switches.Stop The computer will come to a halt at the com-pletion of the current memory cycle.Continue The computer will resume operation startinga t the s tate indicated by the lights.

Deposit

Read In

Examine The contents of the memory register indicatedby the Field and Address Switches will bedisplayed in the Accumulator and the MemoryBuffer lights.The word selected by the Test Word Switcheswill be put in the memory location indicatedby the Field and Address Switches.The photoelectric punched tape reader willstart operating in the Read-In mode.

Operating Toggle SwitchesPower Turns all power to the computer on and off.Single Step When the Single Step Switch is on, the com-puter will halt at the completion of eachmemory cycle. This switch is particularly use-ful in debugging programs. Repeated opera-


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tion of the Continue Push Button will stepthe program one cycle at a time. T he pro-grammer is thus able to examine the s tat e ofthe machine a t each step.Single Instruction Same as Single Step except th at entire instruc-tions are stepped one a t a time, regardless ofthe number of cycles required for their com-pletion. (If Single Step and Single Instructiontoggles are both on, the mode of operation willbe single step.)Operating Indicator Lights

R u n On while the computer is executing instruc-tions.Cycle On after the completion of one or more inslruc-tion cycles with one or more to follow.Defer On immediately prior to the execution of anydeferred cycle.High Speed Cycle On while the computer is executing a highspeed channel, Input-Output Transfer instruc-tion.Break Counter 1 On while the computer is executing Cycle 1(deposit Accumulator) and Cycle 3 (depositInput-Output Register) of a sequence break.Break Counter 2 On while the computer is executing Cycle 2(deposit Program Counter) and Cycle 3 of asequence break.

PDP-1 Control Panel


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Overflow On if overflow has occurred. (Can only beturned off or cleared by executing the Skipon Zero Overflow instruction or pressingStart.)Read In On while the computer is reading or trying toread punched tape in the Read-In mode.Sequence Break On while the computer is using the SequenceBreak System.In-Out Halt On while the computer is executing a deferred

Input-Output Transfer instruction.In-Out Commands On while the computer is executing any Input-Output Transfer instruction.In-Out Sync Used for maintenance purposes only.Program Flags On after the computer has executed the SetSelected Program Flag instruction or an in-outdevice has been activated, indicating its readi-ness to be serviced. (Can only be turned off orcleared by executing the Clear Selected Pro-gram Flag instruction.)Memory Field These indicate which memory field is currentlyin use.

Register Indicator LightsProgram Counter Displays 12 bits which represent the address ofthe next instruction to be executed.Instruction Displays 5 bits which represent the basicoperation code of the instruction being exe-cuted.Memory Address Displays 12 bits which represent the address ofthe instruction being executed (after Cycle 1)or the address of the operand (after succeed-ing cycles).Memory Buffer Displays 18 bits which represent the instruc-tion being executed (operation code andaddress part after Cycle 1)or the 18-bit oper-and (after succeeding cycles).Accumulator Displays 18 bits which represent the results ofarithmetic and logical operations.In-Out Displays 18 bits which represent informationjust transferred in or out of the computer orthe results of certain arithmetic and logicaloperations.


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INSTRUCTION LISTThis list includes the titl e of t he instruction, th e normal execution

time of the instruction, i.e., the time with no indirect address, th emnemonic code of th e instruction, and th e operation code number.I n th e following list, t he c ontent s of a register a re indicated by C ( ).Thu s C( Y) means the contents of memory at Address Y; C(AC)means th e contents of t he accumulator; C ( 1 0 ) means the contentsof th e in-out register. An alphabetical an d numerical listing of t heinstructions is contained on Pag es 32 to 39 .

Memory Reference InstructionsARITHMETIC INSTRUCTIONS

Add (1 0 psec)add Y Operation Code 40The new C(AC) are the sum of C(Y) and the original C (AC). The C(Y )are unchanged. The addition is performed with 1's complement arith-metic. If the sum exceeds the capacity of the Accumulator Register, theoverflow flip-flop will be set (see Skip Group instructions) .Subtract (10 psec)su b Y Operation Code 4 2The new C (AC) are the original C (AC) minus the C (Y). The C (Y) areunchanged. The subtraction is performed using 1's complement arith-metic. If the difference exceeds the capacity of the Accumulator, the over-flow flip-flop will be set (see Skip Group instructions).Multiply St ep (10 psec)m u s Y Operation Code 54If Bit 17 of th e In-Out Register is a ONE,he C(Y) are added to C(AC).If I0 Bit 17 is a ZERO,he addition does not take place. I n either case, theC(AC) and C(10) re shifted right one place. AC Bit 0 is made ZERO bythis shift. This instruction is used in the multiply subroutine.Divide Ste p (1 0 psec)dis Y Operation Code 56The Accumulator and the In-Out Register are rotated left one place.1 0 Bit 17 receives the complement of AC Bit 0. If I0 Bit 17 is ONE, heC(Y ) are subtracted from C(AC). If I0 Bit 17 is ZERO,C(Y)+ 1 areadded to C(AC). This instruction is used in the divide subroutine.Index (1 0 psec)idx Y Operation Code 44The C (Y) are replaced by C(Y )+ 1. The C(Y) + 1 are left in the Ac-cumulator. The previous C(AC) are lost. Overflow is not indicated.Index a nd Skip if Positive (1 0 psec)i sp Y Operation Code 46The C(Y ) are replaced by C(Y )+ 1.The C(Y)+ 1 are left in the Ac-cumulator. The previous C(AC) are lost. If, after the addition, C(Y)


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+ 1 are positive, the Program Counter is advanced one extra positionand the next instruction in the sequence is skipped. Overflow is notindicated.LOGICAL INSTRUCTIONS

Logical AND (10 psec)and Y Operation Code 02The bits of C (Y) operate on the corresponding bits of the Accumulatorto form the logicalAND. The result is left in the Accumulator. T he C(Y)are unaffected by this instruction.

LOGICALND TABLEAC Bit Y Bi t Result

Exclusive OR (10 psec)xor Y Operation Code 06The bits of C(Y) operate on the corresponding bits of the Accumulatorto form the exclusiveOR . The result is left in the Accumulator. The C(Y)are unaffected by this order.

EXCLUSIVER TABLEAC Bit Y Bi t Result0 0 0

Inclusive OR (10 psec)ior Y Operation Code 04The bits of C (Y) operate on the corresponding bits of the Accumulatorto form the inclusive OR. The result is left in the Accumulator. The C (Y)are unaffected by this order.

INCLUSIVER TABLEAC Bit Y Bit Result0 0 00 1 1

GENERAL INSTRUCTIONSLoad Accumulator (10 psec)lac Y Operation Code 20The C(Y) are placed in the Accumulator. The C(Y) are unchanged. Theoriginal C (AC) are lost.Deposit Accumulator (1 0 psec)dac Y Operation Code 24The C (AC) replace the C (Y) in the memory. The C (AC) are left un-changed by this instruction. The original C (Y) are lost.


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Deposit Address'Pa rt (10 psec)dap Y Operation Code 2 6Bits 6 through 17 of the Accumulator replace the corresponding digitsof memory register Y. C (AC) are unchanged as are the contents of Bits 0through 5 of Y. The original contents of Bits 6 through 17 of Y are lost.Deposit Instruction Part (10 psec)d ip Y Operation Code 30Bits 0 hrough 5 of the Accumulator replace the corresponding digits ofmemory register Y. The Accumulator is unchanged as are Bits 6 through17 of Y. The original contents of Bits 0 hrough 5 of Y are lost.Load In-O ut Register (10 psec)lio Y Operation Code 2 2The C (Y) are placed in the In-Out Register. C(Y) are unchanged. Theoriginal C (I 0) are lost.Deposit In-Out Register (10 psec)dio Y Operation Code 32The C (10)replace the C (Y) in memory. The C (10) are unaffected by thisinstruction. The original C (Y) are lost.Deposit Zero in Memory (1 0 psec)dzm Y Operation Code 34Clears (sets equal to plus zero) the contents of register Y.Execute (5 psec plu s tim e of instruction executed)xct Y Operation Code 10The instruction located in register Y is executed. The Program Counterremains unchanged (unless a jump or sklp were executed). Execute maybe indirectly addressed, and the instruction being executed may use in-direct addressing. An xc t instruction may execute other xct commands.Jump (5 psec)jm p Y Operation Code 60The Program Counter is reset to Address Y. The next instruction tha twill be executed will be taken from Memory Register Y. The originalcontents of the Program Counter are lost.Jum p and Save Program Counter (5 psec)jsp Y Operation Code 62The contents of the Program Counter are transferred to the Accumulator.When the transfer takes place, the Program Counter holds the address ofthe instruction following the jsp. The Program Counter is then reset toAddress Y. The next instruction that will be executed will be taken fromMemory Register Y. The original C(AC) are lost.Call Subroutine (10 psec)c d Y Operation Code 16The address part of the instruction, Y, is ignored. The contents of theAccumulator are deposited in Memory Register 100. The contents of the


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Program Counter (holding he address of the instruction following the cal)are transferred to the Accumulator. The next instruction that will beexecuted is taken from Memory Register 101. This instruction requiresthat the indirect bit be ZERO. The instruction may be used as part of amaster routine to call subroutines.Ju mp and Deposit Accumulator (1 0 psec)jda Y Operation Code 17The contents of the Accumulator are deposited in Memory Register Y.The contents of the Program Counter (holding he address of the instruc-tion following the jda) are transferred to the Accumulator. The next in-struction tha t will be executed is taken from Memory Register Y + 1.This instruction requires that the indirect bit be a ONE. The instruc-tion is equivalent to the instructions dac Y, followed by jsp Y + 1.Skip if Accumulator and Y differ (1 0 psec)sad Y Operation Code 50The C(Y) are compared with the C(AC). If the two numbers are differ-ent, the Program Counter is indexed one extra position and the next in-struction in the sequence is skipped. The C(AC) and the C(Y ) are un-affected by this operation.Skip if Accumulator an d Y are the same (10 psec)sas Y Operation Code 52The C(Y) are compared with the C(AC). If the two numbers are identi-cal, the Program Counter is indexed one extra position and the next in-struction in the sequence is skipped. The C(AC) and C (Y) are unaffectedby this operation.

Augmented InstructionsLoad Accumulator with N ( 5 psec)law N Operation Code 70The number in the memory address bits of the instruction word is placedin the Accumulator. If the indirect address bit is ONE,he complement ofN (- N) is pu t in the Accumulator.Shift Group ( 5 psec)sft Operation Code 66This group of instructions will rotate or shift the Accumulator and/orthe In-Out Register. When the two registers operate combined, the In-Out Register is considered to be an 18-bit magnitude extension of theright end of the Accumulator.

Rotate is a non-arithmetic cyclic shift. That is, the two ends of theregister are logically tied together and information is rotated as thoughthe register were a ring.Shift is an arithmetic operation and is, in effect, multiplication of thenumber in the register by 2 *N, where N is the number of shifts; plus isleft and minus is right.The number of shift or rotate steps to be performed (N ) is indicatedby the number of ONE'S in Bits 9 thru 17 of the instruction word. Thus,Rotate Accumulator Right nine times is 671777. A shift or rotate of oneplace can be indicated nine different ways. The usual convention is touse the right end of the instruction word (rar 1= 671001).


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Rot ate Accumulator Righ t (5psec)rar N Operation Code 671Rotates the bits of the Accumulator right N positions, where N is thenumber of ONE'S in Bits 9-17 of the instruction word.Rot ate Accumulator Left (5 psec)ral N Operation Code 661Rotates the bits of the Accumulator left N positions, where N is thenumber of ONE'S in Bits 9-17 of the instruction word.Shift Accumulator Right (5 psec)sa r N Operation Code 675Shifts the contents of the Accumulator right N positions, where N isthe number of ONE'S in Bits 9-17 of the instruction word.Shift Accumulator Left (5 psec)sal N Operation Code 665Shifts the contents of the Accumulator left N positions, where N is thenumber of ONE'S in Bits 9-17 of the instruction word.Rotat e In-Out Register Right (5 psec)rir N Operation Code 672Rotates the bits of the In-Out Register right N positions, where N isthe number of ONE'S in Bits 9-17 of the instruction word.Rotat e In-O ut Register Left (5 psec)ril N Operation Code 662Rotates the bits of the In-Out Register left N positions, where N isthe number of ONE'S in Bits 9-17 of the instruction word.Shift In-Ou t Register Right (5 psec)sir N Operation Code 676Shifts the contents of the In-Out Register right N positions, where Nis the number of ONE'S in Bits 9-17 of the instruction word.Shift In-Ou t Register Left (5 usec)sil N Operation Code 666Shifts the contents of the In-Out Register left N positions, where N isthe number of ONE'S in Bits 9-17 of the instruction word.Rotate AC and I0 Right (5 psec)rcr N Operation Code 673Rotates the bits of the combined registers right in a single ring N posi-tions, where N is the number of ONE'S in Bits 9-17 of the instructionword.Rotate AC and I0 Left (5 psec)rcl N Operation Code 663Rotates the bits of the combined registers left in a single ring N posi-tions, where N is the number of ONE'S in Bits 9-17 of the instructionword.


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Shift AC and I0 Right (5 psec)scr N Operation Code 677Shifts the contents of the combined registers right N positions,whereN is the number of ONE'S in Bits 9-17 of the instruction word.Shift AC and I0 Left (5 psec)scl N Operation Code 667Shifts the contents of the combined registers left N positions, whereN is the number of ONE'S in Bits 9-17 of the instruction word.

Skip Group (5 psec)skp Operation Code 64This group of instructions senses the state of various flip-flops andswitches in the machine. The address portion of the instruction selectsthe particular function to be sensed. All members of this group have thesame operation code.The instructions in the Skip Group may be combined to form the in-clusive OR of the separate skips. Thus, if Address 3000 is selected, theskip would occur if the overflow flip-flop equals ZERO or if the In-OutRegister is positive. The combined instruction would still take 5 micro-seconds.The intent of any skip instruction can be reversed by making Bit 5(normally the Deferred Address Bit) equal to ONE. For example, theSkip on Zero Accumulator instruction, if deferred, becomes Do Not Skipon Zero Accumulator.Skip on ZERO Accumulator (5 psec)sza Address 100If the Accumulator is equal to plus ZERO (all bits are ZERO),he Pro-gram Counter is advanced one extra position and the next instructionin the sequence is skipped.Skip on Plus Accumulator (5 psec)spa Address 200If the sign bit of the Accumulator is ZERO,he Program Counter is ad-vanced one extra position and the next instruction in the sequence isskipped.Skip on Minus Accumulator (5 psec)sma Address 400If the sign bit of the Accumulator is ONE, the Program Counter is ad-vanced one extra position and the next instruction in the sequence isskipped.Ski p on ZER O Overflow (5 psec)szo Address 1000If the overflow flip-flop is a ZERO,he Program Counter is advanced oneextra position and the next instruction in the sequence will be skipped.The overflow flip-flop is cleared by the instruction. This flip-flop is setby an addition or subtraction that exceeds the capacity of the Accumu-lator. The overflow flip-flop is not cleared by arithmetic operationswhich do not cause an overflow. Thus, a whole series of arithmeticoperations can be checked for correctness by a single szo. The overflowflip-flop is cleared by the "Sta rt" Switch.


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Skip on Plus In-Out Register (5 pet)spi Address 2000If the sign digit of the In-Out Register is ZERO, the Program Counteris indexed one extra position and the next instruction in sequence isskipped.Skip on ZERO Switch (5 psec)szs Addresses 10, 20 . . . . .7 0If the selected Sense Switch is ZERO, the Program Counter is advancedone extra position and the next instruction in the sequence will beskipped. Address 10 senses the position of Sense Switch 1, Address 20Switch 2, etc. Address 70 senses all the switches. If 70 is selected all 6switches must be ZERO to cause the skip.Skip on ZERO Program Flag (5 psec)szf Addresses 0 to 7 inclusiveIf the selected program flag is a ZERO, the Program Counter is ad-vanced one extra position and the next instruction in the sequence willbe skipped. Address 0 is no selection. Address 1 elects Program Flag 1,etc. Address 7 selects all program flags. All flags must be ZERO to causethe skip.

Operate Group (5 psec)opr Operation Code 76This instruction group performs miscellaneous operations on variousCentral Processor Registers. The address portion of the instruction speci-

fies the action t o be performed.The instructions in the Operate Group can be combined to give theunion of the functions. The instruction opr 3200 will clear the AC, putTW to AC, and complement AC. If the number minus zero is interpretedas an instruction, the I0 is cleared, AC gets the complement of the TWswitches, all program flags are set and the computer halts.Clear In-Out Register (5 psec)cli Address 4000Clears (sets equal to plus zero) the In-Out Register.Load Accumulator from Test Word (5 psec)lat Address 2000Forms the inclusive OR of the C(AC) and the contents of the TestWord. This instruction is usually combined with Address 200 (ClearAccumulator), so th at C (AC) will equal the contents of the Test WordSwitches.Complement Accumulator (5 psec)cma Address 1000Complements (makes negative) the contents of the Accumulator.Halthlt Address 400Stops the computer.


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Clear Accumulator (5 psec)cla Address 200Clears (sets equal to plus zero) the contents of the Accumulator.Clear Selected Program F lag (5 wet)elf Address 01 to 07 inclusiveClears the selected program flag. Address 01 clears Program Flag 1,02 clears Program Flag 2, etc. Address 07 clears all program flags.Set Selected Program Flag (5 psec)stf Addresses 11 to 17 inclusiveSets the selected program flag. Address 11 sets Program Flag 1; 12 setsProgram Flag 2, etc. Address 17 sets all program flags.No Operation (5 psec)nop Address 0000The state of the computer is unaffected by this operation, and theProgram Counter continues in sequence.

In-Out Transfer Group (5 psec without in-out wait)iot Operation Code 72The variations within this group of instructions perform all the in-outcontrol and information transfer functions. If Bit 5 (normal ly the In-

direct Address bit) is a ONE, the computer will halt and wait for the com-pletion pulse from the device activated. When this device delivers itscompletion, the computer will resume operation of the instruction se-quence.

An incidental fact which may be of importance in certain scient ific orreal time control applications is that the time origin of operations follow-ing an in-out completion pulse is identical with the time of that pulse.

Most in-out opera tions require a known minimum time before com-pletion. This time may be utilized for programming. The appropriateIn-Out Transfer is given with no in-out wait (Bit 5 a ZERO and Bit 6a ONE). The instruction sequence then continues. This sequence mustinclude an iot instruction 730000 which performs nothing but the in-outwait, and the instruction must occur before the safe minimum time.A table of minimum times for all in-out devices is delivered with thecomputer: it lists minimum time before completion pulse and minimumIn-Out Register free time.

Bit 6 determines whether a completion pulse will or wil l not be re-ceived from the in-out device. When it is different than Bit 5, a comple-tion pulse will be received. When it is the same as Bit 5, a completionpulse will not be received.

In addition to the control functions of Bits 5 and 6, Bits 7 through 11are also used as control bits serving to extend greatly the power of the iotinstructions. For example, Bits 12 through 17, which are used to desig-nate a class of input or output devices such as typewriters, may befurther defined by Bits 7 through 11 as referring to Typewriter 1, 2, 3,etc., and whether or not the Sequence Break System is to be used.

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CENTRAL PROCESSOR OPTIONS

READERElW R I T E REl

PD P-1CENTRAL MACHINE

COMMUNICATION FORPERIPHERAL DEVICES

AND OPTIONS

L I G H T P E N \C O N T R O L R E A D E R P U N C H P R I N T E R P R I N T E RC O N T R O L C O N T R O L C O N T R O L

4 0 - 5 2 3 4 1 - 5 2 3

T A P E T A P ER E A D E R P U N C H P R I N T E R P R I N T E R

INPUT-OUTPUT OPTIONSD E N O T E O P T I O N T Y P E S

Y O N E O P T I O N M A Y B E C O N N E C T E D FO R A M A C H I N E

E Q U I P M E N T

PDP-1 System Configuration Diagram


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Read Punched Tape, Binaryrpb Address 0002For each In-Out Transfer instruction, three lines of punched tape areread and assembled in the In-Out Register to form a full computerword. For a line to be recognized in this mode, the eighth hole must bepunched; i.e., lines with no eighth hole will be skipped over. Theseventh hole is ignored. The pat tern of holes in the binary tape is ar-ranged so as to be easily interpreted visually in terms of machineinstruction.Read Reader Bufferrrb Address 0030When operating in the Sequence Break Mode, the rpa and rpb in-structions operate as usual but do not transfer information from thereader buffer to the I 0 Register. To accomplish the transfer, theseinstructions must be followed by an rrb instruction.Read-In ModeThis is a special mode activated by the "Read-In" switch on the con-sole. It provides a means of entering programs which neither rely onprograms in memory nor require a plug board. Pushing the "Read-In" switch starts the reader in the binary mode. The f i s t group ofthree lines, and alternate succeeding groups of three lines, are inter-preted as "Read-In" mode instructions. Even-numbered groups ofthree lines are data. The "Read-In" mode instructions must be either"deposit in-out" (dio Y) r " ump7' (jmpY).f the instruction is dioY, he next group of three binary lines will be stored in memory loca-tion Y nd the reader continues moving. If the instruction is jmp Y,the "Read-In" mode is terminated, and the computer will commenceoperation at the address of the jump instruction.

Punched Tape PunchThe standard PD P-1 punched tape punch operates at a speed of 63 linesper second. It can operate in either the alphanumeric mode or the binarymode.

Punch Punched Tap e, Alphanumericppa Address 0005For each In-Out Transfer instruction one line of tape is punched. In -Out Register Bit 17 conditions Hole 1.Bit 16 conditions Hole 2, etc.Bit 10 conditions Hole 8.Punch Punched Ta pe, Binaryppb Address 0006For each In-Out Transfer instruction one line of tape is punched. In-Out Register Bit 5 conditions Hole 1.Bit 4 conditions Hole 2, etc. Bit0 conditions Hole 6. Hole 7 is left blank. Hole 8 is always punched inthis mode.


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Alphanumeric TypewriterThe typewriter will operate in the input mode or the outpu t mode.

Type Outtyo Address 0003For each In-Out Transfer instruction one character is typed. Thecharacter is specified by th e right six bits of th e In-Out Register.Type Intyi Address 0004This operation is completely asynchronous and is therefore handleddifferently than any of the preceding in-out operations.When a typewriter key is struck, Program Flag 1 s set. At the sametime the code for the struck key is presented to gates connected to theright six bits of the In-Out Register. This information will remain atthe gate for a relatively long time by virtue of the slow mechanicalaction.A program designed to accept typed-in data would periodicallycheck the status of Program Flag 1. If a t any time Program Flag 1 sfound to be set, an In-Out Transfer instruction with Address 4 mustbe executed for information to be transferred. This In-Out Transfershould not use the optional in-out halt. The information contained inthe typewriter's coder is then read into the right six bits of the In-OutRegister. The tyi instruction automatically clears the I 0 before trans-ferring the information. The tyi instruction is usually preceded by aClear Selected Program Flag 1 nstruction.

Sequence Break ModeTwo instructions a re associated directly with th e One-Channel

Sequence Break Sy stem on the standard PDP-1.Ent er Sequence Break Modeesm Address 0055This instruction turns on th e Sequence Break System, allowingautomatic interrupts to the main sequence to occur. The contents ofthe Sequence Break flip-flops are unaffected by this instruction.Leave Sequence Break Mo deIsm Address 0054This instruction turns off the Sequence Break System, thus prevent-ing interrupts to the main sequence. Should interrupts occur while theSystem is off, the Sequence Break flip-flops will, nevertheless, continueto be set.

MiscellaneousCheck Statu scks Address 0033This instruction checks the s tatus of various in-out devices and setsI 0 Bits 0 through 4 for subsequent program interrogation as follows:


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I0 BitPositions IfONE

0 Displayed point sensed by light pen1 Punched tape reader busy2 Typewriter busy3 Typewriter key stuck4 Punched tape punch busy

OPTIONAL EQUIPMENTAutomatic Multiply and Divide (Type 1 0 )

This option replaces the Multiply Step and Divide Step instructionswith the following instructions:Multiply (14 to 25 psec)mul Y Operation Code 54The product of C(AC) and C (Y ) is formed in the AC and I 0 registers.The sign of the product is in the AC sign bit. I 0 Bit 17 also containsthe sign of the product. The magnitude of the product is the 34-bitstring from AC Bit 1 hrough I 0 Bit 16. The C ( Y ) are not affectedby this instruction.Divide (3 0 to 40 psec, except o n overflow, 12 psec)div Y Operation Code 56The dividend must be in the AC and I 0 egisters in the form indicatedin the instruction, Multiply. I 0 Bit 17 is ignored. The divisor is theC (Y). At the completion of the instruction, the C (AC) are the quotientand the C (TO) are the remainder. The sign of the remainder is the signof the dividend. If an overflow were to occur, the division does nottake place, the C ( A C ) and C ( I 0 ) are unchanged, and the overflowindicator is set. The C ( Y ) are not affected by this instruction.

Memory M odule (Type 12 )Each Memory Module consists of 4096 18-bit words. A maximum ofeight modules may be connected to the PDP-1.

Memory Field Control (Type 1 3 )This control allows for memory expansion up to 16,384 18-bit words(i.e., four 4096-word memory modules). Each memory module isdefined as consisting of two 2048-word fields. A select memory instruc-tion, jump field according to the C (Y), fd Y, selects any two fields tobe connected to the PDP-1 and jumps to a specified location in one ofthe two fields.A second instruction, change fields according to Y, cfd Y, replaces thecontents of the two 3-bit field registers with Bits 6 through 11of thecfd instruction. The Program Counter is unaffected and computationcontinues in sequence using the newly selected fields.When High Speed Channel transfers are involved, the high speedehannel specifies a 14-bit address for one of 16,384 words.


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Mem ory Field Control (Type 14)This control allows for memory expansion up to 32,768 18-bit words(i.e., eight 4096-word memory modules). Each memory module repre-sents either a 4096 word Instruction Field or a 4096 word Data Field.A select memory instruction, jump field according to the C(Y),jf d Y, selects any two fields (one Instruction Field and one DataField) to be connected to t he P DP-1 and jumps to a specified locationin the newly selected Instruction Field.A second instruction, change da ta field according to Y, cdf Y, replacesthe contents of the 3-bit Data Field Register with Bits 9 through 11of the cdf instruction. The Program Counter and the Instruction FieldRegister are unaffected, and computation continues in sequence usingthe same Instruction Field.When High Speed Channel transfers are involved, the high speedchannel specifies a 15-bit address for one of 32,768 words.

High Spee d Channel (Type 1 9 )The High Speed Channel is used to transfer blocks of words betweenmemory and an in-out device, usually a high speed device such asmagnetic tape. Such a channel is installed with the Tape ControlUnit T ype 52 or may be installed separately for special applications.As many as three High Speed Channels may be added to the PDP-1.Each of these is automatically interrogated at the completion of eachmemory cycle on a priority basis. The priority is wired and fixed.The Sequence Break System has a n over-all priority just below tha t ofthe lowest priority High Speed Channel.When wired to this channel, a device communicates directly withmemory through th e Memory Buffer Register, bypassing the I0Register. After proper initiation, data transfers proceed withoutdisturbing the main program. If the channel has a word for or needs aword from the memory, the current program sequence pauses for onememory cycle in order to serve that channel, then continues.

Sequence Break System (Type 20)An optional in-out control is available for PDP-1. This control, termedthe Sequence Break System, allows concurrent operation of severalin-out devices and the main sequence. The system has, nominally,16 automatic interrupt channels arranged in a priority chain.A break to a particular sequence may be initiated by the completionof an in-out device, the program or any external signal. If this se-quence has priority, the C(AC), C(IO), C(PC) , and the contents ofthe memory field flip-flops (if present) are stored in adjacent fixedlocations unique to that sequence. The Program Counter is reset tothe address contained in a fourth fixed location. The program is nowoperating in the new sequence. This new sequence may be broken bya higher priority sequence. A typical program loop for handling anin-out sequence would contain three to five instructions, including theappropriate iot. These are followed by load AC and load I 0 from thefixed locations and an indirect jump to location of the previous C (PC).This last instruction terminates the sequence.The Sequence Break System provides PDP-1 with much of the powerof a multiple sequence machine or of a computer having in-outsynchronizers or automatic trunks.


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Cathode Ray X-Y Point PlotterVisual C R T Display (Type 30)

The PDP-1 cathode ray tube display is useful for presentation ofgraphical or tabular d ata to the operator. For each Display instruction(730007), one point is displayed. The first 10 bits of the I 0 Register,Bits 0 through 9, are the Y coordinate of the point. Bits 0 hrough 9of the Accumulator are the X coordinate of the point.


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Information is displayed at a rate of 20,000 points per second, and theresolution is 1 part in 1024.

Cathode Ray Tube DisplayPrecision CR T Display (Type 31 )

The operation of th is 5-inch cathode ray tube display is similar to th atof the Type 30. The resolution is 1 part in 4096. It comes equippedwith mounting bezel to accept a camera or a photomultiplier device.Light Pen (Typ e 32 )

This accessory allows information to be "written" on the cathode raytube. The pen detects displayed information, and the pen output setsa program flip-flop in th e machine each time a pulse of light strikesthe pen.Ca rd Punch Control (Type 40-523)

This control allows for on-line operation of standard card punchingequipment. It contains an 80-bit buffer which is loaded from theI 0 Register, using an iot instruction for each card row punched. Thecontrol is for use with a 523 Summary Punch a t speeds of 100 cardsper minute.

Car d Reader Control (Type 41-523)This control provides for on-line operation of standard card readingequipment. It allows the read brush outputs to be directed to theI 0 Register. The control is for use with a 523 Summary Punch atspeeds of 100 cards per minute.


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Tape Transport (Type 50)This transport is compatible with IBM tape formats with a recordingdensity of 200 7-bit characters per inch and an inter-record gap ofinch. The transfer ra te is 15,000 characters per second at a tapespeed of 75 inches per second. The method of recording is non-return-to-zero. A maximum of 24 tape transports may be connected tothe PDP-1.

Programmed Tape Con trol U nit ('Type 51)This control transfers information between the computer and the tapeone character at a time. All transfer operations, including timing,error checking and assembly of characters into computer words areperformed by routines. The Type 51 allows a choice of tape format,including the standard IBM tape format described under TapeTransport (Type 50).

Automatic Tape Control Unit (Type 5 2 )This control automatically transfers information between the com-puter memory and the tape in variable-length blocks of characters.It allows computation to continue while the transfer is in process byusing the High Speed Channel, which is part of th e control unit.Special features include scatter-read and gather-write; automatic,bit-by-bit read-compare with core memory; automatic parity errordetection while reading and writing; and rapid tape searching throughits ability t o skip a pre-selected number of blocks. Tape format isstandard IBM as described under Tape Transport (Type 50).Programmed Line Printer and Control (Type 61)This is an on-line printing sta tion capable of operating a t 150 lines perminute (120 columns per line with 64 characters per column). Alltransfer operations, formatting and control functions are underprogram control.Automatic Line Printer and Control (Type 6 2 )

This is an on-line printing station capable of operating a t 600 lines perminute (120 columns per line with 64 characters per column). A simpleone-line buffer is used. T he appropriate iot instruction is repeated tofill the buffer. Th e order to print is then given. Following the comple-tion of the line print, the printer returns a completion pulse andspaces the paper.

Real Time C lockA special input register may be connected to operate as a real timeclock. Th is is a counting register operated by a crystal controlledoscillator.Th e state of this counter may be read a t any time by the appropriateIn-Out Transfer instruction. The computer stops only long enough toprovide synchronization with the clock oscillator, then resumes opera-tion in phase with it.


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The Basic Program Library for PDP-1 is designed to provide thenucleus of a growing system of programs and subroutines. Amongthe programs in use are:DECAL

Digital Equipment Compiler, Assembler and Linking Loader isan integrated program for PDP-1 incorporating in one system allof the essential features of advanced compilers, assemblers andloaders. The outstanding features of DECAL are:Open-Ended Programming System. DECAL can be modifiedwithout a detailed understanding of its internal operation bymeans of a recursive definition facility based on a skeleton com-piler with a basic set of logical capabilities. The skeleton compilercan act as a bootstrap for implementing additional featuresor deleting or changing existing facilities.Efficient Us e of Storage Capacity. All available memory spacewill be used before DECAL runs out of space. This is accom-plished by means of a single table tha t meets all of the storageneeds of DECAL. When any feature of DECAL is removed, allof the associated space is again made available.Efficient U se of T im e. DECAL processing takes full advantageof the speeds of the standard PDP-1 input-output equipment(400 lines per second reader and 63 lines per second punch).One Pass Compiler-Assembler. The symbolic tape (usually pre-pared off-line) is only read one time. It is not stored in memory.A relocatable tape ready for the linking loader is punched as thesymbolic tape is read.Eficient Object Program. Since DECAL allows compiler andassembler statements to be freely intermixed a t the discretion ofthe programmer, the object program can be as efficient as desired.Variable Length Symbols. Symbol lengths are not restrictive andcan be hundreds of characters long if necessary.Program Integration and Relocation. At load time, individualroutines and subroutines can be loaded in any order. All cross-referencing is done automatically, and the resulting program isarranged compactly starting at any specified origin. The namesof subroutines required at run time and not yet loaded arelisted on the typewriter so that they may be subsequentlyloaded.Use of A LG OL. DECAL includes that part of ALGOL whichis compatible with the PDP-1 Computer. Compiler (algebraic)


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and assembler statements can be written taking full advantageof the ALGOL reference language due to the unique characterset used by the PDP-1.a Recursively Defined Macro Instructions. Full use of such complexitems as recursively defined macro instructions can be madewhen writing DECAL assembler statements.a Use of Arbitrary Languages. Arbitrary reference languages canbe defined and incorporated into DECAL to handle specialproblems.a Use of Floating Po int S ystems. DECAL-compatible, singleand double precision floating point systems can be incorporated.a Generalized subscripting, indexing and address arithmetic facilitiescan be incorporated.

OTHER PROGRAMSFRAP Assembly Program is a basic assembler designed to oper-ate with a very minimum amount of internal storage.Standard Function Generator Subroutines for single precisionfixed point arithmetic. These include: sine, cosine, arctangent,square root, exponential and logarithmic subroutines.Single Precision Floating Point Package for arithmetic using an18-bit fraction and an 18-bit exponent. The package includesstandard funclion generator subroutines.Double Precision Floating Point Package for arithmetic using a36-bit fraction and an 18-bit exponent. The package includesstandard function generator subroutines.Basic Double Precision Fixed Point Subroutines including addi-tion, subtraction, multiplication and division.Utility Routine Package including a wide range of input-outputsubroutines and debugging aids.


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V. APPENDIXABBREVIATED INSTRUCTION LIST

Basic InstructionsInstruction Code # Explanation Oper. Time Page Ref

( P e e )add Y 40 Add C ( Y ) to C(AC) 10 12and Y 02 Logical AND C ( Y ) withC(AC) 10 13cal Y 16 Equals jda 100 10 14dac Y 24 Put C(AC) in Y 10 13dap Y 26 Pu t contents of addresspart of AC in Y 10 14dio Y 32 Put C ( I 0 ) in Y 10 14dip Y 30 Pu t contents of instruc-tion part of AC in Y 10 14dis Y 56 Divide step 10 12dzm Y 34 Make C (Y ) zero 10 14idx Y 44 Index (add one) C (Y ) ,leave in Y & AC 10 12ior Y 04 Inclusive OR C(Y) withC (A C ) 10 13iot Y 72 In-out transfer, see below 19isp Y 46 Index and skip if resultis positive 10 13jda Y 17 Equals dac Y and jsp Y +1 10 19jfd Y 12 Jump memory field according

to C ( Y ) 10 26jmp Y 60 Take next instructionfrom Y 5 14~ S P 62 Jump to Y and saveprogram counter in AC 5 14lac Y 20 Load the AC with C ( Y ) 10 13law N 70 Load the AC with thenumber N 5 15


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Basic Instructions (Continued)Instruction Code # Explanation Oper. Time Page Ref.

(~sec)law -N Load the AC with thenumber -Nlio Ymus Yoprsad Y

Load I0 with C (Y)Multiply stepOperate, see belowSkip next instructionif C(AC) # C(Y)

sas Y Skip next instructionif C(AC) = C (Y)sf tskpsub Y

Shif t, see belowSkip, see belowSubtract C (Y) fromc AC)

xct Yxor Y

Perform instruction in YExclusive OR C (Y )with C(AC)

Operate Groupclaclf

760200 Clear AC760001-7 Clear selected ProgramFlag

clicmahltla t

764000 Clear I0761000 Complement AC760400 Halt762200 Load AC from TestWord switches760000 No operationoP

stf 760011-7 Set selected Program Flag


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In-Out Transfer GroupInstruction Code #

cdf 720x74cfd 72XX74cks 730033dpy 730007esm 720055Ism 720054ppa 730005

ppb 730006rpa 730001

rpb 730002rr b 720030tyi 720004

tyo 730003

Explanation Oper. Time Page Ref.(wee)

Change data field 5 26Change fields 5 25Check status 5 24Display one point on CR T 50 27Enter Sequence Break Mode 5 24Leave Sequence Break Mode 5 24Punch punched tapealphanumericPunch punched tape binary 23Read punched tapealphanumericRead punched tape binary 23Read Reader Buffer 5 23Read typewriter inputswitches 5 24Type out 24

Skip Groupsma 640400 Skip on minus AC 5 17spa 640200 Skip on plus AC 5 17spi 642000 Skip on plus I 0 5 18sza 640100 Skip on ZERO ( +0) AC 5 17szf 64000F Skip on ZERO flag(F = flag # ) 5 18szo 641000 Skip on ZERO overflow(and clear overflow) 5 17szs 6400SO Skip on ZERO senseswitch (S = switch #) 5 18


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Shift/Rotate GroupInstruction Code #

ral 661rar 671rcl 663

rcr 673ril 662rir 672sal 665sar 675scl 667

scr 677

sil 666sir 676

Explanat ion Oper . Tim e Page Ref .( ~ s e c )Rotate AC left 5 16Rota te AC right 5 16Rotate combined AC &I0 left 5 16Rotate combined AC &I0 right 5 16Rotate I0 left 5 16Rotate I0 right 5 16Shift AC left 5 16Shift AC right 5 16Shift combined AC & I0left 5 17Shift combined AC & I0right 5 17Shift I0 left 5 16Shift I0 right 5 16


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Code

NUMERICAL INSTRUCTION LISTInstruction

*

andiorxorxc tjfd*

caljdalaclioda cdapdipdiodzm*

Code Instructionaddsu bidx~ S Psadsasmusdisjmp~ S PskpShiftlawlawiot

*

* Spare code, computer will halt.


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ALPHANUMERIC CODES

Charactera Ab Bc Cd De Ef Fg Gh Hi Ij Jk K1 Lm Mn N0 0

P ps Qr Rs St Tu Uv vw Wx XY Yz z

FIO-DECCode6162

ConciseCode6162636465


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Alphanumeric Codes (Continued)Character FIO-DEC Concise

Code Code0 + (right arrow) 20 201 " (double quotes) 01 012 ' (single quote) 02 023 - (not) 203 034 3 (implies) 04 045 V (01) 205 056 A (and) 206 067 < (less than) 07 078 > (greater than) 10 109 7' (up arrow) 211 11

- (non-spacingoverstrike andvertical) 256 56- + (minus and plus) 54 54

(non-spacingmiddle dotand underline) 40 40-

> 233 33. X (period andmultiply) 73 731 221 21Lower CaseUpper CaseSpace~ a c k s ~ a c eTab


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DEC TECHNICAL BULLETINSNOTE: DEC digital circuit packages are being renamed "Modules." As newbulletins are published, the two basic product lines will be referred to as"Laboratory Modules" instead of "Digital Test Equipment" and as "SystemModules" rather than "System Building Blocks."

D I G I T A L M O D U LE S (A-702)- hort form catalog listing DEC'scomplete product line.DEC 10 Megacycle Building Blocks (A-710) -describes new 5000Series Digital Test Equipment and 6000 Series System BuildingBlocks.Expanded 100 Series DEC Digital Test Equipment (B-100) -de-scribes DEC's 5 megacycle patchcord units.New 3000 Series DEC Digital Test Equipment (B-3000)-describesDEC's 500 kilocycle patchcord units.Expanded 1000 Series DEC System Building Blocks (C-1000A)-describes DEC's 5 megacycle plug-in units.Ne w 4000 Series DEC System B uilding Blocks (C-4000A)-describesDEC's 500 kilocycle plug-in units.DEC Basic Logic K it (E-150) -describes a basic selection of DECDigital Test Equipment and Accessories which can be used toperform a variety of logical operations.DE C Programmed Data Processor (F-11A) -describes DEC's PD P-1high-speed, solid state, general purpose computer.DEC Memory Tester Ty pe 1512 (F-1512A)- escribes DEC's 1500Series testers for coincident current core memories.DEC Memory Tester Typ e 1514 (F-1514)- escribes DEC's 1500Series testers for word address and coincident current core mem-ories.DE C Automatic Memory Core Tester Ty pe 2101 (F-2101) describesDEC's automatic tester for ferrite magnetic memory cores.DE C M emory Exerciser T yp e 2201 (F-2201) -describes DEC'sexercisers for coincident current core memory systems.

Copies of the above bulletins are available on request from theDEC Sales Department, 146 Main Street, Maynard, Massachu-setts, or 8820 Sepulveda Boulevard, Los Angeles 45, California.

Dec.pdp 1.Pdp 1 Programmed Data Processor 1.1961.102664957

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