Dec 2010VLSI Interconnects 1 Instructed by Shmuel Wimer Eng. School, Bar-Ilan University Credits:...
-
Upload
bonnie-garrett -
Category
Documents
-
view
215 -
download
0
Transcript of Dec 2010VLSI Interconnects 1 Instructed by Shmuel Wimer Eng. School, Bar-Ilan University Credits:...
Dec 2010 VLSI Interconnects 1
VLSI Interconnects
Instructed by Shmuel WimerEng. School, Bar-Ilan University
Credits: David HarrisHarvey Mudd College
(Some material copied/taken/adapted from Harris’ lecture notes)
Dec 2010 VLSI Interconnects 2
Outline Introduction
Wire Resistance
Wire Capacitance
Wire RC Delay
Crosstalk
Wire Engineering
Repeaters
Scaling
Dec 2010 VLSI Interconnects 3
Introduction
Chips are mostly made of wires called interconnect Alternating layers run orthogonally
Dec 2010 VLSI Interconnects 4
Transistors are little things under the wires Many layers of wires
Dec 2010 VLSI Interconnects 5
Wires are as important as transistors– Speed– Power– Noise
Dec 2010 VLSI Interconnects 6
Wire Geometry Pitch = w + s Aspect ratio: AR = t/w
– Old processes had AR << 1– Modern processes have AR 2
• Pack in many skinny wires
l
w s
t
h
Dec 2010 VLSI Interconnects 7
Layer Stack
Modern processes use 6-10+ metal layers
Example: Intel 180 nm process
M1: thin, narrow (< 3)
– High density cells
M2-M4: thicker
– For longer wires
M5-M6: thickest
– For VDD, GND, clk
6 1720 860 860 2.0
5 1600 800 800 2.0
4 1080 540 540 2.0
3 700 320 320 2.2
2 700 320 320 2.2
Substrate
1 480 250 250 1.9
Layer T(nm) ARW(nm) S (nm)
Dec 2010 VLSI Interconnects 8
Wire Resistance
= resistivity (*m)
R = sheet resistance (/)
is a dimensionless unit(!) Count number of squares
– R = R * (# of squares)
l lR R
t w w
l
w
t
1 Rectangular BlockR = R (L/W)
4 Rectangular BlocksR = R (2L/2W) = R (L/W)
t
l
w w
l
Dec 2010 VLSI Interconnects 9
Choice of Metals
Until 180 nm generation, most wires were aluminum Modern processes use copper
– Cu atoms diffuse into silicon and damage FETs– Must be surrounded by a diffusion barrier
Metal Bulk resistivity (*cm)
Silver (Ag) 1.6
Copper (Cu) 1.7
Gold (Au) 2.2
Aluminum (Al) 2.8
Tungsten (W) 5.3
Molybdenum (Mo) 5.3
Dec 2010 VLSI Interconnects 10
Sheet Resistance Typical sheet resistances in 180 nm process
Layer Sheet Resistance (/)
Diffusion (silicided) 3-10
Diffusion (no silicide) 50-200
Polysilicon (silicided) 3-10
Polysilicon (no silicide) 50-400
Metal1 0.08
Metal2 0.05
Metal3 0.05
Metal4 0.03
Metal5 0.02
Metal6 0.02
Dec 2010 VLSI Interconnects 11
Contacts Resistance
Contacts and vias also have 2-20 Use many contacts for lower R
– Many small contacts for current crowding around periphery
Dec 2010 VLSI Interconnects 12
Wire Capacitance Wire has capacitance per unit length
– To neighbors– To layers above and below
Ctotal = Ctop + Cbot + 2Cadj
layer n+1
layer n
layer n-1
Cadj
Ctop
Cbot
ws
t
h1
h2
Dec 2010 VLSI Interconnects 13
Capacitance Trends
Parallel plate equation: C = A/d– Wires are not parallel plates, but obey trends– Increasing area (W, t) increases capacitance– Increasing distance (s, h) decreases capacitance
Dielectric constant
– = k0
0 = 8.85 x 10-14 F/cm
k = 3.9 for SiO2
Processes are starting to use low-k dielectrics– k 3 (or less) as dielectrics use air pockets
Dec 2010 VLSI Interconnects 14
M2 Capacitance Data Typical wires have ~ 0.2 fF/m
– Compare to 2 fF/m for gate capacitance
0
50
100
150
200
250
300
350
400
0 500 1000 1500 2000
Cto
tal (
aF/
m)
w (nm)
M1, M3 planes
Isolated
s = 320
s = 480
s = 640
s= 8
s = 320
s = 480
s = 640
s= 8
Capacitance increases with metal planes above and below
Capacitance decreases with spacing
Dec 2010 VLSI Interconnects 15
Diffusion & Polysilicon
Diffusion capacitance is very high (about 2 fF/m)
– Comparable to gate capacitance
– Diffusion also has high resistance
– Avoid using diffusion (and polysilicon) runners for
wires!
Polysilicon has lower C but high R
– Use for transistor gates
– Occasionally for very short wires between gates
Dec 2010 VLSI Interconnects 16
Lumped Element Models Wires are a distributed system
– Approximate with lumped element models
3-segment -model is accurate to 3% in simulation
C
R
C/N
R/N
C/N
R/N
C/N
R/N
C/N
R/N
R
C
L-model
R
C/2 C/2
R/2 R/2
C
N segments
-model T-model
Dec 2010 VLSI Interconnects 17
Dec 2010 VLSI Interconnects 18
Dec 2010 VLSI Interconnects 19
RC Example
Metal2 wire in 180 nm process– 5 mm long– 0.32 m wide
Construct a 3-segment -model
– R = 0.05 / => R = 781
– Cpermicron = 0.2 fF/m => C = 1 pF
260
167 fF 167 fF
260
167 fF 167 fF
260
167 fF 167 fF
Dec 2010 VLSI Interconnects 20
Dec 2010 VLSI Interconnects 21
Wire RC Delay Example
Estimate the delay of a 10x inverter driving a 2x inverter at the end of the 5mm wire from the previous example– R = 2.5 k*m for gates– Unit inverter: 0.36 m nMOS, 0.72 m pMOS
– tpd = 1.1 ns
781
500 fF 500 fF
Wire
4 fF
LoadDriver
690
Dec 2010 VLSI Interconnects 22
Crosstalk
A capacitor does not like to change its voltage instantaneously
A wire has high capacitance to its neighbor.
– When the neighbor switches from 1→ 0 or 0→ 1, the wire tends to switch too.
– Called capacitive coupling or crosstalk
Crosstalk effects
– Noise on non switching wires
– Increased delay on switching wires
Dec 2010 VLSI Interconnects 23
Miller Effect Assume layers above and below on average are quiet
– Second terminal of capacitor can be ignored
– Model as Cgnd = Ctop + Cbot
Effective Cadj depends on behavior of neighbors
– Miller effect
B V Ceff(A) MCF
Constant VDD Cgnd + Cadj 1
Switching with A
0 Cgnd 0
Switching opposite A
2VDD Cgnd + 2 Cadj 2
A BC
adjCgnd
Cgnd
Delay and power increase
Dec 2010 VLSI Interconnects 24
Crosstalk Noise
Crosstalk causes noise on non switching wires If victim is floating:
– model as capacitive voltage divider
adj
gnd-v adaggresvictim o
js r
CV
C CV
Cadj
Cgnd-v
Aggressor
Victim
Vaggressor
Vvictim
Dec 2010 VLSI Interconnects 25
Driven Victims
Usually victim is driven by a gate that fights noise– Noise depends on relative resistances– Victim driver is in linear region, agg. in saturation
– If sizes are same, Raggressor = 2-4 x Rvictim
adj
gnd-v adaggressor
jvictim
1
1
CV
C C kV
aggressor gnd-aggresso a adj
gndvict -im victim j
r
v ad
C C
CR
Rk
C
Cadj
Cgnd-v
Aggressor
Victim
Vaggressor
Vvictim
Raggressor
Rvictim
Cgnd-a
Dec 2010 VLSI Interconnects 26
Coupling Waveforms
Simulated coupling for Cadj = Cvictim
Aggressor
Victim (undriven): 50%
Victim (half size driver): 16%
Victim (equal size driver): 8%
Victim (double size driver): 4%
t (ps)
0 200 400 600 800 1000 1200 1400 1800 2000
0
0.3
0.6
0.9
1.2
1.5
1.8
Dec 2010 VLSI Interconnects 27
Noise Implications
So what if we have noise? If the noise is less than the noise margin, nothing
happens Static CMOS logic will eventually settle to correct
output even if disturbed by large noise spikes– But glitches cause extra delay– Also cause extra power from false transitions
Dynamic logic never recovers from glitches Memories and other sensitive circuits also can
produce the wrong answer
Dec 2010 VLSI Interconnects 28
Wire Engineering
Dec 2010 VLSI Interconnects 29
Goal: achieve delay, area, power goals with acceptable noise
Degrees of freedom:– Width – Spacing– Layer– Shielding
vdd a0
a1gnd a
2vdd b
0a
1a
2b
2vdd a
0a
1gnd a
2a
3vdd gnd a
0b
1
Dec 2010 VLSI Interconnects 30
Repeaters R and C are proportional to l RC delay is proportional to l2
– Unacceptably great for long wires Break long wires into N shorter segments
– Drive each one with an inverter or buffer
Wire Length: l
Driver Receiver
l/N
Driver
Segment
Repeater
l/N
Repeater
l/N
ReceiverRepeater
N Segments
Dec 2010 VLSI Interconnects 31
Repeater Design How many repeaters should we use? How large should each one be? Equivalent Circuit
– Wire length l
• Wire Capacitance Cw*l, Resistance Rw*l
– Inverter width W (nMOS = W, pMOS = 2W)• Gate Capacitance C’*W, Resistance R/W
R/W C'WCwl/2N Cwl/2N
Rwl/N
Dec 2010 VLSI Interconnects 32
Dec 2010 VLSI Interconnects 33
w/o repeater k=1
Showing that repeater insertion pays
2 2 2 2
2 2 2 2
2
1.21 0.16 0.56 0.49
0 0.16 0.65 0.49
0 0.4 0.7 0.09
o o i i i i o o i i o o
i i o o i i o o
i i o o o o i i
R C RC R C R C RC R C
R C R C RC R C
RC R C R C RC
small
Dec 2010 VLSI Interconnects 34
Under what condition repeater insertion should take place?
Dec 2010 VLSI Interconnects 35
Dec 2010 VLSI Interconnects 36
Dec 2010 VLSI Interconnects 37
Dec 2010 VLSI Interconnects 38
Cascaded driver with non-repeated interconnect
Non-repeated interconnect
The method is useful when Rtr is dominant and Cint is large
39
v
u , qu , q
, : driver to receiver delay. Root required time: min , .i i ii
d v u T q d v u
Optimal Buffer Insertion
buffer insertions
: max min , by buffer insertion at internal nodes.i iiq d v uProblem 1
buffer insertions
: max min , , s.t. power and area constraints.i iiq d v uProblem 2
?
?
?
?
Buffer reduces load delay but adds internal delay, power and area.
? ?
?
40
Delay Model
- nodes along path from root to node
- nodes of sub-tree rooted at node
- resistance along common paths
- capacitance of sub-tree
jkl j k l
jk j T k
k k
T k k
R R
L C
, i ji j j jj j i
d v u R C R L
R3
C1
R2
R6
R5
R4
R7
C6
C5
C4
C7
R1
C2
C3
01
3
2
4
5
6
7
41
Bottom-Up Solution
without buffer
1
2K K K K K K
K K K
T T R L R C
L L C
min ,K M N
K M N
T T T
L L L
RK
CK
K
(T’K , L’K)
RM
CM
M
sub-tree
(TM , LM)
RN
CN
N
sub-tree
(TN , LN)
with buffer
1
2K K buffer buffer K K buffer K K
K buffer K
T T D R L R C R C
L C C
(TK , LK)
Dec 2010 VLSI Interconnects 42
Scaling
Dec 2010 VLSI Interconnects 43
Dec 2010 VLSI Interconnects 44
Dec 2010 VLSI Interconnects 45
Dec 2010 VLSI Interconnects 46
Scaling