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Army Institute of Technology, Pune

Department of Electronics & Telecommunication Engg.

Teaching Plan ( June 2013 to 0ct 2013) S.E (E&TC) Semester-I

Name of faculty: Miss. Dhanashree V. Patil

DIGITAL ELECTRONICS (04185)

Teaching Scheme: Examination Scheme:Lectures/Week: 4 Hrs Theory Paper: 50 Marks

Theory online: 50

Sr.No. Name of Topic

Date ofConducti

on

No. ofLecture

sUNIT -I

08

1. Introduction to DE, logic families, Classification ofICs

2. Characteristics of digital ICs-Speed of operation3. TTL logic. Operation of TTL NAND gate4. Active pull up, wired AND, open collector output,

unconnected inputs.5. Tri-State logic. CMOS logic CMOS inverter.6. NAND, NOR gates, unconnected inputs, wired logic7. Drain output. Interfacing CMOS and TTL.8. Comparison table of Characteristics of TTL, CMOS,

ECL, RTL, I2L, DCTL.UNIT -II

08

9. Standard representations for logic functions, k map

representation of logic functions (SOP m POS forms)10. minimization of logical functions for min-terms and

max-terms (upto 4 variables)11. dont care conditions, Design Examples12. Adders and their use as subtractions13. Look ahead carry, ALU, Digital Comparator, Parity

generators14. Multiplexers

15Demultiplexers and decoders

16 Problems and Quine McCluskey methodUNIT-III

08

15. 1 Bit Memory Cell, Clocked SR, JK Flip Flop16. D and T flip-flops, with use of preset and clear terminals17. Excitation Table for flip flops18. Conversion of flip flops19. Registers, Shift registers20. Counters (ring counters, twisted ring counters)21. Sequence Generators, ripple counters

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22. up/down counters, synchronous counters, Clock Skew,

Clock jitterSr.No. Name of Topic

Date ofConducti

on

No. ofLecture

sUNIT-IV

08

23. State diagram, State table24.

State reduction, State assignment25. Problems26. Mealy and Moore machines representation27. Implementation28. finite state machine implementation29. Sequence detector30. Problems

UNIT-V

07

31. Architecture of PLDs32. Study of PROM, PAL, PLA33. Designing combinational circuits using PLDs.

34. General Architecture of FPGA and CPLD35. Memory organization and operation36. expanding memory size, Classification and

characteristics of memories37. RAM, ROM, EPROM, EEPROM, NVRAM, SRAM,

DRAMUNIT-VI

07

39. Library, Entity, Architecture40. Modeling styles, Data objects41. Concurrent and sequential statements, Design examples42. VHDL code for basic combinational and sequential

circuits43. Examples44. Attributes45. Examples

Total Lecturers=46Hours

Dhanashree PatilSubject In

charge

Text Books:

1. R.P. Jain , Modern digital electronics , 3rd edition , 12 threprint TMH Publication.

2. Stephen Brown, Fundamentals of digital logic design with VHDL 1stedition, TMH

Publication.

Reference Books:

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1. A. Anand Kumar, Fundamentals of digital circuits 1stedition, PHIpublication, 20012. Wakerly Pearon, Digital Design: Principles and Practices, 3rdedition,4threprint, PearonEducation, 20043. J. Bhaskar, VHDL Primer 3rd Edition.PHI Publication.4. Mark Bach, Complete Digital Design, Tata MCGraw Hill, 2005.

5. Volnei Pedroni, Digital: Electronics and Design with VHDL, Elsevier