Ddr Routing Guidelines

DDR2 System Design Guide, Revision 0.2DL-0265 Rambus Confidential Page 4-1

Chapter 4 PCB Design

4.1 Stackup and Thickness

The DDR2 channel can be implemented with microstrip or stripline traces. For a microstrip implementa-

tion, the outer two layers of the PCB are used for routing the signal and clock traces. For a stripline imple-

mentation, the channel’s high-speed traces are routed on internal signal layers sandwiched between ground

planes. This construction improves impedance control and reduces crosstalk for better electrical perform-

ance over the microstrip layout. Since each routing layer’s characteristics differ from one another, the

DDR2 high-speed signals, ideally, should be routed on as few routing layers as possible. In addition, to

simplify layout, one structure type (microstrip or stripline) should be used for the DDR2 high-speed

signals since microstrip’s and stripline’s trace propagation delay (ns/inch) differs.

4.1.1 Reference Plane Considerations

DDR2 drivers pull current through ground and the 1.8 v power planes (VDDIO and VDDQ). An ideal

stackup would place the ground or 1.8 v plane as the reference plane for the DDR2 high-speed signals. For

a microstrip structure with DDR2 signals, the adjacent plane should be either the 1.8 v or the ground plane.

In the standard stripline structure (one signal layer between two power planes), at least one of the two

surrounding planes should be a ground or 1.8 v plane. If the DDR2 signal layer is not equidistant from both

planes of the stripline structure, the reference plane (ground or 1.8 v plane) should be the closer plane;

making it the primary reference plane. As for a dual stripline structure, the surrounding planes should be

ground and/or 1.8 v planes.

Figure 4-1: PCB Stackups for Microstrip DDR2 Signal Routing

DDR2 signal layer

VDDQ or Ground plane/island-L2

VDDQ or Ground plane/island-L(n-1)

DDR2 signal layer-Ln

Board Stackup for Microstrip Routing of DDR2 Signals

..

DDR2 System Design Guide, Revision 0.2Page 4-2 Rambus Confidential DL-0265

Figure 4-2: PCB Stackups for Stripline DDR2 Signal Routing

Figure 4-1 and Figure 4-2 show example stackups for both microstrip and stripline PCBs. For any of the

DDR2 reference planes, if the entire plane is not available, it is acceptable to use an island that covers only

the DDR2 signal area of the PCB. If an island is used, the island must extend past all high-speed DDR2

signals on the adjacent layer(s) by a distance that is at least twice the dielectric thickness.

4.1.2 Microstrip Structure

Figure 4-1 example:

• DDR2 signals routed on outer microstrip layers.

• Power distribution primarily on internal plane layers: L2, L(n-1) for power distribution

(VDDQ, VDDIO supplies, and ground). Planes should use 35 �m (1 oz.) copper thickness

if the planes must transport large currents. External layers, L1 and Ln, may be used addi-

tionally for power distribution.

• Finished outer pre-preg thickness should be less than 150 �m for impedance and crosstalk

control.

4.1.3 Stripline Structures

Figure 4-2 example:

• DDR2 signals are routed on inner stripline layers.

• Power distribution on internal plane layers: Lx, L(x+2)/L(x+3) for power distribution, that

is, VDDIO, VDDQ supplies and ground. Planes should use 35 �m (1 oz.) copper thickness

if the plane must transport large currents.

• Inner core thickness should be less than 150 �m for impedance and crosstalk control.

Other signals

VDDQ or Ground plane/island-Lx

DDR2 signal layer-L(x+1)

Other signals

VDDQ or Ground

Dual-Stripline Board Stackupfor Routing of DDR2 Signals


Other signals

VDDQ or Ground plane/ island-Lx

Other signals

VDDQ or Ground plane/ island-L(x+2)

Stripline Board Stackupfor Routing of DDR2 Signals


.

.

.

.plane/ island-L(x+3)

PCB Design


4.2 Dielectric Material

Standard FR-4 materials are recommended with the following specifications across system environmental

operating conditions such as humidity and temperature:

• �r range of 4.1 to 4.6 at 1 GHz.

• Loss tangent not to exceed 0.025 at 1 GHz.

4.3 Impedance

• Nominal impedance

� TBD � differential impedance for DDR2 clock signals ("CK", "CKN").

� TBD ��impedance for DDR2 high-speed signals.

• Impedance tolerance of ±TBD%

� Applies to high-speed DDR2 signals on all applicable layers.

4.3.1 Impedance Test Coupons

The following test coupons should be included in the PCB layout. Each coupon must be at least 150 mm in

length.

� Differential coupon designed to match TBD � differential impedance of clock

signals.

� Single-ended coupon designed to match nominal impedance of DDR2 high-speed

signals (TBD �).

The test coupons are used to test the board’s manufacturing process. With test coupons, a designer can

verify the board’s impedance is within specifications. Test coupons should be placed on layers with crit-

ical, high-speed traces.

DDR2 System Design Guide, Revision 0.2-4 Rambus Confidential DL-0265

DDR2 System Design Guide, Revision 0.2DL-0265 Rambus Confidential -1

Chapter 5 DDR2 Interface Layout

5.1 Component Placement

The layout consists of:

� Memory controller

� DDR2 DRAMs

� The routing between each of these components

5.1.1 Placement Guidelines

The placement of these parts affects:

� Path timing (meeting setup and hold times)

� Signal integrity (amount of reflection, crosstalk, and simultaneous switching)

� Routing (ability to route the board with limited number of layers)

� Board space (amount of board space needed)

� Manufacturing (what manufacturing technology can be used)

The DDR2 DRAMs should be placed close to the DDR2 pins of the memory controller. By doing this, the

traces between the controller and memory will be short and any signal reflections that may develop on

these traces will die out quickly. In addition, placing these parts close together will help in the areas of path

timing and board space.

5.2 High-Speed Routing Requirements

5.2.1 Overview

• Reference plane for high-speed DDR2 signals.

� Reference only to the ground planes or 1.8 v planes. Place ground and/or 1.8 v

plane/island adjacent to each high-speed DDR2 signal layer.

• Recommended PCB signal and reference plane assignment (see Figure 4-1 and Figure 4-

2).

� Microstrip PCB: top DDR2 traces reference to L2 plane; bottom layer lines refer-

ence to L(n-1) plane/island.

� Stripline PCB: L(x+1) DDR2 traces reference to Lx and/or L(x+2) reference

planes/islands.


� Dual-Stripline PCB: L(x+1) DDR2 traces reference to Lx reference plane/island;

L(x+2) traces reference to L(x+3) reference plane/island.

• There is signal attenuation in the PCB trace at high frequency. The signal attenuation

increases with PCB length. In order to maximize system timing and voltage margin, it is

HIGHLY recommended to limit the DDR2 PCB trace lengths to be less than TBD inches,

if possible. The maximum DDR2 PCB trace length should not exceed TBD inches.

• DDR2 signal lines must not be routed over plane splits or voids.

• Equalize routing density on available routing layers to avoid unnecessary congestion and

signal crosstalk.

5.2.2 Impedance

5.2.2.1 Microstrip Line Design

Figure 5-1 depicts the microstrip cross-section of high-speed DDR2 traces.

Figure 5-1: Microstrip Trace Cross-Section

Table 5-1: Example of Single-Ended Microstrip Parameters for DDR2 Channel

Parameter Value (�m)

Dielectric Thickness (h1) TBD

Solder resist+trace+plating thickness (h2) 75 (=25.4+16.6+33.3)

DDR2 trace+plating thickness 50

DDR2 trace width (W) TBD

Spacing (S2) TBD

GND

h1

h2

S1 S2 W

trace trace trace trace

solder

resist

dielectric

DDR2 Interface Layout


Table 5-2: Example of Differential Microstrip Parameters for DDR2 Channel

• Table 5-1 and Table 5-2 give microstrip trace parameters based on the four-layer reference

stackup of Figure 5-1.

� The parameters achieve TBD � single-ended and TBD ��differential trace imped-

ance.

� A nominal finished dielectric thickness of 115 �m is preferred. It should not

exceed ~150 �m.

5.2.2.2 Stripline Design

Depicted below is the cross-section of the stripline trace.

Figure 5-2: Stripline Trace Cross-Section

Table 5-3: Example of Single-Ended Stripline Parameters for DDR2 Channel

Parameter Value (�m)

Dielectric thickness (h1) TBD

Solder resist+trace+plating thickness (h2) 75 (=25.4+16.6+33.3)

DDR2 trace+plating thickness 50


Intra-pair spacing (S1) TBD

Inter-pair spacing (S2) TBD

Parameter Value (um)


DDR2 trace thickness (t) 15.24


Spacing (S2) TBD

GND

h1

S1 S2 W


dielectric

h1

t

GND


Table 5-4: Example of Differential Stripline Parameters for DDR2 Channel

• Table 5-3 and Table 5-4 give trace parameters for the example stripline traces shown

above.

� The parameters achieve TBD � single-ended and TBD ��differential trace imped-

ance.

5.2.2.3 Dual Stripline Design

Figure 5-3 depicts the cross-section of dual stripline traces.

Figure 5-3: Dual Stripline DDR2 Trace Cross-Section

In this dual stripline configuration:

• A separation between the two signal layers (h2) is greater than TBD times the distance

between the signal layer and the nearest reference plane (h1).

• Intra-pair signal lines (or a differential pair) are routed on the same layer with an S1

spacing. Broadside differential pair routing is not recommended.

• Spacing between unrelated traces on the same layer is set to S2.

• Differential pairs on adjacent layers should be staggered relative to each other to minimize

crosstalk.



DDR2 trace thickness (t) 15.24




GND

h2

S1 S2 W


dielectrich1

trace

W

GND

dielectric

dielectric

h1



Table 5-6: Example of Dual Stripline Differential DDR2 Trace Parameters

• Table 5-5 and Table 5-6 give dual stripline trace parameters based on the four-layer refer-

ence stackup of Figure 5-3.

� The parameters achieve TBD � single-ended and TBD � differential trace imped-

ance.

� A nominal finished core dielectric thickness of 100 �m is preferred. The dielectric

thickness should not exceed 150 �m.

5.2.2.4 Other Considerations

• DDR2 signal traces should reference ground and/or 1.8 v.

• The DDR2 signal traces must not be routed over plane splits or voids.

• Vias have a significant effect on signal integrity at high frequency.

� Via separation and antipad rules are TBD.

� No more than TBD through vias are allowed per DDR2 net.

� Avoid placing stub vias on DDR2 microstrip lines.

� Via stub length should not exceed TBD mm length in stripline and dual stripline

configurations.

Table 5-5: Example of Dual Stripline Single-Ended DDR2 Trace Parameters


Core dielectric thickness (h1) TBD

Internal pre-preg thickness (h2) TBD

DDR2 trace thickness 15.24




Core dielectric thickness (h1) TBD

Internal pre-preg thickness (h2) TBD

DDR2 trace thickness 15.24





� For signal probing, use minimal-size pads embedded directly into signal trace.

Probe pad size and layout are TBD.

5.2.3 Trace Length Matching

*

In a DDR2 design, the following signals must limit the amount of skew between them to within certain

tolerances.

• Between the clock signals, "CK" and "CKN", a TBD ps time of flight mismatch is toler-

able on the PCB. To achieve this, a maximum trace length mismatch of TBD is allowed.

• The Data Strobe ("xDQS") and "DQ" lines must be routed similarly and must match trace

lengths. The allowed mismatch between these signal traces is TBD.

• The clock ("CK" and "CKN"), address lines ("A[13:0]" and "BA[2:0]"), "RASN",

"CASN", "WEN", and "CSN[1:0]" (if driven by the memory controller) traces must be

routed similarly and have equal trace lengths with each other. The allowed trace length

mismatch between these signals is TBD.

• Data masks ("DM") must be routed similarly and have equal trace lengths to the "DQ"

bits. The allowed trace length mismatch between the data mask and the data bits is TBD.

• Data strobe ("xDQS") has a setup and hold timing relationship with clock ("CK" and

"CKN"). As a result, data strobe must be delayed relative to clock.

5.2.3.1 Trace Propagation Delay

The above signals require matched trace lengths, that is, equal propagation delay between the controller die

pads and the DDR2 DRAM on the channel. The propagation delay, Td, in picoseconds, for a stripline trace

of length L mm can be calculated by

(Eq 1)

where �r is the relative permittivity of the dielectric. The approximate value for FR-4 is 6.69 ps/mm for a

stripline trace.

The per-unit-length delay of a microstrip trace is geometry-dependent and should be determined through a

2-D field simulation of the trace cross-section. A typical value for FR-4 dielectric is 5.91 ps/mm for a

microstrip trace.

5.2.3.2 Accounting for Package Delay

The total electrical length of a net is the sum of the PCB and controller package propagation delay. It is this total delay that must be matched. The preferred method for calculating package delay is through a field

solver and Spice simulation. This takes into account the substrate delay, the filtering effect of IO pad

capacitance, and the inductive wirebonds, if present. Alternatively, the package delay can be estimated by

multiplying the total length of the wiring in the package—wirebonds and substrate traces—by the appro-

priate per-unit-length delay.

Td 3.335L �r ps=



Figure 5-4: Variables for Estimating Package Wiring Length

If precise data is not available, the package wiring physical length Lpkg for a particular ball can be esti-

mated with the equation

(Eq 2)

where:

• WR is the width of the IO.

• WB is the approximate width of the array of ball pads dedicated to the IO.

• x is the horizontal distance from the center of the IO ball array to the particular ball.

• y is the vertical distance from the edge of the die to the particular ball.

• DO is the offset distance between the center of the IO and the center of the IO ball array

(refer to Figure 5-4).

• The multiplier k is an empirical factor to account for the fact that package traces are

always longer than the straight-line distance from the die pad to the ball. A reasonable

value for k is 1.1. It is always preferable to use precise propagation times if they are avail-

able. In this case, a spreadsheet can be used to tabulate per-pin skews providing the

package delay and PCB trace length for each net.

WR

WB

DO

x

y

IO

Bold circles indicate ballsassociated with IO

Lpkg k y2 x 1WRWB--------–� �

� � DO+2

+


If possible, PCB and package length skews should compensate each other, as shown in Figure 5-5 below.

This reduces the overall timing skew of the two traces.

Figure 5-5: Package/PCB Length Compensation

5.2.3.3 Zig-Zag Routing

Some PCB traces will have to be routed in a serpentine or zig-zag pattern, increasing their length so that

the total propagation delay matches the other nets. When routing traces to achieve length matching, the

board designer should use a serpentine pattern that minimizes the total number of bends. Using a large

number of tight zig-zags will result in a trace with a smaller effective propagation delay than would be

predicted by its length.

Figure 5-6 illustrates the preferred style of length-matching. All the traces in the figure are of equal length,

but the routing on the right is better than that on the left because fewer bends are used to achieve matching

length. Right-angle bends should be avoided in favor of 45o bends. The minimum distance between bends

should be no less than twice the trace width.

Package PCB

DQ DQN



..

Figure 5-6: Length-Matching Routing

5.2.4 Crosstalk Control

These following actions can be taken to reduce crosstalk between traces.

5.2.4.1 General Considerations

• Equalize routing density on available signal routing layers to avoid routing congestion and

associated crosstalk.

• Where possible, closely positioned vias that contain sensitive or high-speed signals should

be shielded vertically by placing a ground via between them.

• Separate fast edge rate, sensitive, adjacent traces by an appropriate distance. This distance

is determined by analyzing the system’s noise budget and the coupling between the adja-

cent traces. This rule also applies to traces in adjacent layers.

• Separate adjacent signal layers that contain fast edge rate, sensitive signals by an appro-

priate distance.

• Set a minimum distance a critical trace is allowed to have between it and another trace.

• Use ground traces or vias to isolate critical traces.

• Reduce the separation between the critical signal’s trace and its return path.

• Make the critical signal’s return path a very low impedance path.

Distance between

AVOID THIS MINIMIZE TOTAL NUMBER OF BENDS

turns should be no lessthan 2X the trace width


5.2.5 Clearances

5.2.5.1 Metal Structures

The vertical separation between any DDR2 trace and a planar metal structure (floating or fixed potential)

should be at least TBD times the microstrip dielectric thickness (that is, dimension "h1" in Figure 5-1).

Adhesive material should not be applied directly to the PCB surface above or within TBD horizontal

distance of any DDR2 trace. This rule applies to metal features such as heat sinks and mounting brackets,

as illustrated in Figure 5-7.

Figure 5-7: Examples of DDR2 Vertical Metal Clearance

A minimum horizontal separation of 600 �m should be maintained between DDR2 lines and metal shapes

etched on the same PCB layer. This pertains to partial plane floods used for power distribution and compo-

nent solder pads that run parallel to the DDR2 signal trace for greater than 2 mm.

5.2.5.2 PCB Through Holes

A 600 �m or greater horizontal clearance should be maintained between DDR2 traces and large PCB

through holes and metal capture pads, such as mounting holes and component rework holes. This require-

ment does not apply to PTH vias used for signal routing.

Greater than 4X h1

Bad OK

OK OK

Ddr Routing Guidelines

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