HARDWARE LAB-I (CS-217)

INSTRUCTION MANUAL

DEPARTMENT OF COMPUTER SCIENCE ENGINEERING AND

INFORMATION TECHNOLOGY.

BABA BANDA SINGH BAHADUR ENGINEERING COLLEGE,FATEHGARH SAHIB-140407

CONTENTS

1. Verification of the truth tables of TTL gates, e. g., 7400, 7402,7404, 7408, 7432, 7486.2. Design, fabrication and testing of low frequency TTL clocks using NAND gates.3. Verification of the truth table of the Multiplexer 74150.4. Verification of the truth table of the De-Multiplexer 74154.

5. Design and verification of the truth tables of(a) half adder circuits (b) full adder circuits

using gates 7483.6. (a)Design and test of an SR flip flop using Nor/Nand gates. (b)Verify the truth table of a J-K flip flop.(7476) (c)Verify the truth table of a D-flip flop (7474) and study its operation in the toggle and asynchronous modes.7. (a) To study the operation of 2 bit and 4 bit asynchronous counters. (b) To study the operation of 2 bit and 4 bit synchronous counters.8. To study the operation of 2 bit and 4 bit Johnson counters.

EXPERIMENT NO.1

AIM: Verification of truth table of TTL gate e.g. 7400, 7402, 7408, 7432, 7486, 7404.

EQUIPMENT: IC:-7400, 7402, 7432, 7486, 7404; Logic trainer board; BinarySwitches.

THEORY: The logic gate is a circuit which has two or more inputs and only one outputsignal. Gates are digital circuits because the signals are either high or low. OR, NOR,AND are basic gates. NAND and NOR are universal gates. The truth table is the tablewhich shows all the output possibilities for all input combinations for a logic circuit.

AND: Two or more inputs and only one output is in AND gate. The input must be high toobtain high output.

Boolean Expression: Y=AB

Truth Table:

A B Y=A.B 0 0 0 0 1 0 1 0 0 1 1 1

OR: Two or more inputs and only one output are in OR g~o get a high output anyone of all the input may be high.

Boolean Expression: Y=A+B

Truth Table:

A B Y=A.B 0 0 0 0 1 0 1 0 0 1 1 1

NOT: One input and only one output is in NOT gate. The output state is always theinverted of input.

Boolean Expression: Y=A'

Truth Table:

A Y=A’ 0 1 1 0

NAND: NAND gate is combination of AND gate and NOT gate.

Boolean Expression: Y=(AB)’

Truth Table:

NOR: NOR gate is combination of OR gate and NOT gate.

Boolean Expression: Y=(A+B)’

Truth Table:

A B Y=A.B’ 0 0 1 0 1 1 1 0 1 1 1 0

A B Y=A+B’ 0 0 1 0 1 0 1 0 0 1 1 0

PROCEDURE:1. First of all IC 7400 was inverted on IC base of logic trainer board.2. 5V supply was given to pin14 and ground was connected to pin7.3. Input A&B was given to pinl and pin2 using binary switches.4. Output pin3 was connected to LED.5. Then the trainer was switched on.6. Output of LED was observed and noted corresponding to input values.7. .Different combinations of input were fed and output was noted.8. The same thing is repeated for all IC's.

RESULTS:

IC No. Types of gates inside 7400 NAND gate 7402 NOR gate 7408 AND gate 7432 OR gate 7404 NOT gate 7486 XOR gate

PRECAUTIONS: 1. Reverse connection to pin14 and pin7 of an IC can cause error. 2 .Output of LED should be written carefully corresponding to respective input.

CONCLUSION: Output of IC 's were composed with truth tables of different gates andit was concluded that 7400 is an IC of NAND gate, 7402 is an IC of NOR gate, 7404 isan IC of NOT gate, 7408 is an IC of AND gate, 7432 is an IC of OR gate AND 7486 ISan IC of XOR gate.

EXPERIMENT NO.2

AIM:Design, fabrication and testing of low frequency TTL clocks using NAND gates.

EQUIPMENT:-IC 7400,Connecting nobs.

THEORY: Transistor–Transistor Logic (TTL) is a class of digital circuits built from bipolar junction transistors(BJT), and resistors. It is called transistor–transistor logic because both the logic gating function and the amplifying function are performed by transistors .Integrated circuits (IC) family used in many applications such as computers, industrial controls, test equipment and instrumentation, consumer electronics etc. Because of the wide use of this logic family, signal inputs and outputs of electronic equipment may be called "TTL" inputs or outputs, signifying compatibility with the voltage levels used.

TTL integrated circuits are examples of small-scale to large-scale integration. Each "chip" contains the equivalent of a few dozen to a few hundred transistors, contrasting with early very-large-scale integration devices that had the equivalent of up to 10,000 transistors, and modern microprocessors that are equivalent to tens of millions of transistors.

Low-power TTL, which traded switching speed (33ns) for a reduction in power consumption (1mW). TTL IC s use a relatively small amount of power individually,but in moderate to large systems,using many IC packages power drain can very quickly add up. To alleviate this problem,special Low power TTL IC s are sometimes used. These low power units are numbered in same way as regular TTL devices ,but with L added in the middle to indicates to low power status requires only tenth part of power as much require for standard TTL version.

In low power TTL gate,the resistor values are higher than in the standard gate to reduce power dissipation,but the propagation delay is increased.

TTL versions and Characteristics: Name Abbreviation Propagation

delay (ns)Power dissipation(mW)

Standard TTL TTL 10 10

Low power TTL LTTL 33 1

High speed TTL HTTL 6 22

Schottky TTL STTL 3 19

EXPERIMENT NO.3

AIM: Verification of the truth tables of the Multiplexer 74150.

EQUIPMENT: IC 7415.0, logic trainer board, binary switches.

Theory:Multiplex means many input and one output. A multiplexer is a circuit with many data inputs but only one output. By applying control signals (called select or address lines), you can steer any input to the output. Multiplexers are available asfor 2: 1, 4: 1, 8:1 and 16:1 multiplexed operations.

CIRCUIT DIAGRAM:

BLOCK DIAGRAM OF MUX

PIN OUT OF 16:1 MUX

PROCEDURE: 1. Give high/low inputs to the select lines with the help of binary switches 2. Give high input to the corresponding selected data line. 3. Observe the output from LED.

4. Note down in the observation table.5. Repeat the steps for all combinations of address lines.

OBSERVATIONS:

D C B A Y0 0 0 0 Eo0 0 0 1 E10 0 1 0 E20 0 1 1 E30 1 0 0 E40 1 0 1 E50 1 1 0 E60 1 1 1 E71 0 0 0 E81 0 0 1 E91 0 1 0 E101 0 1 1 E111 1 0 0 E121 1 0 1 E131 1 1 0 E141 1 1 1 E15

RESULT:Truth table of IC 74150 is verified.

PRECAUTIONS. 1. Output of LED should be written carefully corresponding to the respective inputs. 2. Connections should not be loose,

EXPERIMENT NO.4

AIM: Verification of the .truth table of the Demultiplexer.

EQUIPMENT: IC 74154, logic trainer board, binary switches.

THEORY:A demultiplexer (DEMUX) performs the reverse operation of a multiplexer.It accepts one input and steers it to one of the several outputs by means of select lines, Like MUX we have 1:2,1:4,1:8 and 1:16 DEMUX too.Demultiplexer are commonly called decoders e. g.1-line to 4-line DECODER,a 1:16 DEMUX is called a 4-line to 16-line. DECODER(used for decoding a nibble of bits to its hexadecimal equivalent). The block diagram of a demultiplexer is shown in figure.

BLOCK DIAGRAM:

-'-"

PIN OUT OF 1:16 DEMUX

PROCEDURE: 1. Strobe is active low in this IC. F:irstof all give high signal to the strobe and observe the output. 2. Give low signal to the strobe and hence activate IC 3. Give inputs to the two input lines with the help of binary switches 4. Observe the output from LED.

5. Record the readings in a table.6. Repeat the procedure for all possible combinations of the inputs.

OBSERVATIONS:

G S1 So Yo Y1 Y2 Y3H * * H H H HL 0 0 L H H HL 0 1L 1 0L 1 1

RESULT:Truth table of IC 74154 is verified.

PRECAUTIONS: 1. Output of LED should be written carefully corresponding to the respective inputs. 2. Connections should not be loose.

EXPERIMENT NO. 5(a)

AIM: Design and Verification of the truth table of half-adder using i. ANDandXOR gate.

ii. Using IC-7483

EQUIPMENT: IC 7483, 7408, 7486, Logic trainer board and binary switches.

THEORY: Half adder can add two bit at a time. It is seen that binary addition generatesa sum and carry. The rules for addition are tabulated in the truth table.

The truth table leads to the following logic equations for sum(S) and carry (C).S=AXORB C=A.B

TRUTH TABLE

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

Half adder can not accept a carry from a previous addition, hence use of half added islimited.LOGIC CIRCUIT:

PROCEDCURE:. 1. To verify truth table using AND & XOR gates setup the circuit as shown in

diagram. 2. Give different combinations of inputs to A & B and note down outputs

corresponding to Carry and Sum. 3. To verify truth table using IC 7483, give 5V supply to pin5 and ground to pinI2. 4. Give different combinations of inputs to pinl0 & pin11 only. 5. Note down the output from pin9 (Sum) and pin6 (Carry) and make observation table. Also make Al and BI zero.

RESULT: Output of XOR gate and pin9 of lC 7483 is same as that of TT for Sum andoutput of AND gate and pin6 of lC 7483 is same that of TT for Carry.

CONCLUSION: Half adder can be realized using either AND or XOR gate or IC 748l

EXPERIMENT NO.5(b)

AIM: Design and verification of truth table of full adder using i. NAND and XOR gate. ii. IC 7483.

EQUIPMENT: IC 7483, 7400, 7486, Logic Trainer Board and Binary switches.

THEORY: Full adder is used to add three or more bits. The addition is complex. Anyprocess to add multi bit numbers should have provision to accept carries from an additionof bits to the right & to pass carries to the left. . Sum (S) =AXORB XORC Carry(C) = AB+AC+BC

TRUTH TABLE : Z X Y S C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Binary adder circuit requires combination of half adder & full adder. Four bit binaryadder circuit has been given in figure.

PROCEDURE:1. To verify truth table using NAND and XOR gates, setup the circuit as shownin circuit diagram.2. Give different combinations of inputs to A, B, C and note down the outputcorresponding to Carry and Sum.3. Give different combinations of four bit input to pin 1,3,8,10 and pin 16,4,7,11corresponding to A3,A2,Al,AO,B3,B2,Bl,BO respectively.4. Note down the output from pins 15,2,6,9 corresponding to S3,S2,S1,S0andpin14 corresponding to Sum and Carry.

RESULT: The truth table of full adder has been verified using XOR & NAND gates andIC 7483.

CONCLUSION: Full adder is the fundamental building block of 4-bit binary adder(IC7483).

EXPERIMENT No.6(a)

AIM: (a) Design and test of a SR ff using NANDI NOR gates.

EQUIPMENT: IC 7402, IC 7400, logic trainer board and binary switches.

THEORY:The SR ff is the most basic of all ff s and can be realized using NOR/NAND gates. Figure1 shows the RS ff in NOR logic whereas figure2 shows the RS ff in NAND logic. In NOR logic, low R and low S results in inactive state. Low R and high S results in set state, high R and low S results in reset state,whereas both Rand S high results in invalid state. NOR gate gives output one if all the inputs are low. The results are summarized in following truth table.

CIRCUIT DIAGRAM:

a. SR ff using NOR gates

TRUTH TABLE :

S R Q 0 0 No change 0 1 0 1 0 1

1 1 ?

NAND gate gives output zero iff all the inputs are high. In NAND,logic low Rand S results in forbidden state, low S and high R results in set state. Low R and high S results in reset state whereas both Rand S high results in no change in state.

b. SR ff using NAND logic

TRUTH TABLE:

S R Q 0 0 ? 0 1 0 1 0 1 1 1 No Change

To have same output from NAND logic as that of NOR logic,inverted in-puts must be given to NAND logic.

PROCEDURE: 1. Insert IC 7400 on IC base of logic trainer board. 2. Give +5V supply to pin 14 and ground pin 7. 3. Form RS ff as shown in fig.2. 4. Give binary inputs and observe outputs. 5. Note down the outputs in a table.

6. Insert IC 7402 on IC base of logic trainer board. 7. Give +5V supply to pin 14 and ground pin 7. 8. Form RS ff as shown in fig.1. 9. Give binary inputs and observe outputs. 10.Note down the outputs in a table.

OBSERVATIONS:

R S NOR LOGIC O/P

NAND LOGIC O/P

0 0 0 1 1 0 1 1

PRECAUTIONS: 1. Output should be written carefully corresponding to the respective inputs. 2. Connections should not be loose.

EXPERIMENT NO.6(b)

AIM: Verify the truth table of a JK ff (7476).

EQUIPMENT:Logic trainer board and binary switches.

THEORY:The JK ff is a versatile. The uncertainty in the state of a SR ff when S=R=1 can be eliminated by using master-slave JK ff. The data inputs J & K are ANDed with inverted and non-inverted outputs respectively to obtain S &R inputs. The M-S JK ff is a cascade of two SR ff 's with feedback from the outputs of the second to the inputs of the first as shown in figure. Positive clock pulses are applied to the first ff & the clock pulses are inverted before these are applied to the second ff. First RS ff is called the master & the second is the slave. When clock is high, the master is active & the slave is inactive. When clock is low, the master is inactive & the slave is active. The output Q will change at the falling edge of clock. Hence race around condition is avoided.

SYMBOL:

PIN OUT OF IC 7476:

JK master Slave Flip flop circuit diagram

TRUTH TABLE:

PROCEDURE: 1. Connect the Vcc to pin5 & ground to pin 13 of the IC. 2. Connect the preset terminal to "a" and clear terminal to "1" & observe the output. 3. Connect the preset to "1" and clear terminal to "a" & observe the output. 4. Connect the preset and clear terminals to "1".Apply clock to the clock terminal. 5. Observe the output for all possible combinations of inputs to J & K Input terminals. 6. Note down all the observations in the table.

OBSERVATIONS:

Pr Clr Clk J1 K1 Output0 1 0 * *1 0 0 * *1 1 1 0 01 1 1 0 11 1 1 1 0 1 1 1 1 1

RESULT:Slave ff just copies the action of master ft. M-S JK ff is capable of solvingthe race problem of SR FF.

PRECAUTIONS:1. Output should be written carefully corresponding to the respective inputs.2. Connections should not be loose.

EXPERIMENT NO. 6(c)

AIM: Verify the truth table of aD ff (7474) & study its operation in thetoggle and asynchronous modes.

EQUIPMENT: IC7474, logic trainer board and binary switches.

THEORY:This is the most commonly used type of FF in computers as it samples thedata at a unique instant of time. It is used to avoid race problem in SR. In D ff,only one input is given from outside & the second is obtained from first i/p by inverting that. Hence both inputs are never high together. In this way race problem will never occur.

PIN OUT OF IC 7474

CIRCUIT DIAGRAM USING NAND GATES:

D-type positive-edge triggered flip-flop

TRUTH TABLE:

CLK D I/P D O/P 0 * NC 1 0 0 1 1 1

In asynchronous mode, preset and clear (called asynchronous inputs) are used. Applying '0' to preset will force the O/P to be 1 even if 0 I/P is '0'. Similarly applying '0' to clear will force the O/P to be '0' irrespective of the 0 I/P.

PROCEDURE: 1. Give power supply to IC chip (i.e. Vcc to pin14 & ground to pin?). 2. To verify truth table of 0 ff, apply i/p to 01 (pin2). Initially don't give clock and observe the output from pin5. 3. Apply clock to pin3 & observe the output for different inputs. t. 4. To study asynchronous mode operation, apply different inputs to preset & clear terminals (pin4 & 1 respectively) and observe the output from pin5. 5. Note down all the observations in the table

OBSERVATIONS:

Pr Clr Clk D I/P

Q O/P

0 0 * *0 1 * *1 0 * *1 1 0 *1 1 1 01 1 1 1

RESULT:Same input appear at output after some time i.e. when active clock appears, hence the name Delay (D) ff. Race problem of SR ft has been solved in D.

PRECAUTIONS:1. Output should be written carefully corresponding to the respective inputs.2. Connections should not be loose.

EXPERIMENT NO.7(a)

AIM: To study the operation of 2 bit and 4 bit asynchronous counters.

EQUIPMENT: IC 7473,trainer bread board, binary switches.

THEORY:A counter is a sequential machine that produces a specified count sequence. The count changes whenever the input clock is asserted. There is a great variety of counter based on its construction.1. Clock: Synchronous or Asynchronous2. Clock Trigger: Positive edged or Negative edged3. Counts: Binary, Decade4. Count Direction: Up, Down, or Up/Down

5. Flip-flops: JK or T or D• A counter can be constructed by a synchronous circuit or by an asynchronous circuit. With a synchronous circuit, all the bits in the count change synchronously with the assertion of the clock. With an asynchronous circuit, all the bits in the count do not all change at the same time.• A counter may count up or count down or count up and down depending on the input control.• Because of limited word length, the count sequence is limited. For and n-bit counter, the range of the count is [0, 2n-1]. The count sequence usually repeats itself. When counting up, the count sequence goes in this manner: 0, 1, 2, … 2n-2, 2n-1, 0, 1, …etc. When counting down the count sequence goes in the same manner: 2n-1, 2n-2, … 2, 1, 0, 2n-1, 2n-2, … etc.

Asynchronous: The events do not have a fixed time relationship with each other and do not occur at the same time .The clock pulse fed into FF0 is rippled through the other counters after propagation delays, like a ripple on water, hence the name Ripple counter.

The external clock is connected to the clock input of the first flip-flop (FF0) only. So, FF0 changes state at the falling edge of each clock pulse, but FF1 changes only when triggered by the falling edge of the Q output of FF0. Because of the inherent propagation delay through a flip-flop, the transition of the input clock pulse and a transition of theQ output of FF0 can never occur at exactly the same time. Therefore, the flip-flops cannot be triggered simultaneously, producing an asynchronous operation.

The 2-bit ripple counter circuit above has four different states, each one corresponding to a count value. Similarly, a counter with n flip flops can have 2 to the power n states. The number of states in a counter is known as its mod (modulo) number. Thus a 2-bit counter is a mod-4 counter.

CIRCUIT DIAGRAM AND CLOCK PULSE:.

2-Bit Ripple Counter

TRUTH TABLE: Count Q1 Qo 0 0 0

1 0 1

2 1 0

3 1 1

A 4 bit ripple counter is shown in the figure. It consists of 4 edge triggered JK flip flop. As indicated by small circles at the CLK input of FF, the triggering occurs when CLK input gets a negative edge. Q0 is the least significant bit(LSB) and Q3 is the most significant bit(MSB). The FF’s are connected in series. The Q0 output is connected to CLK terminal of second FF. The Q1 output is connected to CLK terminal of third FF and so on. By adding more FF’s, a counter of any length can be built. It is known as a ripple counter because the carry moves through the FF. Initially, CLR is made low and all the

FF’s reset giving an output Q=0000.When CLR becomes high, the counter is ready to start. As LSB receives its clock pulse, its output changes from 0 to 1and the total output Q=0001.When second CLK pulse arrives,Q0 resets and carries (i.e., from 0 to 1 and ,second FF receive CLK input). Now the output is Q=0010.The third CLK changes Q0 to 1 giving a total output Q=0011.The fourth CLK pulse causes Q0 to reset and carry and Q1 also resets and carries giving a total output Q=0100 and the process is goes on. The number of output states of a counter is known as modulus or mod. A ripple counter with 4 FF’s can count from 0 to 15 and known as mod-16 counter.

CIRCUIT DIAGRAM:

TRUTH TABLE: – 4 -BIT RIPPLE COUNTER

Count Q3 Q2 Q1 Q0 0 0 0 0 0 1 0 0 0 1

2 0 0 1 0 3 0 0 1 1 4 0 1 0 0 5 0 1 0 1 6 0 1 1 0 7 0 1 1 1 8 1 0 0 0 9 1 0 0 1 10 1 0 1 0 11 1 0 1 1 12 1 1 0 0 13 1 1 0 1 14 1 1 1 0 15 1 1 1 1

PROCEDURE: 1.Insert IC in the IC base of logic trainer board and construct the circuit. 2.Clear the output to 0000. 3.Apply clock pulses using clock generator. Observe the LEDs.

EXPERIMENT NO. 7(b)

AIM:To study the operation of 2 bit and 4 bit synchronous counters.

EQUIPMENT: IC 7473,trainer bread board, binary switches.

THEORY:Synchronous CountersIn synchronous counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel).

2-BIT SYNCHRONOUS BINARY COUNTER AND ITS CLOCLK PULSE:

BINARY STATE SEQUENCE:

FF1 FF0

0 0

0 1

1 0

1 1

4-BIT SYNCHRONOUS BINARY COUNTER

In this counters, the clock inputs of all the flip-flops are connected together and are triggered by the input pulses. Thus, all the flip-flops change state simultaneously (in parallel).JK flip flops are used.

4-BIT SYNCHRONOUS BINARY COUNTER AND ITS CLOCK PULSE

PROCEDURE: 1.Insert IC in the IC base of logic trainer board and construct the circuit. 2.Clear the output to 0000. 3.Apply clock pulses using clock generator. Observe the LEDs.

EXPERIMENTNO.8

AIM:To study the operation of 2 bit and 4 bit Johnson counter.

EQUIPMENT: Johnson counter, Bounce less pulse generation,Set of patch chords & manual.

THEORY:A counter is a versatile subsystems in a digital system. A counter driven by a clock can be used to control the number of clock cycles. Since the clockpulses occur at known intervals, the counter can be used as an instrument for measuring time and therefore period or frequency. There are basically two different types of counters-Synchronous and asynchronous.We want a counter that provides individual digit outputs rather than a binary or BCD output. Of course, we can do this by adding a decoder circuit to the binary counter.In many cases it is much simpler to use a different counter structure, that will permit much simpler decoding of individual digit outputs.For example, consider the counting sequence to the right. It actually resembles the behavior of a shift register more than a counter, but that need not be a problem. Indeed, we can easily use a shift register to implement such a counter. In addition, we can notice that each legal count may be defined by the location of the last flip-flop to change states, and which way it changed state. This can be accomplished with a simple two-input AND or NOR gate monitoring the output states of two adjacent flip-flops. In this way, we can use ten simple input gates to provide ten decoded outputs for digits 0-9. This is known as the Johnson counting sequence, and counters that implement this approach are called Johnson Counters. The 4-stage circuit uses four flip-flops, and therefore has 16 possible binary states. The 4-stage counter uses only eight of 16 possible states. We must include circuitry that will filter out the illegal states and force this circuit to go towards the correct counting sequence, even if it finds itself in an illegal mode when first powered up. This is not difficult, and the demonstration circuit below includes the necessary gating structure.The demonstration above initially implements only the legitimate counting sequence of the Johnson counter. Each output is enabled by a transition from 0 to 1 or from 1 to 0 in a specific position in the counter.

.

JOHNSON COUNTER:

TRUTH TABLE:

A B C D Count0 0 0 0 01 0 0 0 11 1 0 0 2 1 1 1 0 31 1 1 1 40 1 1 1 50 0 1 1 60 0 1 1 7

PROCEDURE: 1. Switch 'ON' the experimental kit. 2. Connect the monopluse output to the clock input of Johnson counter. 3. Reset the counter with reset switch. 4. Observe the counter outputs and verify the truth table.