DCDC Design Slides Ver2

Design of DC-DC Converters

Frank [email protected]

Monolithic Power Systems Inc.

IEEE SSCS Dallas Chapter, October 2007

11/1/2007 IEEE SSCS - Oct. 2007 2

Design of DC-DC Converters

DC-DC Converter BasicsTopology and Operation of DCDC ConvertersControl Scheme for DCDC

DC-DC Converter Design TechniquesSystem Level Modeling and DesignBuilding Block Design Considerations

11/1/2007 IEEE SSCS - Oct. 2007 3

DC-DC Converter Basics

DC-DC Converter is a Voltage RegulatorUse Switches, Inductor and Capacitor for Power ConversionSwitched Mode Operation

Why DC-DC Converters?High EfficiencyCan Step-Down, Step-up, or Both, or Invert Can Achieve Higher Output Power

11/1/2007 IEEE SSCS - Oct. 2007 4


Why not DC-DC Converters?Complex Control LoopHigher Noise and Output RippleMore External Components

Basic DC-DC Converter TopologiesMajority of DC-DC uses PWM Control Operated in CCM Mode

11/1/2007 IEEE SSCS - Oct. 2007 5


Basic RelationshipsCCM Mode

IL always supplies loadIC small, independent of load

DCM Mode

IN

IN

OON

ONOUT V

VTLIT

TV⋅⋅

+= 22

2

OUTIN

ININON

OUT

IDI

VDVT

TV

⋅=

⋅==

Step-down (Buck)L

C

S

D

VSW VOUTVIN

IL IC

VSW

IL

IO

IO

VOUT

IIN

TON

T

Continuous Conduction Mode (CCM)

ID

IIN ID

IL

Discontinuous Conduction Mode (DCM)

IO

11/1/2007 IEEE SSCS - Oct. 2007 6


Step-up (Boost)Basic Relationships

CCM ModeIL only supplies load during TOFF periodIC large and load dependent

DCM Mode

INON

IN

OON

OUT VT

VTLIT

V 2

2 2 ⋅⋅+

=

OUTLIN

ININOFF

OUT

ID

II

VD

VT

TV

⋅−

==

⋅−

==

11

11

L

CS

DVSW VOUTVIN

IL IC

VSW

IL

-IO

IO

VOUT

TON

T

Continuous Conduction Mode (CCM)

IC

IL

-IODiscontinuous Conduction Mode (DCM)

IC

TOFF

11/1/2007 IEEE SSCS - Oct. 2007 7

Common Control Architectures

Modulation SchemePFM (Pulse-Frequency-Modulation)

Pulse Skipping, Hysteretic, Constant-on etc. High Efficiency at Light LoadInherently Higher Output RippleUnmanaged Spectrum Noise

PWM (Pulse-Width-Modulation)Fixed Frequency with Variable Duty CycleBetter Transient Response (except Hysteretic?)

Most Widely Used

11/1/2007 IEEE SSCS - Oct. 2007 8


Control Method (for PWM)Voltage Mode

Regulates Output Voltage by Adjusting Duty CycleConstant Ramp for Modulation, Better Noise ImmunityLC Filter Contributes to Complex Conjugate PolesLoop Has No Information on Inductor CurrentSlower Response to Input Voltage ChangeBandwidth Varies with Input VoltageCurrent Limit Done Separately

11/1/2007 IEEE SSCS - Oct. 2007 9


Current ModePCM (Peak-Current-Mode) Most Commonly Used Regulates Inductor Current to Satisfy Load Demand and Maintain Output Voltage Fast Current Loop makes Inductor to be a VCCS, eliminates Complex Conjugate PolesEasy Built-in Cycle-to-Cycle Current LimitNaturally Suitable for Multi-Phase OperationCurrent Sense Susceptible to NoiseNeed Slope Compensation for >50% Duty Cycle Operation

11/1/2007 IEEE SSCS - Oct. 2007 10

DC-DC Converter Design

Examples of Common DC-DC ConvertersVoltage Mode Buck

L

C

S1VSW

RESR

RL

S2

R1

R2

VREF

VRAMP

S

R

Q

QB

CLK

VFBVEA

VOUTVIN

CLK

VRAMP VEA

VSW

VOUT

IL IOUT

D

D’

EARST

11/1/2007 IEEE SSCS - Oct. 2007 11

Voltage Mode Buck

Voltage Mode Buck Transfer Functions:

amplifiererror the of functiontransfer the is where

and

)(

)(1

11,1

1

)1(

1)(

)1(

0

20

2

0

2

sa

saVv

d

LCR

CL

R

QLC

sQ

ssCRV

CRRLsLCs

sCRVdv

RFB

ESRL

ESRIN

ESRL

ESRIN

O

=

+==

++

+=

+++

+≈

ω

ωω

11/1/2007 IEEE SSCS - Oct. 2007 12

Voltage Mode Buck

Example: L=2.2uH, C=22uF, RESR=10m OhmVIN=5V, VOUT=3.3VRL=10 OhmFSW=1.5MHzVRAMP=100mV

ω0 = 22.9kHzQ = ~15.8ωZ = 700kHz

Control (Duty Cycle) to Output Transfer Function:

11/1/2007 IEEE SSCS - Oct. 2007 13

Voltage Mode Buck - Error Amp Ex. 1

20

2

0

1

2

1

2

1

2

1

)1(

)(

ωωs

QssCR

VV

RRLG

vRRv

VVRRVV

ESR

R

IN

FBEA

FBREFREFEA

++

+⋅−=

−=

−+=

Use low DC gain to set the bandwidth so that the phase margin is acceptable:

Bandwidth: ~400kHzPhase margin: ~35°Conditionally stable

Example: R2=500k, R1=100k, VR=100mVClosed loop step response

EAVREF

VFB

R1 R2VEA

11/1/2007 IEEE SSCS - Oct. 2007 14


Some Improvements Can Be Added:Make VRAMP proportional to VIN -> Constant BandwidthAdd Feed-forward Cap on Feedback Resistor String -> better phase margin

Limitations of Low DC Gain:Loose Output RegulationNeed some ESR to Stabilize the LoopSmall Modulation Ramp Sensitive to NoiseDC Offset if Output Cap has large ESR

11/1/2007 IEEE SSCS - Oct. 2007 15


Use Type-III Compensation Network to Re-Shape Loop Frequency Response:

LCVVCRUGBW

sQ

ssCR

VV

CsRCsRCAsRCsRRsCALG

CCsRCsRCCAsRCRRsRsCA

vv

R

IN

ESR

R

IN

FB

EA

1

1

)1()1)(1](1[

)1)(1()||1)(1)]()(1(1[

])(1)[1(

21

20

2

0

3122103

23110

131223103

223110

⋅⋅≈

++

+⋅

+++++

−≈

++++++++

−≈

ωω

• High DC gain rolls off by dominant pole and, phase shift recovered by 1st zero before ω0

• 2nd zero brings back phase shift above ω0

• 2nd and 3rd pole attenuates high frequency noise

Example Design Steps:1. Set R1C2=100uS for desired

BW of ~300kHz 2. Set 1st zero to be 1/5 of ω0:

R1=1Meg, C1=30pF, ωz1=5.3kHz

3. Set 2nd zero to be 4x of ω0: C2=10pF, R3=200k, ωz2=79.5kHz

4. mid-band DC gain of 5: R3=200k

5. Set 2nd and 3rd pole to near switching frequency for high frequency noise attenuation: C3=0.2pF, ωp2=795kHz; R2=10k, ωp3=1.5MHz

EAVREF

VFB

VEA

R3

R2

R1

C2

C1

C3

11/1/2007 IEEE SSCS - Oct. 2007 16


• Modulation ramp VRAMP increased to 500mV for better noise immunity

• Blue: control to output transfer function• Green: Type-III compensation error

Amp transfer function• Red: Complete loop transfer function

bandwidth: ~340kHz, PM: ~65 degree

Compare to Error Amp Ex. 1:• Step response has less overshoot

due to better phase margin• Settling is much slower due to 1st

zero at low frequency

11/1/2007 IEEE SSCS - Oct. 2007 17


Current Mode Buck (Peak Current Control)

L

C

S1VSW

RESR

RL

S2

R1

R2

VREF

VRAMP

S

R

Q

QB

CLK

VFBVEA

VOUTVIN

CLK

VRAMP

VEA

VSW

VOUT

IL IOUTD

D’

EA

Slope Comp

RSEN

RST

RST

11/1/2007 IEEE SSCS - Oct. 2007 18

Current Mode Buck

correction cycle 1 ,

stable guaranteed ,2

:ex

1 that sochosen is

)(][]1[

2

2

1

2

1

2

mm

mm

mmmmm

mmmmnini

a

a

a

aa

a

aee

=

=

<+−

+−

−⋅=+

Inductor Current Instability for Duty Cycle > 50%:

Requires Slope Compensation:

cyclesover grows :1

cyclesover attenuates :1

]0[)(][]1[

1

2

1

2

1

2

1

2

e

e

n

eee

imm

imm

mmi

mmnini

>

<

⎟⎟⎠

⎞⎜⎜⎝

⎛−⋅=−⋅=+

m1 m2

m1m2

ma

ie[n]

ie[n+1]

ie[n]

ie[n+1]

ie[n+1]

ie[n]

1. D=1/3: m2/m1=1/2

2. D=2/3: m2/m1=2

3. D=2/3 with slope compensation

11/1/2007 IEEE SSCS - Oct. 2007 19

Current Mode Buck• Fast current loop regulates inductor peak current, can

be modeled as a VCCS with output impedance Rx

• Slower voltage loop provides reference for current loop

)1(21

12

5.0)1)(1(

12

1

1

1

11)(

11

1

]5.0)1)(1[(1

11)(

11

1)(

]5.0)1)(1[(

1

11

]5.0)1)(1[(1

11

21

2

2

1

1

2

1

1

mmDD

mmQ

sQ

sRRR

sG

sTe

eDmm

LTRR

sG

mmmm

sTe

esH

DmmT

LR

RRRD

mm

LTRRv

iG

aa

SSX

LSENm

S

sT

sTaSLSEN

m

a

a

S

sT

sTe

aS

X

X

LSENaSLSENEA

om

S

S

S

S

−−=

−−+=

+++≈

−⋅++

−−++=

+−

=−

⋅++

=

−−+=

+=

−−++==

−

−

−

−

ππ

ωω

αα

αα

α

:responsefrequency including ctancetranscondu VCCSComplete

where

:effect sampling anddelay in results Operation Switched

where

C

RESR

RL

R1

R2

VREF

VFBVEA

VOUTVIN

EA

Gm IO

RX

11/1/2007 IEEE SSCS - Oct. 2007 20

Current Mode Buck

Example: L=2.2uH, VIN=5V, VOUT=3.3V, RL=10 OhmRSEN = 0.5 OhmFSW = 1.5MHz

Blue: ma=0.5*m2RX=19.4 OhmGm=1.32 A/VQ=1.87

Green: ma=m2RX=6.6 OhmGm=0.80 A/VQ=0.64

Peak Current Mode Current Loop Transfer Function

11/1/2007 IEEE SSCS - Oct. 2007 21

Current Mode Buck

Control to Output Transfer FunctionEquivalently Single-Pole System with Current Source Input

)]||(1[1

)(1

1

1

12 XL

ESR

SSX

LSEN

LOm

EA

o

RRsCsCR

sQ

sRRR

RZGvv

++

+++=⋅=

ωω

Example: C=22uF, RESR=10m OhmRSEN = 0.5 OhmFSW = 1.5MHzRX=19.4 Ohm

RL=10k, 1k, 100, 10, 1 OhmRL=10k, 1k, 100, 10, 1 Ohm

11/1/2007 IEEE SSCS - Oct. 2007 22

Current Mode Buck – Error Amp

Error Amplifier Example:

impedanceoutput the is amperror the of ctancetranscondu the is :where

o

m

C

ZZomoC

ZC

FB

EA

rg

CCRsCRrRgrsC

RsCAvvsa

)()1)]((1[

1)(

1

110

>>++++

+−≈=

EAVREF

VFB

R1

RZ

VEA

CC

C1

ie

• Bandwidth defined by R1 and C1

• Much smaller CC, need large RZ

• VFB more error during transientExample:

gm=100uS, ro=10MOhm,R1=100kOhm, CC=25pF, RZ=1.5MOhm, C1=0.3pF

11/1/2007 IEEE SSCS - Oct. 2007 23

Current Mode Buck – Error Amp

CRRRBW

RR

CsRsLG

LGBW

SEN

Z

Z

BWSENBW

121

111|)(|

:1|

1

1

π=

=⋅⋅≈

=

|settingby obtained

Complete Loop Transfer Function of Current Mode Buck:

)1)]((1[1

)]||(1[1

)(1

1

1

111

02 ZZomoC

ZC

XL

ESR

SSX

LSEN

L

RsCRRrgrsCRsCA

RRsCsCR

sQ

sRRR

RLG++++

+⋅

++

⋅+++

−=

ωω

• 1st zero of error amp placed near output filter pole

• ESR zero and 2nd pole of error amp are placed out of loop bandwidth

11/1/2007 IEEE SSCS - Oct. 2007 24


Voltage Mode Boost

L

C

S2VSW

RESR

RL

R1

R2

VREF

VRAMP

S

R

Q

QB

CLK

VFBVEA

VOUTVIN

CLK

VRAMP

VEA

VSW

VIN

ILIOUTD

D’

EA

S1D

RST

11/1/2007 IEEE SSCS - Oct. 2007 25

Voltage Mode Boost

Voltage Mode Boost Transfer Functions:

amplifiererror the of functiontransfer the is where

and

)(

)(1

)1()1(

11,)1(,)1(

1

)1)(1(

)1(1))1(

()1(

))1(

1)(1(

)1(

2

0

20

2

0

2

222

2

2

sa

saVv

d

LCRD

CL

RD

QL

DRLC

D

sQ

s

ss

DV

CRDR

LsD

LCs

DRLssCR

DV

dv

RFB

ESRL

LRHP

RHPZIN

ESRL

LESR

INO

=

−+−

=−

=−

=

++

−+

−=

++−

+−

−−+

−≈

ωω

ωω

ωω

11/1/2007 IEEE SSCS - Oct. 2007 26

Perturbation from Output to Inductor Current:

2)1( DsL

ivZ

o

oO −

==

)1()1(

)1()1(

DiiDII

sLvDiVDV

dtdiL

LoLO

oLOIN

L

−=⇒−=

−=⇒−−=

and

Impedance looking into the Inductor from Output:

Thus the Effective Inductance 2)1( DLLeff −

=

This makes the ω0 of the LC Filter to Move with D

Voltage Mode Boost - Effective Inductance

11/1/2007 IEEE SSCS - Oct. 2007 27

Voltage Mode Boost - RHP Zero

Perturbation from Duty Cycle to Output Current:

sLVdiVVDDV

dtdiL

DIdDiIdDiiDII

OLOININ

L

OLLLoLO

⋅≈⇒−−+=

−⋅−−=⋅−−=⇒−=

))(1(

1)1()1()1(

Right-Half-Plan Zero forms at frequency where:

LDR

DIdD

LjVd

LRHP

O

RHP

O

2)1(

|1

||)1(|

−=

−⋅=−

⋅

ω

ω

Right-Half-Plan Zero exists for both Voltage Mode and Current Mode Boost

11/1/2007 IEEE SSCS - Oct. 2007 28

Voltage Mode Boost

Example: L=2.2uH, C=10uF, RESR=10m Ohm, VIN=2.5V, VOUT=5V, 10V, 15V, IOUT=100mAFSW=1.5MHz

ω0 and ωRHP moves lower with increased duty cycle

Control (Duty Cycle) to Output Transfer Function:

11/1/2007 IEEE SSCS - Oct. 2007 29

Voltage Mode Boost – Type-III Error Amp

Usually Type-III Compensation Network is Required:

LCVVCR

BWLCsV

VCRBW

sQ

s

ss

DVV

CsRCsRCAsRCsRRsCALG

CCsRCsRCCAsRCRRsRsCA

vv

R

IN

BWR

IN

RHPZ

RHPZ

R

IN

FB

EA

⋅⋅=⇒=⋅⋅

++

−+

−⋅

+++++

−≈

++++++++

−≈

21

21

20

2

0

23122103

23110

131223103

223110

2111:

1

)1)(1(

)1()1)(1](1[)1)(1(

)||1)(1)]()(1(1[])(1)[1(

π

ωωωω

ωω

: and thanlower be to BWSet

EAVREF

VFB

VEA

R3

R2

R1

C2

C1

C3 Example Design Steps:1. Estimate worst case

ωRHP=300kHz 2. Set BW<100k:

R1C2<2.75µs3. Set both zeros near ω0:

R1=100k, C1=100pF, R3=300k, C2=20pF, ωz1=16.0kHz, ωz2=26.5kHz

4. Bandwidth: fBW= 80kHz5. Mid-band DC gain of 1/36. Set 2nd and 3rd pole to

beyond ωRHP :R2=10k, C3=3pFωp2=530kHz, ωp3=790kHz

11/1/2007 IEEE SSCS - Oct. 2007 30

Voltage Mode Boost – Type-III Error Amp

• Phase shift exceeds 180° at ω0 -> conditionally stable

• Move 1st zero lower to improve phase shift -> much larger C1

• Adjust C1 to move 1st zero• Adjust R3 to move 2nd zero and

mid-band gain• 2nd pole and 3rd poles suppress

high frequency noise

11/1/2007 IEEE SSCS - Oct. 2007 31


Current Mode Boost

C

S2VSW

RESR

RL

S1

R1

R2

VREF

VRAMP

S

R

Q

QB

CLK

VFBVEA

VOUTVIN

CLK

VRAMPVEA

VSWVIN

IL

IOUT

D

D

EA

Slope Comp

RSEN

RST

L

D’

RST

11/1/2007 IEEE SSCS - Oct. 2007 32

Current Mode Boost

)1(21

12

5.0)1)(1(

12

1

1

21

11)(

)2||]5.0)1)(1[(

()1(

12

1

11

21

2

2

1

2

mmDD

mmQ

T

sQ

sRRR

DsG

DTL

DmmT

LD

R

RRR

DviG

aa

SS

SSX

LSENm

SaS

X

X

LSENEA

om

−−=

−−+=

=

+++

−≈

−−+−=

+

−==

ππ

πω

ωω

:system pole-2 a in resultseffect sampling andDelay Buck ModeCurrent Peak toSimilar

where

C

RESR

RL

R1

R2

VREF

VFBVEA

VOUTVIN

EA

Gm IO

RX

Transfer Function of the Current Loop:

11/1/2007 IEEE SSCS - Oct. 2007 33

Current Mode Boost

Control to Output Transfer Function:

LDR

RRsC

ssCR

sQ

sRRR

RDZsGvv

LRHP

XL

ZRHPESR

SSX

LSEN

LOm

EA

o

2

2

)1(

)]||2

(1[

)1)(1(

)(1

1

21

12

)1()(

−=

+

−+⋅

+++

−=⋅=

ω

ω

ωω

Example: VIN=2.5VVOUT= 5V, 10V, 15V, 20VL=2.2uH, C=10uF RESR=10m OhmIOUT = 100mARSEN = 0.5 OhmFSW = 1.5MHz

11/1/2007 IEEE SSCS - Oct. 2007 34

Current Mode Boost – Error Amp Ex.

)1)]((1[1

)]||2

(1[

)1)(1(

)(1

1

21

12

)1()(11

02 ZZomoC

ZC

XL

ZRHPESR

SSX

LSEN

L

RsCRRrgrsCRsCA

RRsC

sssCR

sQ

sRRR

RDsT++++

+⋅

+

−+⋅

+++

−−= ω

ωω

Use the same error amp structure as on page 22:

The Complete Loop Transfer Function:

Generally Guideline:• To ensure loop stability, the unity-gain bandwidth is set to be

3-5x lower than the worst case RHP zero• The ESR zero and 2nd pole of the amplifier is placed higher than

the RHP zero• The current loop poles are usually much higher than RHP zero

EAVREF

VFB

R1

RZ

VEA

CC

C1

11/1/2007 IEEE SSCS - Oct. 2007 35

Current Mode Boost – Error Amp Ex.

Loop Bandwidth can be estimated as:

)1()()1(

3)1(

21

222

1

DBW,IV

VVVRDR

RR

CRDBW

OO

IN

O

INLLRHP

RHPZ

SEN

−∝⋅

==−∝

<≤⋅−

=

Since

shift) phase18 scontribute zero (RHP o

ω

ωπ

Bandwidth should be set at max. duty cycle and load

Example:VIN=2.5V, VOUT=5V, IO=500mAL=2.2uH, C=10uF, RSEN=0.5 Ohm, RZ=1M Ohm,ωZRHP=181kHz, BW chosen to be ~60kHzCalculate: R1:~300k Ohm

11/1/2007 IEEE SSCS - Oct. 2007 36

Current Mode Boost

Error Amplifier Example:R1=250k, RZ=1MCC=25pF, C1=0.3pF

Output Current:1mA, 10mA, 100mA, 500mA

Loop BW: ~60kHz

Complete Loop Transfer Function of Current Mode Boost Converter:

11/1/2007 IEEE SSCS - Oct. 2007 37

DC-DC Converter – Building Blocks

PWM ComparatorMulti-Stage Gain -> Faster For Small Input SignalBut, High-Gain Stage Has Longer Recovery TimeSo, Usually Low-Gain Amp(s) Followed by High-Gain Comparator

11/1/2007 IEEE SSCS - Oct. 2007 38

Building Blocks – PWM Comparator

OTA based comparator with pre-amps

INP INN

COMP OUT

11/1/2007 IEEE SSCS - Oct. 2007 39

Building Blocks – Error Amplifiers

Good:• Input Common Mode Down

to Ground• Smaller Input Offset than

OTA

But:• Difficult to get large Gm

INP

INNOUT

BIAS

Error AmplifiersFolded-Cascode Error Amplifier

11/1/2007 IEEE SSCS - Oct. 2007 40

Building Blocks – Error Amplifiers

Good:• Constant Gm Defined by R• Scalable Gm by Current

Mirrors

But:• Higher Input Offset due to

Even More Current Mirrors• Additional Gm Regulation

Loop

Constant Gm Error Amplifier

INPINN

I1 I1

I2I2

ROUT

11/1/2007 IEEE SSCS - Oct. 2007 41


Acknowledgement:Jian Zhou etc. for Review and Suggestions

Thank You For Your Attendance

DCDC Design Slides Ver2

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