dc to dc converter

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 9, SEPTEMBER 2012 3897

Novel Nonisolated High-Voltage Gain DC–DCConverters Based on 3SSC and VMC

Fernando Lessa Tofoli, Demercil de Souza Oliveira, Jr., Rene Pastor Torrico-Bascope,and Yblin Janeth Acosta Alcazar

Abstract—This paper introduces a new family of dc–dc convert-ers based on the three-state switching cell and voltage multipliercells. A brief literature review is presented to demonstrate someadvantages and inherent limitations of several topologies that aretypically used in voltage step-up applications. In order to verifythe operation principle of this family, the boost converter is cho-sen and investigated in detail. The behavior of the converter isanalyzed through an extensive theoretical analysis, while its per-formance is investigated by experimental results obtained from a1-kW laboratory prototype and relevant issues are discussed. Theanalyzed converter can be applied in uninterruptible power sup-plies, fuel cell systems, and is also adequate to operate as a high-gainboost stage with cascaded inverters in renewable energy systems.Furthermore, it is suitable in cases where dc voltage step-up isdemanded, such as electrical fork-lift, audio amplifiers, and manyother applications.

Index Terms—Boost converters, dc–dc converters, high voltagegain, voltage multiplier cells (VMCs).

I. INTRODUCTION

D EPENDING on the application nature, several types ofstatic power converters are necessary for the adequate

conversion and conditioning of the energy provided by primarysources such as photovoltaic arrays, wind turbines, and fuelcells. Besides, considering that the overall cost of renewable en-ergy systems is high, the use of high-efficiency power electronicconverters is a must [1].

The literature presents numerous examples for applicationswhere dc–dc step-up stages are necessary, e.g., audio amplifiers[2], uninterruptible power supplies (UPSs) [3], fuel cell poweredsystems [4], and fork lift vehicles [5], although many otherones can be easily found. Typical solutions include the use oflow-frequency or high-frequency power transformers to adjustthe voltage gain properly. Besides, galvanic isolation may benecessary due to safety reasons [6]. Unfortunately, this practice

Manuscript received November 21, 2011; revised January 30, 2012;accepted February 27, 2012. Date of current version May 15, 2012. This workwas supported in part by the Conselho Nacional de Desenvolvimento Cientıficoe Tecnologico (CNPq), Coordenacao de Aperfeicoamento de Pessoal de NıvelSuperior (CAPES), Fundacao de Amparo a Pesquisa do estado de Minas Gerais(FAPEMIG), and Fundacao Cearense de Apoio ao Desenvolvimento Cientıficoe Tecnologico (FUNCAP). Recommended for publication by Associate EditorJ. A. Pomilio.

F. L. Tofoli is with the Department of Electrical Engineering, Federal Uni-versity of Sao Joao del-Rei, Sao Joao Del-Rei, Minas Gerais 36307-352, Brazil(e-mail: [email protected]).

D. de Souza Oliveira, R. P. Torrico-Bascope, and Y. J. Acosta Alcazar are withthe Department of Electrical Engineering, Federal University of Ceara, Fort-aleza, Ceara 60020-181, Brazil (e-mail: [email protected]; [email protected];[email protected]).

Digital Object Identifier 10.1109/TPEL.2012.2190943

may bring increased size, weight, and volume if compared withnonisolated approaches such as the boost converter.

The conventional boost converter can be advantageous forstep-up applications that do not demand very high voltage gain,mainly due to the resulting low conduction loss and designsimplicity [7]. Theoretically, the boost converter static gain tendsto be infinite when duty cycle also tends to unity. However, inpractical terms, such gain is limited by the I2R loss in the boostinductor due to its intrinsic resistance, leading to the necessityof accurate and high-cost drive circuitry for the active switch,mainly because great variations in the duty cycle will affect theoutput voltage directly [8].

Due to the importance of the conventional boost converter inobtaining distinct and improved topologies for voltage step-upapplications, some techniques have been developed and modi-fied with the aim of improving the characteristics of the originalstructure. Basically, two strategies are adopted for this purpose:voltage step-up with and without using extreme values of dutycycle. Some arrangements available in the literature will be dis-cussed as follows.

Cascading one or more boost converters may be consideredto obtain high voltage gain. Even though more than one powerprocessing stage exists, the operation in continuous conduc-tion mode (CCM) may still lead to high efficiency [9]. Themain drawbacks in this case are increased complexity and theneed for two sets that include active switches, magnetics, andcontrollers. Besides, the controllers must be synchronized andstability is of great concern [10]. Due to high power levels andhigh output voltage, the latter cascaded boost stage has severereverse losses, with consequent low efficiency and high electro-magnetic interference (EMI) levels. Typical examples of suchtopologies are the single-switch quadratic boost converter andthe two-switch three-level boost converter [11].

Converters with magnetically coupled inductance such as fly-back or the single-ended primary inductance converter (SEPIC)can easily achieve high voltage gain using switches with re-duced on-resistance, even though efficiency is compromised bythe losses due to the leakage inductance [12]. An active clamp-ing circuit is able to regenerate the leakage energy, at the cost ofincreased complexity and some loss in the auxiliary circuit [13].

A hybrid boost–flyback converter is introduced in [14]. Theefficiency of the conventional flyback structure is typically lowdue to the parasitic inductance. A possible solution lies in con-necting the output of the boost converter to that of the flybacktopology, with consequent increase of voltage gain due to theexistent coupling between the arrangements. In this case, theboost convert behaves as an active clamping circuit when themain switch of the flyback stage is turned OFF.

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3898 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27, NO. 9, SEPTEMBER 2012

A boost converter using switched capacitors is proposed in[15], where high voltage gain can be obtained, but it is restrictedto low-power applications. In this case, the dc output voltage canbe increased as desired by adding a given number of capacitors.Low duty cycle is used, alleviating the problem of the boostdiode reverse recovery. However, the high component countwith distinct ratings is an inherent drawback.

As the power rating increases, it is often required to associateconverters in series or in parallel. In high-power applications,interleaving of two boost converters is usually employed toimprove performance and reduce size of magnetics. Besides,for high-current applications and voltage step-up, the currentsthrough the switches become just fractions of the input current.Interleaving effectively doubles the switching frequency andalso partially cancels the input and output ripples, as the sizeof the energy storage inductors and differential-mode EMI filterin interleaved implementations can be reduced [16]. The con-verter studied in [17] uses two boost topologies coupled throughan autotransformer with unity turns ratio and opposite polarityso that the current is equally shared between the switches. Be-sides, voltage doubler characteristic is achieved. Even thoughthe current stress through the switches is reduced, the respec-tive voltage stress is less than or equal to half the total outputvoltage. Isolated drive circuitry must also be employed in thiscase.

Other topologies using the interleaving technique are inves-tigated in [18]. Voltage multiplier cells (VMCs) are adopted toprovide high voltage gain and reduce voltage stress across thesemiconductor elements. Interleaving allows the operation ofthe multiplier stages with reduction of the current stress throughthe devices. Besides, the size of input inductors and capacitors isdrastically reduced. The voltage stress across the main switchesis limited to half of the output voltage for a single multiplierstage. However, high component count is necessary, with theaddition of a snubber circuit due to the sum of the reverse re-covery currents through the multiplier diodes and consequentincrease of conduction losses.

The converter described in [19] allows the increase of thestatic gain by cascading several VMCs that operate based on theresonance principle. It is also shown that the input inductance isthe same as that of a conventional boost converter. Even thoughswitching losses are minimized because there is zero-current-switching (ZCS) turn-on of the main switch, conduction lossestend to increase due to the circulating reactive energy.

The topology studied in [20] uses a voltage doubler recti-fier as the output stage of an interleaved boost converter withcoupled inductors. High voltage gain can be obtained, althoughefficiency is affected by the use of an resistor-capacitor-diode(RCD) snubber.

In the last few years, some converters based on the three-state switching cell (3SSC) have been proposed, and will bediscussed as follows. The 3SSC is obtained by the associationof two two-state switching PWM cells (2SSCs) interconnectedto a center tap autotransformer, from which a family of dc–dcconverters can be derived. This concept was first introducedin [21]. Some prominent advantages can be addressed to suchstructures, e.g., reduced size, weight, and volume of magnetics,which are designed for twice the switching frequency; the cur-

rent stress through each main switch is equal to half of the totaloutput current, allowing the use of switches with lower currentrating; losses are distributed among the semiconductors, leadingto better heat distribution and consequently more efficient useof the heat sinks; the drive circuit of the main switches becomesless complex because they are connected to the same referencenode [22].

The topology investigated in [23] uses VMCs associated withthe 3SSC, whose claimed advantages are the input current is con-tinuous with low ripple; the input inductor is designed for twicethe switching frequency, with consequent weight and volumereduction; the voltage stress across the switches is lower thanhalf of the output voltage, and naturally clamped by one outputfilter capacitor. As a disadvantage, a small snubber is necessaryfor each switch and one additional winding per cell is requiredfor the autotransformer [23].

The converter proposed in [24] presents high voltage gain,while the input current is continuous with reduced ripple. Theinput inductor is also designed for twice the switching fre-quency, implying reduction of weight and size. The voltagestress through the switches is less than half of the output voltagedue to clamping performed by the output filter capacitor. It isalso important to mention that, for a given duty cycle, the outputvoltage can be increased by adjusting the transformer turns ra-tio without affecting the voltage stress across the main switches.Metal oxide semiconductor field-effect transistors (MOSFETs)with reduced on-resistance can be used to further minimizeconduction losses. However, the converter cannot operate ad-equately when a duty cycle is lower than 0.5 due to magneticinduction issues. The hard commutation of switches and highcomponent count are also possible drawbacks.

An isolated converter, whose characteristics are similar tothose of the push–pull converter, is introduced in [25]. The use ofthe 3SSC is associated with the following advantages: utilizationof only one primary winding that allows the addition of a dccurrent blocking capacitor in series connection, in order to avoidthe transformer saturation problem; less copper and reducedmagnetic cores are involved during the transformer assembly;and the moderate leakage inductance of the transformer allowsthe reduction of overvoltage, and the commutation losses ofthe switches. The autotransformer of the 3SSC has small size,because it is designed for half of the output power and for a highmagnetic flux density, since the current through the windings isnearly continuous with low ripple [25].

This paper presents a topology for voltage step-up applica-tions based on the use of multiplier cells constituted by diodesand capacitors. The converter is able to operate in overlappingmode (when a duty cycle D is higher than 0.5) and nonoverlap-ping mode (when a duty cycle D is lower than 0.5), analogouslyto other 3SSC-based structures [4], [7], [21]–[25]. However, thestudy carried out in this paper only considers the operation withD > 0.5. The generic structure, which is valid for any numberof cells, is initially presented, while the analysis is focused onstructures with three cells, aiming to determine the stress re-garding the elements that constitute the aforementioned config-urations. Experimental results regarding the structure with threemultiplier cells are also presented and discussed to validate theproposal.

TOFOLI et al.: NOVEL NONISOLATED HIGH-VOLTAGE GAIN DC–DC CONVERTERS BASED ON 3SSC AND VMC 3899

Fig. 1. (a) Voltage multiplier cell. (b) Three-state switching cell. (c) Resulting cell.

II. PROPOSED TOPOLOGIES

For good operation of the VMC shown in Fig. 1(a), ac inputvoltage is required, which is an important requirement of thiscell. Due to this fact, the use of the 3SSC depicted in Fig. 1(b)is considered because it generates such ac voltage across theterminals of the autotransformer and the drain terminals of thecontrolled switches. For this reason, both cells are integratedleading to the proposed cell shown in Fig. 1(c). In the resultingcell, the controlled switches can be represented by MOSFETs,junction field-effect transistors, insulated gate bipolar transis-tors, bipolar junction transistors, etc. All the generated topolo-gies present bidirectional characteristics.

By using the proposed cell shown in Fig. 1(c), it is possible togenerate the six novel nonisolated dc–dc converters, i.e., buck,boost, buck–boost, Cuk, SEPIC, and zeta, which are shown inFig. 2.

As was mentioned before, the use of high-voltage gain con-verters is of great interest, even though many approaches arebased on isolated topologies [26]–[28]. It is worth to notice thatthe use of nonisolated converters particularly dedicated to appli-cations regarding renewable power systems has been the scopeof recent works [29]–[33]. The efforts leading to the develop-ment of such nonisolated topologies are then well justified inthe literature.

In order to verify the claimed advantages of the converterfamily, the boost converter shown in Fig. 2(b) is chosen. Thedeveloped analysis considers the converter associated with threevoltage multiplier cells and is detailed as follows.

In order to better understand the operating principle of thestructures, the following assumptions are made:

1) the input voltage is lower than the output voltage;2) steady-state operation is considered;3) semiconductors and magnetics are ideals;

4) switching frequency is constant;5) the turns ratio of the autotransformer is unity;6) the drive signals applied to the switches are 180◦

displaced.

A. Operating Principle

The configuration that uses three multiplier cells is repre-sented in Fig. 3. The equivalent circuits that correspond to theconverter operation and the relevant theoretical waveforms arepresented in Figs. 4 and 5, respectively.

First stage [t0 , t1] [see Fig. 4(a)]: Switches S1 and S2 areturned ON, while all diodes are reverse biased. Energy is storedin inductor L and there is no energy transfer to the load. Theoutput capacitor provides energy to the load. This stage finisheswhen switch S1 is turned OFF.

Second stage [t1 , t2] [see Fig. 4(b)]: Switch S1 is turned OFF,while S2 is still turned ON and diode D5 is forward biased. Thereis no energy transfer to the load as well. Inductor L stores energy,capacitors C1 and C3 are discharged, and capacitors C2 , C4 , andC6 are charged.

Third stage [t2 , t3] [see Fig. 4(c)]: Switches S1 and S2 remainturned OFF and ON, respectively. Diodes D3 and D7 are forwardbiased, while all the remaining ones are reverse biased. Energyis transferred to the output stage through D7 . The inductor storesenergy, and capacitors C2 and C4 are still charged. CapacitorsC1 is discharged, and so are C3 and C5 .

Fourth stage [t3 , t4] [see Fig. 4(d)]: Switch S2 remains turnedON, diode D3 is reverse biased, and diode D1 is forward biased.Energy is transferred to the load through D7 . The inductor isdischarged, and so are capacitors C1 , C3 , and C5 , while C2 ischarged.

Fifth stage [t4 , t5] [see Fig. 4(e)]: This stage is identical tothe first one.


Fig. 2. Nonisolated dc–dc converters using the 3SSC and VMC: (a) buck, (b) boost, (c) buck–boost, (d) Cuk, (e) SEPIC, and (f) zeta.


Fig. 3. Proposed boost converter using three VMCs.

Sixth stage [t5 , t6] [see Fig. 4(f)]: Switch S2 is turned OFFand switch S1 is still turned ON. Diode D6 is forward biased.The inductor is charged by the input source, although capacitorsC2 and C4 are discharged instead.

Seventh stage [t6 , t7] [see Fig. 4(g)]: This stage is similar tothe third one.

Eighth stage [t7 , t8] [see Fig. 4(h)]: Switch S1 is turned ON,while S2 remains turned OFF. Diodes D2 and D8 are forward bi-ased, while D4 is reverse biased as well as the remaining diodes.Energy transfer to the load occurs through D8 , and capacitor Co

is still charged. The inductor is discharged, while capacitor C1is charged and capacitors C2 , C4 , and C6 are discharged.

B. Static Gain

The static gain for the generic structure of the boost convertercan be obtained from the inductor volt–second balance. Thevoltage area multiplied by the time interval that correspondsto the inductor charge is equal to that regarding the inductordischarged. The following expression can then be derived:

Gv =Vo

Vi=

(mc + 1)(1 − D)

(1)

where mc is the number of voltage multiplier cells; Vi is theinput voltage; Vo is the output voltage; and D is the duty cycle.

Expression (1) is plotted and shown in Fig. 6, where one cansee that the static gain changes when D<0.5, as represented bythe dotted line. It occurs because the multiplier capacitors arenot fully charged due to the reduced charge time.

III. DESIGN PROCEDURE

According to Fig. 6, the static gain of the proposed noniso-lated boost converter can be further increased by adding VMCsas necessary, with consequent reduction of voltage stress acrossthe main switches. However, this practice may lead to high com-ponent count and also compromise robustness considering thatadditional diodes and multiplier capacitors are included in the

Fig. 4. Operating stages: (a) first stage, (b) second stage, (c) third stage, (d)fourth stage, (e) fifth stage, (f) sixth stage, (g) seventh stage, and (h) eighthstage.


Fig. 5. Main theoretical waveforms.

Fig. 6. Static gain curves.

original topology, as seen in Fig. 3. Increased conduction andswitching losses are also of major concern in this case.

Even though a simpler arrangement with two VMCs couldbe considered instead, a design example of the proposed 3SSCboost converter with three cells is presented as follows. It willbe also shown that the converter achieves high efficiency over awide load range.

The specifications are listed in Table I and were used inthe implementation of an experimental prototype. Some im-portant calculations are performed in order to evidence theloss mechanism. It is also worth to mention that both conduc-tion and commutation losses are estimated under the rated loadcondition.

TABLE IDESIGN SPECIFICATIONS

A. Preliminary Calculation

The maximum input power is

Pi =Po

η= 1052.3W. (2)

The maximum duty cycle is obtained using (3) as follows:

Dmax =Vo − Vi(min) · (mc + 1)

Vo= 0.58. (3)

The average and maximum values of the input current aregiven by (4) and (5), respectively

IL(avg) = Ii(avg) =Po

Vi(min) · η= 25.06A (4)

IL(max) =Po

Vi(min) · η+

ΔIL

2= 26.94A. (5)

B. Inductor

Besides, the normalized ripple current β as a function of theduty cycle is given by

β =2 · L · ΔIL · fs

Vo=

(1 − D) · (2D − 1)(mc + 1)

. (6)

Expression (6) is plotted in Fig. 7, where it can be seen thatfor curve mc = 3 and duty cycle D = 0.75 the maximum normal-ized ripple current is β= 0.03125. The respective inductance iscalculated from (7) as

L =Vo · β

2 · fs · ΔIL

∼= 70μH. (7)

The core loss in the inductor is given by [35]

PL(core) = ΔB2.4 ·(KH · fL + KE · f 2

L

)· Ve = 0.075W

(8)where ΔB = 0.045 T is the magnetic flux variation; KH =4×10−5 is the hysteresis loss coefficient; fL = 2·fs = 50 kHz isthe operating frequency of the inductor; KE = 4×10−10 is the


Fig. 7. Normalized ripple current as a function of the duty cycle.

eddy-current loss coefficient; and Ve = 42.50 cm3 is the volumeof Thornton core NEE-55/28/21.

The copper loss in the inductor is

PL(copper) =ρ · lt · NL · I2

L(rms)

nL · Sf= 2.89W (9)

where ρ = 2.078×10−6 Ω·cm is the copper resistivity at 70 ◦C;lt = 11.6 cm is the average length of one turn; NL = 15 is thenumber of turns of the inductor; IL (rms) = 25.06 A is the rmscurrent through the inductor; nL = 62 is the number of wiresin parallel; Sf = 0.001287 cm2 is the cross-sectional area ofcopper wire AWG26.

C. Autotransformer

The active power processed by the high-frequency auto-transformer is obtained similarly to that processed by its low-frequency counterpart, as demonstrated in [34]. Besides, it hasbeen shown that it corresponds to half of the total output power.The design procedure of such a magnetic element is analogousto that for the transformer of a conventional full-bridge con-verter [35], i.e.,

AeAw =Pi/2

KT · KU · KP · Jmax · ΔBmax · 2 · fs· 104

= 12.22 cm4 (10)

where AeAw is the core area product; KT = 1 is the topologyfactor; KU = 0.4 is the window utilization factor; KP = 0.41 isthe primary winding utilization factor; Jmax = 350 A/cm2 is themagnetic flux density; ΔBmax = 0.15 is the maximum magneticflux variation; and fs = 25 kHz is the operating frequency of thetransformer.

Core NEE-65/33/26 manufactured by Thornton is then cho-sen, whose characteristics are as follows: Ae = 5.32 cm2 is theeffective core cross-sectional area; Aw = 3.7 cm2 is the windowarea considering the former coil; AeAw = 19.68 cm4 ; and VE

= 78.2 cm3 is the core volume.The number of turns for the autotransformer windings is

NT =Vi min

2 · (1 − Dmax) · Ae · ΔBmax · 2 · fs· 104

≥ 12.53 turns. (11)

Considering the presence of the skin effect, the maximumdiameter of the conductor used in the windings must be lowerthan [36]

df = 2 · 6.62√fs

= 2 · 6.62√25 × 103

= 0.084 cm. (12)

The core loss in the autotransformer is given by

PT (core) = ΔB2.4 ·(KH · fT + KE · f 2

T

)· VE = 2.4714W

(13)where ΔB = 0.15 is the magnetic flux variation; KH = 4×10−5

is the hysteresis loss coefficient; KE = 4×10−10 is the eddy-current loss coefficient; and Ve = 78.2 cm3 is the core volume.

The copper loss in the windings of the transformer is

PT (copper) =2 · ρ · lT · NT · I2

T (rms)

nT · Sf= 4.90W (14)

where ρ = 2.078×10−6 Ω·cm is the copper resistivity at 70 ◦C;lT = 14.24 cm is the average length of one turn; nT = 28is the number of wires in parallel; Sf = 0.001287 cm2 is thecross-sectional area of copper wire AWG26; and NT = 19 is thenumber of turns.

D. Capacitors

The multiplier capacitors Cn and the output capacitor Co canbe obtained from the following expressions:

Cn = Cn+1 =(mc − n + 1)

8Ii(avg) · (1 − Dmax)

fs · ΔVC k

for n = 1, 2, 3, and mc = 3

C1 = C2 ∼= 4.5μF C3 = C4 ∼= 3.0μF

C5 = C6 ∼= 1.5μF (15)

Co∼= Io · (2Dmax − 1)

ΔVC o · 2 · fs

∼= 2μF for pure resistive load. (16)

In standalone applications, an inverter is typically connectedto the output of the high-gain dc–dc converter. Considering thistype of application, a 470 μF/450 V capacitance was adoptedfor the filter capacitor Co .

E. Main Switches

The maximum voltage across the main switches S1 and S2 ,diodes D7 and D8 , and multiplier capacitors C1 . . .C6 is given by(17) which is valid when the ripple voltage across the capacitorsis neglected:

VS1−S2 = VC 1−C 6 = VD7−D8 =Vi(min)

(1 − Dmax)= 114.28V.

(17)The average current and the rms current through the switches

are given by (18) and (19), respectively

IS1(avg) = IS2(avg) =18· (Dmax + 3)IL(max)

= 11.21A (18)


IS1(rms) = IS2(rms) =IL(max)

24.√

3 (101 − 53Dmax)

= 15.16A. (19)

MOSFET IRFP4227 is then chosen as the main switch, whosecharacteristics are as follows: drain to source voltage VDS =200 V; diode forward voltage V(F ) = 1.3 V; drain current ID =46 A at Tc = 100 ◦C; on resistance RDS (on) = 37.9 mΩ at Tj

= 100 ◦C; rise time tr = 20 ns; fall time tf = 31 ns.The conduction loss regarding each main switch is obtained

from

PS1...S2(cond.) = RDS (on) · I2S1(rms) = 8.71W. (20)

The switching loss during turn ON and turn OFF for a singleswitch is

PS1...S2(sw .) =fs

2· (tr + tf ) · IS1(avg) · VS1 = 0.837W.

(21)

F. Diodes

The maximum peak reverse voltage (PIV) across diodes D7and D8 is given by (17). On the other hand, the maximum peakreverse voltage across diodes D1 . . .D6 is obtained from

VD1−D6 = 2 · VD7−D8 = 228.571V. (22)

The average currents through diodes D1 . . .D8 are given as

ID1...D8(avg) =Io

2= 1.25A (23)

Ultrafast diode MUR460 is then chosen, whose characteristicsare as follows: reverse voltage VD (rev .) = 600 V; forward volt-age VD (F ) = 1.28 V; average forward current IF = 4 A; reverserecovery time trr = 50 ns.

The estimated conduction losses regarding each diode are

PD1(cond.)−D8(cond.)∼= VD (F ) · ID1(avg)

∼= 1.6W. (24)

Switching losses regarding the diodes are given by

PD1...D6(sw .) =12

(VD (F )P − VD (F )

)ID1(avg)trisefs

+ VD1Qrrfs = 0.572W (25)

PD7...D8(sw .) =12

(VD (F )P − VD (F )

)ID7(avg)trisefs

+ VD7Qrrfs = 0.286W (26)

where VD (F )P = 1.5 V is the maximum value assumed by theforward voltage, trise = 18 ns is the rise time of the currentthrough the diode, and Qrr = 100 nC is the amount of chargestored in the intrinsic capacitance of the diode.

The estimated total loss of the converter is

Ptotal = PLb(core) + PL(copper) + PT (core) + PT (copper)

+ 2 · PS1...S2(cond.) + 2 · PS1...S2(sw .)

+ 8 · PD1...D8(cond.) + 6 · PD1...D6(sw .)

+ 2 · PD7...D8(sw .) = 46.234W. (27)

TABLE IIPROTOTYPE SPECIFICATIONS

Fig. 8. Photograph representing the experimental prototype.

Therefore, the estimated theoretical efficiency under the ratedload condition is obtained from

ηtheor. =Po

Po + Ptotal· 100 ∼= 95.58%. (28)

IV. EXPERIMENTAL RESULTS

An experimental prototype for the structure with three mul-tiplier cells has been designed according to the previous guide-lines and implemented in laboratory. The components used inthe prototype are listed in Table II and a picture is shown inFig. 8.


Fig. 9. Current and voltage waveforms for inductor L: (CH1) 40 V/div,5 μs/div; (CH2) 5 A/div, 5 μs/div.

Fig. 10. Current and voltage waveforms for the primary winding of the auto-transformer: (CH1) 40 V/div, 5 μs/div; (CH2) 2.5 A/div, 5 μs/div.

Fig. 9 shows the waveforms regarding inductor L, where itcan be seen that the ripple current is 6 A. The voltage across theinductor varies from −22 to +42 V in Fig. 9.

The voltage and current stresses regarding the autotrans-former windings are similar because the number of turns isexactly the same. Therefore, current is equally shared in twohalves of the current through inductor L. The ripple current inFig. 10 is approximately 3.5 A. The peak voltage across eachwinding is equal to half that across the switch and varies from−76 to +76 V. Besides, the average voltage across each windingis null.

Fig. 11 represents the commutation of switches S1 and S2 .The voltages across the switches are approximately the same,although 180◦ displaced. The maximum voltage across theswitches is 140 V, which is very close to the theoretical cal-culation. It can be seen that the voltage across the switch islower at the beginning of the turning-off process. The currentthrough switch S1 is discontinuous due to the commutation ofthe multiplier diodes, as predicted in the theoretical analysis.Besides, the current peak is equal to the inductor current, i.e.,30 A.

Fig. 12 presents the voltages across the multiplier diodes D1 ,D3 , D5 , and D7 . The voltages across diodes D1 , D3 , and D5 varyfrom 200 to 250 V due to the presence of adjacent capacitors. Onthe other hand, the voltage across diode D7 is about 140 V dueto the absence of such components. Due to the voltage ripple

Fig. 11. Voltage across switches S1 and S2 , and current through switch S1 :(CH3)(CH4) 50 V/div, 5 μs/div; (CH2) 10 A/div, 5 μs/div.

Fig. 12. Voltage waveforms across multiplier diodes: (CH1)(CH3) 100 V/div,10 μs/div.

Fig. 13. Efficiency as a function of the output power.

across the capacitors, experimental waveforms show that themaximum voltages across all diodes are less than that predictedin expressions (14) and (19).

Finally, the efficiency curve of the topology designed andimplemented according to Tables I and II is depicted in Fig. 13.Maximum efficiency regarding the converter is 97.9%, whilegood performance is also verified for the entire load range. Forinstance, efficiency is 95.3% at rated load.


V. CONCLUSION

This paper has proposed six generalized nonisolated high-gain voltage dc–dc converters. To verify the principle operationof the generated structures, the boost converter was chosen.The topology is adequate for several applications such as photo-voltaic systems, fuel cell systems, and UPSs, where high voltagegain between the input and output voltages is demanded.

An important characteristic that can be seen in the experimen-tal results is the reduced blocking voltages across the controlledswitches compared to similar circuits, allowing the utilization ofMOSFETs with reduced on-resistance. Besides, the advantagesof the 3SSC are also incorporated into the resulting topology,e.g., the current is distributed among the semiconductors. Fur-thermore, only part of the energy from the input source flowsthrough the active switches, while the remaining part is di-rectly transferred to the load without being processed by theseswitches, i.e., this energy is delivered to the load through passivecomponents, such as the diodes and the transformer windings.

The qualitative analysis, theoretical analysis, losses model-ing, and experimental results for a 1-kW prototype have beendiscussed. The converter achieves about 95.3% efficiency atrated load if compared to similar configurations that were pre-viously proposed in the literature. It is also expected that non-isolated converters based on the 3SSC and VMC may be com-petitive solutions for high-current-high-voltage-step-up appli-cations if compared with some other isolated approaches.

ACKNOWLEDGMENT

The authors would like to thank “CM Comandos LinearesLtda” for supplying samples.

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Fernando Lessa Tofoli was born in Sao Paulo,Brazil, on March 11, 1976. He received the B.Sc.,M.Sc., and Ph.D. degrees in electrical engineer-ing from the Federal University of Uberlandia,Uberlandia, Brazil, in 1999, 2002, and 2005,respectively.

He is currently a Professor with the FederalUniversity of Sao Joao Del-Rei, Sao Joao Del-Rei, Brazil. His research interests include power-quality-related issues, high-power factor rectifiers,and soft-switching techniques applied to static power

converters.

Demercil de Souza Oliveira, Jr., was born inSantos, Sao Paulo, Brazil, in 1974. He receivedthe B.Sc. and M.Sc. degrees in electrical engi-neering from the Federal University of Uberlandia,Uberlandia, Brazil, in 1999 and 2001, respectively,and the Ph.D. degree from the Federal University ofSanta Catarina, Florianopolis, Brazil, in 2004.

He has been a Researcher in the Group of PowerProcessing and Control and professor since 2004 atthe Federal University of Ceara, Fortaleza, Brazil.His research interests include static power convert-

ers, soft commutation, and renewable energy applications.

Rene Pastor Torrico-Bascope received the B.Sc. de-gree in electrical engineering from San Simon Uni-versity, Cochabamba, Bolivia, in 1992, and the M.Sc.and Ph.D. degrees in electrical engineering from theFederal University of Santa Catarina, Florianopolis,Brazil, in 1994 and 2000, respectively.

He is currently a Professor in the Department ofElectrical Engineering, Federal University of Ceara,Fortaleza, Brazil. His main research interests includepower supplies, power factor correction techniques,uninterruptible power systems, and renewable energy

systems.

Yblin Janeth Acosta-Alcazar received the BSc. de-gree in electrical engineering from San Simon Uni-versity of Cochabamba, Bolivia, in 2003. She was avisiting scientist at Delft University of Technologyin 2001. She obtained the MSc. degree in ElectricalEngineering from the Federal University of Ceara,Fortaleza, Brazil, in 2010.

Currently, she is a Design Engineer working in thefield of control systems. Her main research interestsinclude converters for renewable energy sources andcontrol systems.

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