DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays SDW 2005 June...

June 2005, R. PhilbrickBall Aerospace & Technologies Corp. 1 of 19

DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays

SDW 2005

• Background

• Channel Potential Test

• DC Gain Test

• Summary

OutlineOutline

R. Philbrick & M. Blouke

Ball Aerospace & Technologies Corp.



SDW 2005

• Problem: How to quickly and accurately qualify scientific

grade CCDs prior to integration into complex packages

and/or multi-chip focal plane arrays (e.g. HiRISE and

NPOESS-OMPS )?

• Full functional (a.k.a. EO or AC) characterization of

incoming CCD detectors can sometimes only be performed

after expensive package assembly steps have been

completed

– Discovering CCD tolerance issues after complex packaging steps

is expensive and can significantly impact development schedules

• EO testing alone does not adequately reveal all potential

problems

– For example, if th and/or Vin for one clock phase significantly

differs from the other clocks or inadequate tolerance range

• Performing thorough DC characterization is an effective way

to quickly and accurately qualify CCDs

Background:

HiRISE Multi-Detector FPA

NPOESS-OMPS FPA



SDW 2005

• The DC tests of most interest in detector screening are:

– ContinuityContinuity Yields pin-to-pin resistance, verifies process, checks for gross ESD damage, and verifies detector arrived without damage

– Leakage CurrentLeakage Current Yields static current draw on each gate, checks for subtle ESD damage, and verifies detector arrived without latent damage

– Diode BreakdownDiode Breakdown Verifies process, and confirms adequate operating margins on drain biases (e.g. OD, RD, and ID)

– Diode / OpensDiode / Opens Checks for open circuits (e.g. bad/missing wirebonds), verifies diode operation, and checks for intra-layer continuity (e.g. poly 1 to poly 1)

– Channel PotentialChannel Potential Yields threshold potential and inversion voltage for each gate, verifies

optimal clock and bias operating points, and confirms tolerance ranges

– DC GainDC Gain Verifies amplifier operating point and voltage tolerance ranges

Background:



SDW 2005

Channel Potential Test:

• Channel Potential (CP) testing yields the threshold potential (th) and inversion voltage (Vin) under many, sometimes all, gates on a CCD detector

– These two parameters are key for establishing clock and bias operating levels and tolerances

• The basic CP measurement requires a gate surrounded by two drains

– One drain is statically biased on (“Source” in figure)– A small current is sourced into the other drain (“Drain” in

figure), which electrically “floats” to the potential under the controlling gate

• Voltage on gate of interest is swept and the “Drain” voltage (i.e. the gate channel potential) is measured

• Channel potential testing yields the most information on CCDs with 3 or 4 architectures, but CCDs with 2 architectures can also yield significant data

• Channel Potential (CP) testing can be performed to some extent on almost all CCD detectors

– Most CCD vendors monitor CP test structures on wafers but significant differences from actual CCD data can exist

Basic channel potential measurement on a MOSFET

SiO2

Source DrainGate

A

A'

VGate

0VIN

TH

A' A

Typical channel potential curve



SDW 2005

• All gates in between the measurement drains, other than the gate being measured, must be turned “on” so they don’t influence results

• Other measurement paths must be removed by turning “off” some gates

– e.g. If measuring SWA and using two RD drains on either side of the serial register, the parallel register clocks need to be “off”

• Typical measurement current is 20 nA

– To high a value can induce a significant I.R voltage drop


RDB RDA

RGB OGB SWB R1 R2 R3 R1 R2 R3

. . .

SWAOGA RGA

+- v

SS

+ -

+ -

VRDB

VSWA

VON

ILOAD

I1 I2 I3

VOFF+-

R01 R02 R03

I01

I01

I03

SWA

RGA

RDA

OGA

RGB

RDB

OGB SWB

Measurement Path

VRDBVOFF

+-

ILOAD

VON+-VSWA

v

+-

+-

Channel potential setup for Summing Well A (SWA) gate using two amplifier RD drains



SDW 2005


• Using CP data and design tolerances, complete CP diagrams for the entire CCD can be easily generated

• Example here uses +/- 0.1 v design tolerance

• Accurately quantifying changes in th as a function of radiation exposure level is needed for space-based applications

Note the significant shift in serial phase 2 (R2) CP from other serial phases

16.85

3.50

17.10

5.75

16.40

16.60

3.50

16.65

5.75

16.90

7.40

7.60

18.90

19.10

7.65

7.85

19.15

19.35

9.25

9.45

16.40

16.60

8.50

8.70

17.50

17.70

7.40

7.60

18.90

19.10

7.00

7.20

5.90

6.10

10.90

11.10

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Ch

an

ne

l Po

ten

tia

l

Serial CCD Channel Potential Diagram

I4 R2 RDOGR4R3 FD RSTR1ID

I4 R2 RDOGR4R3 FD RSTR1ID

SUB = 0V

IG

IG



SDW 2005

• Test measures the small signal gain of each on-chip amplifier by sweeping the reset drain voltage (with reset gate on) and measuring the resultant DC output voltage

– Output MOSFET is biased using a constant current load of typically 2 mA

• Small signal gain is calculated using

• Typical DC gain values range between 0.5 and 0.8 depending on the amplifier configuration (e.g. 1, 2, or 3 stages)

• DC gain or equivalent measurements are generally not possible on CMOS based detectors since access to the internal circuitry is limited

DC Gain Test:

DC Gain Measurement Setup RD

OS

in

outDC V

V

dV

dVG

DC gain test equivalent circuit

RD

ILOAD v

RG

SUB

OS

OD

+-

+-

+-



SDW 2005

DC Gain Test:

• Any type of CCD charge-to-voltage amplifier can be measured (e.g. single stage, dual stage, and AC coupled stage)

• Optimal operating point and adequate bias tolerances can be quickly verified (both pre and post radiation)

• “Bad” MOSFETs can be quickly identified

Common CCD Output Amplifier Configurations: (a) Single-Stage Source Follower, (b) Two-Stage Source Follower, (c) Two-Stage Source Follower with

Bias Control, and (d) AC Coupled, Two-Stage Source Follower

Q1

Q2

Q3

Q4

OS

OD

SS

RG

RD

Q1

Q2

Q3

OS

OD

SS

RD

Q1

Q2

Q3

Q4

OS

OD

SS

RD

RGRG

D1D1

D1

CCD On-chip amplifier

CCD On-chip amplifierCCD On-chip amplifier

Q1

Q2

Q3

Q4

OS

OD

SS

RG

RD

D1

CCD On-chip amplifier

I1

Q5

LG

(a) (b)

(c) (d)



SDW 2005

• A typical input (RD) versus output (OS) curve is shown at right along with small signal gain

• Slope of small signal gain curve around operating point gives a measure of the low frequency linearity response

DC Gain Test:

VRD

GA

INVRG-CUT

VQ5-OFF

Example of DC gain curve for AC coupled two stage amplifier

VRD

VOS

VRG-CUT

VRD

GAIN

VRG-CUT

RD

OS

in

outDC V

V

V

VG

Output Response and Small Signal Gain for a typical DC coupled amplifier

• AC coupled amplifiers yield a slightly different shaped DC gain curve due to the presents of the line reset MOSFET

– Two distinct cutoff points are observed• Line reset MOSFET cut off point• Reset MOSFET cut off point

– Gate of line reset MOSFET should be held “off” during the entire scan

Direction of Increasing

Signal



SDW 2005

VRD

GA

INVRG-CUT

Example of bad recommended DC operating point

• Some examples of problems identified during DC testing

– ESD damage occurring during packaging/shipping

– Processing problems (e.g. low diode breakdowns)

– Non-optimal amplifier operating point

– Non-optimal bias levels (e.g. OG, RD or OD)

– Inadequate bias tolerances • To account for variability in electronics design, within CCD

population, or resulting from post radiation shifts

Summary:

Example of bad recommended OD bias point Example of gate to gate channel potential variability

VGate

0VINV Range

TH

Phase 1

Phase 2

VendorRecommendedOperating Point

PreferredOperating

Point

Range

Non-Optimal OD Operating Point

DC Characterization of CCD-Based Detectors for Use in Multi-Chip Focal Plane Arrays SDW 2005 June...

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