DC Bus Current Ripple Management in Single Phase PWM Inverters · 2013-12-26 · dc: DC bus voltage...
Transcript of DC Bus Current Ripple Management in Single Phase PWM Inverters · 2013-12-26 · dc: DC bus voltage...
DC Bus Current Ripple Management in
Single Phase PWM Inverters
A Project Report
Submitted in Partial Fulfilment of
Requirement for the Degree of
Master of Engineeringin
Electrical Engineering
By
Vishnu M
Department of Electrical Engineering
Indian Institute of Science
Bangalore - 560 012
India
June 2013
Acknowledgements
I express my deep sense of gratitude to my supervisor Dr. Vinod John for giving me an
opportunity to work in the field of Power Electronics. His great patience and constant
support have immensely helped me throughout the course of this project.
I thank Dr. G. Narayanan for teaching me the basics of Power Electronics. His lectures
have deeply influenced me and the way I look at things.
I am thankful to all the professors in IISc for their wonderful lectures. I thank MHRD
for the financial support during the course of my study.
I am grateful to Abhijith, Anirudh, Neeraj, Rakesh and Shamveel for the lively discussions
which I had with them. Their suggestions and support are deeply acknowledged. I thank all
the other members of the Power Electronics Group for their help and support.
I would like to thank Mr. Channegowda, Mr. Purushothama and Mr. Jagannath Kini
for their help in administrative matters. I really appreciate the help given by Mr. Devaraja,
Mr. Erwin Samuel Paul and Mr. Victor Balasubramanian.
Finally, I express my sincere gratitude to my parents and my sister. Their faith in me,
their encouragement and support are the the reason for whatever I have achieved in my life.
i
Abstract
Pulse Width Modulation(PWM) Converters are increasingly being used for AC-DC power
conversion as they have the capability to meet the stringent limits on current harmonics
injected to the utility. But the main problem associated with single phase PWM converters
is the low frequency DC bus ripple current.
When a battery or a Distributed Generation (DG) source is connected to the DC bus,
the low frequency ripple can cause serious issues like overheating of the battery, non-optimal
operation of the DG unit, etc. The DC ripple currrent reduces the efficiency and durability
of DG sources like fuel cell stack. The low frequency ripple has to be maintained under
certain standards which may be specified by the battery manufacturer or may be selected
based on the type of DG source.
The vaious filtering options for DC bus current ripple management such as tuned LC
filters, coupled inductor based filters and active filters were studied. This project has come
up with a novel hybrid filter topology for mitigating the low frequency current ripple in the
DC bus of a PWM converter. Control strategy for the proposed filter has been analytically
derived and it has been observed that this does not compromise the performance of the main
converter. The proposed circuit has been tested and validated on a 150 VA hardware.
ii
Contents
Acknowledgements i
Abstract ii
List of Tables v
List of Figures vi
Nomenclature ix
1 Introduction 1
1.1 Contributions of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Ripple Filtering 3
2.1 Passive Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1.1 Storing Ripple Energy in Electrostatic Field . . . . . . . . . . . . . . 3
2.1.2 Storing Ripple Energy in Electromagnetic Field . . . . . . . . . . . . 4
2.1.3 Storing Ripple Energy Using Both Inductor and Capacitor . . . . . . 4
2.1.3.1 Passive LC filter . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1.3.2 Coupled Inductor based Filter Configurations . . . . . . . . 5
2.2 Active Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Proposed Hybrid Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Ripple Analysis and Compensation Current 10
3.1 Analysis of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
iii
Contents iv
3.1.1 Main Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.2 Compensation Current for Ripple Cancellation . . . . . . . . . . . . . 11
3.1.3 Validity of the Proposed Strategy . . . . . . . . . . . . . . . . . . . . 12
3.2 Selection of Filter Components . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.2.1 Selecting Filter Capacitance, C1 . . . . . . . . . . . . . . . . . . . . . 13
3.2.2 Selecting Cdc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2.3 Selecting Filter Inductance, L . . . . . . . . . . . . . . . . . . . . . . 15
3.2.4 Choosing Vdc2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4 Control Strategy 16
4.1 Single Phase PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.1 Second Order Generalized Integrator(SOGI) . . . . . . . . . . . . . . 17
4.2 Control Scheme of the Converter . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.1 Main Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.2.2 Auxilliary Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.3 Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.4 Digital Implementation of Controllers . . . . . . . . . . . . . . . . . . . . . . 21
5 Results 24
5.1 SOGI based PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.2 Main Converter - Standalone mode with current control . . . . . . . . . . . . 26
5.3 Main Converter - Grid Interactive Mode . . . . . . . . . . . . . . . . . . . . 27
5.4 Auxilliary Converter - Grid Interactive Mode . . . . . . . . . . . . . . . . . . 28
5.5 DC Bus Current Ripple Reduction . . . . . . . . . . . . . . . . . . . . . . . 29
5.5.1 STATCOM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.5.2 ZPF Lag Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.5.3 AFEC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.6 Summary of Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.7 Comparison of Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6 Conclusion 38
References 39
List of Tables
3.1 Closed form expression for compensation current . . . . . . . . . . . . . . . . . . . . 14
4.1 Controller Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1 Circuit Parameters of main converter for standalone mode . . . . . . . . . . . . . . . 26
5.2 Circuit parameters of main converter for grid interactive mode . . . . . . . . . . . . . 27
5.3 Circuit parameters of auxilliary converter for grid interactive mode . . . . . . . . . . . 28
5.4 Circuit parameters used in the proposed topology . . . . . . . . . . . . . . . . . . . 29
5.5 Peak value of DC bus ripple current . . . . . . . . . . . . . . . . . . . . . . . . . . 36
5.6 Comparison of proposed filter with other filters for a 1 KVA system . . . . . . . . . . . 36
v
List of Figures
1.1 Schematic diagram of a grid connected PWM converter with proposed filter . . . . . . . 2
2.1 Capacitive filter for DC ripple filtering . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Tuned passive LC filter for DC ripple filtering . . . . . . . . . . . . . . . . . . . . . 5
2.3 (a)Directly coupled configuartion-I (b) Inversely coupled configuration-I (c) Directly cou-
pled configuartion-II (d) Inversely coupled configuration-II . . . . . . . . . . . . . . . 5
2.4 Directly coupled configuartion-I . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.5 Inversely coupled configuration-I . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.6 Directly coupled configuartion-II . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.7 Inversely coupled configuration-II . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.8 Inductive filter for DC ripple filtering - Active filtering approach . . . . . . . . . . . . 8
2.9 PWM converter with the proposed hybrid filter . . . . . . . . . . . . . . . . . . . . 8
3.1 Main converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Auxilliary converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 (a) Choosing filter inductor, L based on modulation index: Sample curve, (b) Compensation
current to be pumped through the filter inductor, L . . . . . . . . . . . . . . . . . . 15
3.4 Effect of Vdc2 on filter VA rating: Sample curve . . . . . . . . . . . . . . . . . . . . 15
4.1 Single phase PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Second Order Generalized Integrator(SOGI) . . . . . . . . . . . . . . . . . . . . . . 17
4.3 Control scheme of the proposed circuit topology. . . . . . . . . . . . . . . . . . . . . 18
4.4 Block diagram of the current control scheme . . . . . . . . . . . . . . . . . . . . . . 19
4.5 Block diagram for DC voltage regulation . . . . . . . . . . . . . . . . . . . . . . . 20
4.6 SOGI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
vi
List of Figures vii
4.7 Resonant part of PR controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1 PLL outputs when input is clean: Vpll - PLL input(scale: 2V/div), cosθ - Quadrature unit
vector(scale: 5V/div), sinθ - In phase unit vector(scale: 5V/div) . . . . . . . . . . . . 24
5.2 PLL outputs when input is distorted and has DC offset: Vpll - PLL input(scale: 2V/div),
cosθ - Quadrature unit vector(scale: 5V/div), sinθ - In phase unit vector(scale: 5V/div) . 25
5.3 PLL outputs when input frequency varies: Vpll - PLL input(scale: 2V/div), cosθ - Quadra-
ture unit vector(scale: 5V/div), sinθ - In phase unit vector(scale: 5V/div) . . . . . . . . 25
5.4 Vpll - PLL input(scale: 2V/div), θ - Estimated Angle(scale: 360o/div), ω - Estimated
frequency(scale: 50Hz/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.5 Standalone Mode - Current reference generated from PLL outputs: Vg - Sensed grid volt-
age(scale: 2V/div), iinv - Inverter side current(scale: 5A/div) . . . . . . . . . . . . . . 26
5.6 Grid Interactive Mode: Vg - Sensed grid voltage(scale: 2V/div), iinv - Inverter side cur-
rent(scale: 20A/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.7 Grid Interactive Mode: Vg - Sensed grid voltage(scale: 2V/div), iinv - Inverter side cur-
rent(scale: 5A/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.8 Without Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter
side current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2:
idc - Main DC bus capacitor current(scale: 20A/div) . . . . . . . . . . . . . . . . . . 30
5.9 With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter
side current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2:
idc - Main DC bus capacitor current(scale: 20A/div) . . . . . . . . . . . . . . . . . . 30
5.10 With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH2: iact - Actual
DC bus current ripple(scale: 10A/div), CH3: iinj - Injected DC bus current ripple(scale:
10A/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.11 FFT of DC bus capacitor current . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.12 Without Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter
side current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2:
idc - Main DC bus capacitor current(scale: 20A/div) . . . . . . . . . . . . . . . . . . 32
5.13 With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter
side current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2:
idc - Main DC bus capacitor current(scale: 20A/div) . . . . . . . . . . . . . . . . . . 32
List of Figures viii
5.14 With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH2: iact - Actual
DC bus current ripple(scale: 10A/div), CH3: iinj - Injected DC bus current ripple(scale:
10A/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.15 FFT of DC bus capacitor current . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.16 Without Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter
side current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2:
idc - Main DC bus capacitor current(scale: 20A/div) . . . . . . . . . . . . . . . . . . 34
5.17 With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter
side current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2:
idc - Main DC bus capacitor current(scale: 20A/div) . . . . . . . . . . . . . . . . . . 34
5.18 With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH2: iact - Actual
DC bus current ripple(scale: 10A/div), CH3: iinj - Injected DC bus current ripple(scale:
10A/div) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5.19 FFT of DC bus capacitor current . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Nomenclature
Symbols : Definitions
Vdc : DC bus voltage of the main converter
Cdc : DC bus capacitance in main converter
Vg, vs : Grid voltage
Lf , Ls : Output filter inductance in main converter
Rs : Battery resistance
Ldc : Self inductance of DC winding in a coupled inductor filter
Lac : Self inductance of AC winding in a coupled inductor filter
M : Mutual inductance
k : Coefficient of coupling
Cac : Filter capacitance
C1 : Link/Filter capacitance in the hybrid filter
Cdc2 : DC bus capacitance in auxilliary converter
Vdc2 : DC bus voltage of the auxilliary converter
is : Grid current
ir : Low frequency ripple current in the DC bus
L : Filter inductance used in hybrid filter
Vα, Vβ : Outputs of SOGI
Kp,PR, Kr : Gains of PR controller
Kv, Tv : Gains of PI controller
ωo : Grid frequency in rad/s
ix
Chapter 1
Introduction
The use of Pulse Width Modulated (PWM) converters as active front ends is becoming
quite popular as it not only facilitates bidirectional transfer of power between the AC grid
and the DC bus bar; but also ensures very high power quality. They have become quite
indispensable in various Distributed Generation (DG) apllications for interfacing the DG
unit with the grid. However, the low frequency DC ripple current in single phase PWM
converters is a critical issue when a battery or a DG source is connected to the DC Bus. The
ripple current heats up the battery and shortens its life. In various DG applications like the
fuel cell based power conditioning system, the ripple current should be minimized to ensure
energy efficient operation and to improve the durability of the fuel cell stack [1].
1.1 Contributions of the Thesis
This thesis deals with the problem of low frequency current ripple in the DC bus of a
PWM converter. The different possible filter options are analyzed in detail. The problems
associated with simple passive filters are pointed out and the need for an active filter is
emphasized. The whole problem boils down to storing the ripple energy in a filter rather
than allowing it to go to the DC bus.
A new hybrid filter topology is proposed for storing the ripple energy effectively. The
control strategy for the same is also developed. The schematic of the single phase PWM
inverter with hybrid filter is shown in Fig. 1.1.
1
Chapter 1. Introduction 2
Battery/DG source
Grid
Interface
-/~-
HybridFilter
Figure 1.1: Schematic diagram of a grid connected PWM converter with proposed filter
1.2 Organization of the Thesis
In chapter 2, the different filter options for absorbing the low frequency DC bus current
ripple are looked into. A new hybrid filter topology is proposed.
Chapter 3 is dedicated to the theoretical analysis of the DC bus current ripple. Based
on the ripple, the control problem is formulated. Closed form expression for compensation
current to be injected has been found out for various modes of operation of the power
converter.
Chapter 4 discusses the control strategy for the entire system and implementation of the
same in digital domain.
In chapter 5, the simulation as well as experimental results with the pertinent waveforms
are discussed. Conclusion and Future work are discussed in chapter 6.
Chapter 2
Ripple Filtering
This chapter deals with the different filters that may be used for DC bus current ripple
filtering. A detailed study has been carried out and a new hybrid filter topology is proposed.
Basically, the ripple in the DC bus arises due to energy fluctuations which stem out of the
inherent unbalance in a single phase system. These energy fluctuations have to be absorbed
to tackle the issue of ripple current. The ripple energy has to be stored in some alternate
location rather than allowing it to go to the DC bus. A filter essentialy does this job of
storing the ripple energy. There are different possible filter options for handling the DC bus
current ripple problem which includes passive filters, active filters or a combination of both.
2.1 Passive Filters
2.1.1 Storing Ripple Energy in Electrostatic Field
The ripple energy can be stored in the electrostatic field of a capacitor. This can be achieved
by having sufficient amount of capacitance in parallel to the DC bus so that the ripple current
is bypassed by the capacitor.
For effective filtering,1
Cdcωrip<< Rs (2.1)
where Rs is the source/battery impedence and ωrip is the ripple frequency.
But, this is not a practically feasible solution in many situations. In low voltage, high current
applications, the value of capacitance needed for effective ripple filtering can even go upto
several Farads. It is not possible to obtain such huge values of capacitance in practice.
3
Chapter 2. Ripple Filtering 4
Vdc Cdc
leg a leg b
S1
S2
S3
S4
Lf
T
Vg
N1 N2
Figure 2.1: Capacitive filter for DC ripple filtering
2.1.2 Storing Ripple Energy in Electromagnetic Field
Here, the idea is to store the ripple energy in the magnetic field of an inductor. This
method also has its own disadvantages. The energy density of an inductor is much less
when compared to that of a capacitor. So the size of the inductive filter will be quite large
when compared to a capacitive filter. Also, here the inductor handles the entire ripple volt-
amperes(VA). For a given VA rating, the cost of an inductor is significantly higher than that
of a capacitor. In addition to the size, the cost of the filter will also be on the higher side.
2.1.3 Storing Ripple Energy Using Both Inductor and Capacitor
The next option is to use both inductor and capacitor for storing the ripple energy. The
magnetic permeability of the magnetic core for an inductor is much larger than the dielectric
constant of the films for a capacitor [2] whereas the cost and size of the capacitor is much
less for a given VA rating. There is a possibility that the good aspects of both the methods
can be combined to get an optimum design.
2.1.3.1 Passive LC filter
The main power converter is represented as a current source and the battery or source
impedence is modeled as Rs in Fig. 2.2. Here, the idea is to tune the filter in such a way
that the resonant frequency matches with the ripple frequency. The bandwidth of the filter
is decided by Lac and Cac values. High Lac and small Cac implies heavy filtering or narrow
bandwidth whereas large Cac and small Lac implies larger bandwidth. But, there are various
practical difficulties associated with this filter as well. The grid frequency is not fixed at
50Hz. In microgrid and traction applications, the frequency variations are sufficiently large
and cannot be neglected. As a result, the ripple frequency also changes. So to ensure proper
Chapter 2. Ripple Filtering 5
idc Cdc
Lac
Cac
Rs
Inverter Model Battery Model
Figure 2.2: Tuned passive LC filter for DC ripple filtering
filtering, the bandwidth of the filter should be large. In practical scenarios, the value of
capacitor needed is very large which is not feasible.
2.1.3.2 Coupled Inductor based Filter Configurations
Cdc
Cdc
Cdc
Cdc
Cac
Cac Cac
CacRs
Rs Rs
Rs
(a) (b)
(c) (d)
Figure 2.3: (a)Directly coupled configuartion-I (b) Inversely coupled configuration-I (c) Directly coupled
configuartion-II (d) Inversely coupled configuration-II
Numerous applications of coupled inductors stem from the desire to reduce the number
and size of the magnetic components without sacrificing circuit performance [3]. Due to
coupling, higher order filtering is possible without much increase in the size of the filter. By
properly designing the leakage of the coupled inductor, ripple steering is also acheieved in
many applications.
If there are two separate inductors in the circuit, by coupling them, it is possible to
eliminate the ripple in either one of them. Also by replacing a single inductor with a coupled
inductor, the ripple in it can be eliminated. But here, ideally there is/are no inductor(s) at
all in the DC bus. So by introducing a coupled inductor additionally, there may not be any
Chapter 2. Ripple Filtering 6
benefit at all. This situation needs to be carefully analyzed. Fig. 2.3 shows the different
possible ways of connecting a coupled inductor filter to the DC bus.
Cdc CacRs Cdc
Cac
Ldc - M
Lac - M
M
Rs
Coupled Circuit Uncoupled Equivalent Circuit
Figure 2.4: Directly coupled configuartion-I
Consider the first topology in Fig. 2.4. Here, Lac −M and Cac should resonate at ripple
frequency. The width of the notch is high for high Cac. The extra flexibilities due to coupling
are to be analyzed.
Case 1 : Large coefficient of coupling, k and equal turns(Nac = Ndc)
Here, Lac = Ldc ≈M . So there is no advantage at all. A huge Cac will be needed for effective
filtering.
Case 2 : Small k and Nac = Ndc
There is no benefit due to coupling. Zero coupling will give the best performance in this
case.
Case 3 : Large k and Nac > Ndc
There is a possibility to reduce the size of the dc winding. But Ldc − M will always be
negative and emulates the effect of a capacitance. The stability of the system is affected
as unwanted resonances are seen in the low frequency regime. If not properly designed, the
ripple current may get amplified.
The second topology (Fig. 2.5) is more promising. The effective AC impedence of the
Cdc CacRs Cdc
Cac
Ldc+M
Lac+M
-M
Rs
Coupled Circuit Uncoupled Equivalent Circuit
Figure 2.5: Inversely coupled configuration-I
source is significantly increased by Ldc + M . No unwanted resonances are seen and the
Chapter 2. Ripple Filtering 7
circuit is more stable. There is a possibility to reduce the size of the Cac by choosing tight
coupling. But since the entire ripple current flows through −M , large voltage ripple across
Cdc is observed. If not properly designed, this will affect the current control loop of the main
converter.
In the third topology given by Fig. 2.6, tight coupling and equal turns would demand a
CdcCac
Rs
Coupled Circuit Uncoupled Equivalent Circuit
Cdc
CacRs
Ldc-M
Lac-M
M
Figure 2.6: Directly coupled configuartion-II
huge Cac which is not practical. Best results are seen when there is no coupling at all.
This last circuit (Fig. 2.7) possesses some good characteristics of second circuit and some
CdcCac
Rs
Coupled Circuit Uncoupled Equivalent Circuit
Cdc
CacRs
Ldc+M
Lac+M
-M
Figure 2.7: Inversely coupled configuration-II
bad characteristics of first circuit. With tight coupling, smaller Cac would suffice. But pos-
itive resonance is observed because of the negative inductance emulated in series with the
source.
In all these cases the width of the notch is decided by Cac and the equivalent inductance
in series with it. If the grid frequency varies significantly, these passive circuits will not prove
much useful. So an active filter is required to handle grid frequency variations.
2.2 Active Filters
An effective active filter topology has been proposed in [2] where a third active leg is added
and a current is injected through the inductor so as to cancel the ripple current in the DC
Chapter 2. Ripple Filtering 8
bus. The size of the DC bus capacitance can be considerably reduced as it now have to
handle the switching frequency ripple alone.
Vdc Cdc
leg a leg b
S1
S2
S3
S4
Lf
T
Vg
N1 N2 S5
S6
leg c
L
Figure 2.8: Inductive filter for DC ripple filtering - Active filtering approach
Here, the ripple energy is completely stored in the magnetic field of the inductor, L.
Hence, as discussed earlier, the cost and size of the filter will be quite high. The inductor
as well as the two additional active switches, S5 and S6 must handle the entire ripple VA.
Eventhough, the filtering will be effective inspite of grid frequency variations, this also is not
an optimal topology.
2.3 Proposed Hybrid Filter
Based on the filter topologies analyzed, it is clear that good performance can be achieved
with a combination of inductor and capacitor for handling the ripple energy and the circuit
should be tuned actively for meeting grid frequency variations. Considering these aspects,
a new topology is proposed which is shown in Fig. 2.9. Ripple Energy is stored by both C1
and L.
N2
N3
N1
S'1
S'2
S'3
S'4
C1
Cdc2
LS'5
S'6
Vdc
Vg
Lf
S1 S3
S4 S2
Z
Cdc
leg 1 leg 2 leg 3
Vdc2
Hybrid Filter
Figure 2.9: PWM converter with the proposed hybrid filter
Chapter 2. Ripple Filtering 9
The filter converter is also connected to the grid. Leg 1 and leg 2 of the filter converter
are switched to maintain Vdc2 at a desired level. If there is no mechanism to regulate Vdc2,
it will keep on falling due to the losses in the filter converter. These losses mainly include
the conduction and switching losses of the converter. The current drawn from the grid
will be very less which is just enough to meet these losses. The challenge is to find the
switching pattern for leg 3. The current through the inductor L is the factor which affects
the performance of the filter. The current should be injected so as to cancel the ripple in
the main DC bus. The main advantage of this topology is that the volt-amperes(VA) rating
of the active converter is less as part of the ripple VA is handled by the capacitor. The
topology will be extremely beneficial if more energy is stored in capacitor and less energy is
stored in inductor. This will help in reducing the size and cost of the filter system. Choosing
Vdc2 is very crucial as it is the factor which decides the energy sharing between the inductor
and capacitor. The zener, Z is used for ensuring that the auxilliary DC bus voltage doesn’t
exceed a critical value while precharging the main converter DC bus. It is used for one time
dissipation only. During normal operation, the Vdc2 will be maintained at a value much less
than the breakdown voltage of the zener.
Chapter 3
Ripple Analysis and Compensation
Current
In the proposed filter, the challenge is to find out the value of compensation current to
be injected through L so as to cancel the current ripple in the DC bus of the main power
converter. For that, the DC bus ripple has to be properly analyzed. Firstly, the ripple power
in the DC bus is evaluated. Based on the ripple power expression [4], the ripple current
is calculated. This is used to derive a closed form expression for the compensation current
which has to be injected through the filter inductor, L.
3.1 Analysis of Operation
3.1.1 Main Converter
The main converter may be operating as an active rectifier, statcom, PWM inverter or may
be operating at any arbitrary power factor. A generalized analysis is presented to find out
the DC bus low frequency ripple current using the instantaneous power theory.
DC Bus Ripple Analysis Let vs denote the grid voltage and is the grid current and their
instantaneous polarities be as shown in Fig. 3.1. Let the power factor angle be φ.
vs =√
2Vssin(ωt) (3.1)
is =√
2Issin(ωt+ φ) (3.2)
where Vs and Is are the rms values of voltage and current respectively.
The input power, Ps is given by
Ps = vsis = VsIs(cosφ− cos(2ωt+ φ)) (3.3)
10
Chapter 3. Ripple Analysis and Compensation Current 11
S1
S2
S3
S4
Lsis
vs+
Vs
Rs
Vdc Cdc
leg a leg bir1
Figure 3.1: Main converter
The inductor Ls acts as a boost component to transfer power from AC side to DC side. The
instantaneous power in the inductor is given by
PLs = isLsdisdt
= ωLsIs2sin(2ωt+ 2φ) (3.4)
The power output of the converter or the DC side power, Po is given by
Po = vsis − isLsdisdt
= VsIscosφ− VsIscos(2ωt+ φ)− ωLsI2s sin(2ωt+ 2φ) (3.5)
The ripple component of output power is termed as ripple power and is denoted by Pr.
Pr = −VsIscos(2ωt+ φ)− ωLsI2s sin(2ωt+ 2φ) (3.6)
The ripple current in the DC bus of main converter is given by
ir1 =PrVdc
=−VsIscos(2ωt+ φ)− ωLsI2
s sin(2ωt+ 2φ)
Vdc
= −Is√
(Vs2 + ω2Ls
2Is2 + 2VsωLsIssinφ)sin(2ωt+ ψ)
Vdc(3.7)
ψ = tan−1(ωLsIssin2φ+ Vscosφ
ωLsIscos2φ− Vssinφ) (3.8)
3.1.2 Compensation Current for Ripple Cancellation
The ripple current in the DC bus of auxilliary converter is given by
ir2 =PLVdc2
=iLL
diLdt
Vdc2(3.9)
Chapter 3. Ripple Analysis and Compensation Current 12
S'1
S'2
S'3
S'4
Cdc
C1
Cdc2
L
S'5
S'6
L1
ir1
ir2
iL
leg 1 leg 2 leg 3
Figure 3.2: Auxilliary converter
For ripple cancellation, the currents ir2 = ir1. Hence, the instantaneous power in the filter
inductor, L can be expressed by the equation
iLLdiLdt
= −Vdc2Vdc
Is
√(Vs
2 + ω2Ls2Is
2 + 2VsωLsIssinφ)× sin(2ωt+ ψ) (3.10)
Let the required compensation current, iL = Kcos(ωt+ ψ2)
LdiLdt
= −KLωsin(ωt+ψ
2) (3.11)
iLLdiLdt
= −K2Lω
2sin(2ωt+ ψ) (3.12)
From (3.10) and (3.12), we obtain the amplitude of the compensation current to be
K =
√2Vdc2IsLωVdc
√Vs
2 + (ωLsIs)2 + 2VsωLsIssinφ (3.13)
Hence, the instantaneous compensation current is iL = Kcos(ωt + ψ2) where K and ψ are
given by (3.13) and (3.8) respectively
3.1.3 Validity of the Proposed Strategy
For the control strategy to be valid, the instantaneous ripple power generated by the main
converter should be equal to the instantaneous power generated by the hybrid filter which
is nothing but the sum of the instantaneous powers in the capacitor, C1 and inductor, L.
Chapter 3. Ripple Analysis and Compensation Current 13
The instantaneous power in the link capacitor, C1 is given by
PC1 = ir1
C1
∫irdt+ ir(Vdc − Vdc2)
= −Vs2 + (ωLsIs)
2 + 2VsωLsIssinφ)Is2
4C1Vdc2ω
sin(4ωt+ 2ψ)
−(Vdc − Vdc2)
VdcIs
√(Vs
2 + ω2Ls2Is
2 + 2VsωLsIssinφ)× sin(2ωt+ ψ) (3.14)
The instantaneous power in filter inductor, L is given by
PL = iLLdiLdt
= −Vdc2Vdc
Is
√(Vs
2 + ω2Ls2Is
2 + 2VsωLsIssinφ)× sin(2ωt+ ψ) (3.15)
For absorbing the ripple energy completely, Pr = PL + PC1 ⇒ PL = Pr − PC1
PL =(Vs
2 + ω2Ls2Is
2 + 2VsωLsIssinφ)Is2
4C1Vdc2ω
× sin(4ωt+ 2ψ)
−Vdc2Vdc
Is
√(Vs
2 + ω2Ls2Is
2 + 2VsωLsIssinφ)× sin(2ωt+ ψ) (3.16)
Comparing (3.15) and (3.16), the control strategy is valid if and only if the 4ω ripple in the
link capacitor is negligible. That is, the ripple voltage in C1 should be negligible compared
to the DC voltage across it.
The control strategy is valid if and only if the 4ω ripple in the link capacitor
is negligible. That is, the ripple voltage in C1 should be negligible compared to
the DC voltage across it.
The closed form expression for compensation current under the four basic operating
modes is summarized in Table 3.1.
3.2 Selection of Filter Components
3.2.1 Selecting Filter Capacitance, C1
It has been shown that, the 4ω ripple power in the capacitor C1 should be negligible. So the
capacitor should be chosen large enough to minimize the ripple voltage in it. It is advisable
Chapter 3. Ripple Analysis and Compensation Current 14
Table 3.1: Closed form expression for compensation current
K =
√2Vdc2IsLωVdc
√Vs
2 + (ωLsIs)2
UPF Rectification iL = Kcos(ωt+ ψ2 )
ψ = tan−1 Vs
ωLsIs
K =√
2Vdc2
LωVdc(VsIs + ωLsI2s )
STATCOM iL = Ksin(ωt)
K =√
2Vdc2
LωVdc(VsIs − ωLsI2s )
ZPF Lag iL = Kcos(ωt)
K =
√2Vdc2IsLωVdc
√Vs
2 + (ωLsIs)2
UPF Inversion iL = Ksin(ωt+ ψ2 )
ψ = π − tan−1 Vs
ωLsIs
to choose a capacitance value to limit the peak ripple to be about 5-10% of the DC voltage
across C1.
3.2.2 Selecting Cdc2
Cdc2 is the DC bus capacitance of the filter converter if we consider the filter converter
alone. But when the whole system is considered, the effective DC bus capacitance of the
filter converter is C1Cdc
C1+Cdc+Cdc2. The idea is that, when grid frequency current flows through
inductor, L a double frequency ripple will appear at the DC bus of the filter converter. This
current should flow through C1 to the main DC bus and cancel out the ripple there rather
than flowing into Cdc2. So Cdc2 should be about 10-20% of C1Cdc
C1+Cdc.
Chapter 3. Ripple Analysis and Compensation Current 15
3.2.3 Selecting Filter Inductance, L
0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 1.250
1
2
3
4
5
6
7
8x 10−4
Modulation index, m
Filte
rind
ucta
nce,
L
(a)
20 40 60 80 100 120 140 160 1800
1
2
3
4
5
6
7
8x 10−4
Compensation current, icomp
Filte
rind
ucta
nce,
L
(b)
Figure 3.3: (a) Choosing filter inductor, L based on modulation index: Sample curve, (b) Compensation
current to be pumped through the filter inductor, L
Selecting proper L value is a bit tricky. When the main converter is operating at full load,
the modulation indices of leg 2 and leg 3 should be close to unity. Based on this criterion,
the value of L should be chosen. If the legs go into overmodulation, the control strategy
doesn’t hold good. The L value should be selected keeping this in mind.
3.2.4 Choosing Vdc2
Vdc2 is a crucial factor which decides the energy sharing between the inductor and capacitor.
To maximize the benefits of the proposed filter, Vdc2 should be chosen much lesser than the
main DC bus voltage, Vdc.
0 0.2 0.4 0.6 0.8 10
200
400
600
800
1000
1200
Vdc2
/Vdc
VA
ratin
gof
the
activ
epa
rtof
the
filte
r
Figure 3.4: Effect of Vdc2 on filter VA rating: Sample curve
Chapter 4
Control Strategy
This chapter deals with the closed loop control strategy for the entire system. The single
phase PLL, control strategy for the main converter and the control strategy for the auxilliary
converter are discussed. The digital implementation of the PLL as well as various controllers
like PI controller and PR controller are also discussed.
4.1 Single Phase PLL
Since, the main converter is operated in grid interactive mode, a PLL is necessary. Phase,
amplitude and frequency of the utility voltage are to be known for grid connected operation
of inverters. This information is extracted using the PLL. Line notching, line dip, frequency
variations, etc. are common conditions faced by equipment interfacing with electric utility
[5]. The PLL should provide clean outputs even under such abnormal conditions. A single
phase PLL is used here as the main converter is a single phase PWM inverter.
Figure 4.1: Single phase PLL
16
Chapter 4. Control Strategy 17
The design of single phase PLL is slightly different compared to the three phase PLL. A
subsystem is needed to generate a pair of orthogonal voltages Vα and Vβ which are in phase
and in quadrature with the supply voltage. They are easily obtained in a three phase PLL by
making use of the stationary three phase to two phase transformation. This is not possible
in single phase case. Hence a block called ‘Second Order Generalized Integrator’ (SOGI)[6]
is used to obtain Vα and Vβ. The PI controller values were chosen based on symmetric
optimum method.
4.1.1 Second Order Generalized Integrator(SOGI)
The following expressions are implemented by SOGI for Vα and Vβ.
Vα(s)
Vg(s)=
kωos
s2 + kωos+ ω2o
(4.1)
Vβ(s)
Vg(s)=
kω2o
s2 + kωos+ ω2o
(4.2)
Figure 4.2: Second Order Generalized Integrator(SOGI)
The constant k affects the bandwidth of the closed loop system. If k decreases, the filter
becomes narrower resulting in a heavy filtering, but at the same time the dynamic response
of the system becomes slower. The tuning of this structure is frequency dependant and can
face problems when grid frequency has fluctuations. Therefore the resonant frequency of
SOGI is adjusted by the output frequency of PLL structure.
Chapter 4. Control Strategy 18
4.2 Control Scheme of the Converter
X X X X XX
Vg
sin pll
cos pll
PI PRsin pll
cos pll
X
I*d
I*qVoltageController
CurrentController
ILFF
PowerCircuit
-I*d Lsin pll I*q Lcos pll
Inductive drop compensation
V*dc
Vdc Ifb
Iref
VgFF
V*ref+
++ + +
+
- -
+
+
+ + ++
PLL
Vdc
Ifb
X XPI PRsin pllV*dc2
Vdc2IL1fb
+- -
+
PR
ILfb
I*L X+ -
I*L1
ReferenceGenerator
Vs Is Vdc2Vdc
0.5
1
- 1
Compare
Compare
Compare
0.5
1
- 1
Compare
Compare FilterCircuit
Vdc2
ILfb
IL1fb
S1
S2
S3
S4
S'5S'6S'1
S'3S'2
S'4
Figure 4.3: Control scheme of the proposed circuit topology.
4.2.1 Main Converter
Vector control or d-q control scheme is used to control the main power converter. The grid
voltage phasor is aligned along the q axis. I∗q and I∗d rrefers to the peak value of real and
reactive current references respectively [7].
The control scheme consists of an outer voltage loop and an inner current loop. The outer
voltage loop maintains the DC bus voltage at the desired level. A PI controller is used for the
purpose as the reference is pure DC. The fall in the DC bus voltage can be attributed to the
real power demanded by the system. So the output of the PI controller is actually the peak of
the active current reference, I∗q . To improve the dynamic performance of the controller, the
DC load current demand is included as a feedforward term. The actual current reference is
obtained by multiplying this with the inphase unit vector sinθpll. Reactive current reference
depends upon the amount of compensation needed in STATCOM application and upon the
operating power factor in AFEC application. It is obtained by multiplying I∗d with the unit
vector in quadrature with the grid voltage, cosθpll. Since the current reference is an AC
quantity, a PI controller will introduce steady state error. If the gain is increased to expand
the PI controller bandwidth, the system is pushed to its stability limit [8]. So a Proportional
Chapter 4. Control Strategy 19
-Resonant(PR) controller is used for current control.
The bandwidth of the outer voltage loop should be selected such that it is much less than
the bandwidth of the current loop. So, while designing the voltage loop, the inner current
loop can be approximated by a gain without much error. Also, the low frequency ripple in
the DC bus voltage should be rejected by the voltage controller. So the bandwidth of the
voltage loop should be chosen atleast one decade below the low frequency ripple component
in the DC bus.
4.2.2 Auxilliary Converter
The auxilliary converter also operates in grid interactive mode. But, this is to maintain
the DC bus voltage constant. The converter draws active power just enough to meet its
losses from the grid. There is an outer voltage loop and an inner current loop similar to
that of the main converter. In addition to this, one more controller is used to regulate the
compensation current through the filter inductor. Since, that current is also an AC quantity,
a PR controller is used. The reference generator will generate the current reference for ripple
compensation. It is the most important part in the ripple control strategy.
4.3 Controller Design
The procedure followed for selecting the controller parameters is explained below.
Current Controller Design
-
i ii*
i f b
+ Vdc2
c
Figure 4.4: Block diagram of the current control scheme
First a PI controller is designed. The time constant is chosen such that Tc = LR
. The
Chapter 4. Control Strategy 20
actual open loop transfer function is given by
G(s)H(s)C(s) =KpVdcKc
2TcRs(4.3)
The desired open loop transfer function is
G(s)H(s)C(s) =1
sτ(4.4)
where τ = 1ωBW
From 4.3 and 4.4
Kp =2TcR
VdcKcτ=
2L
VdcKcτ(4.5)
Ki =Kp
Tc=
2R
VdcKcτ(4.6)
From 4.6 and 4.6, the gains of PR controller is obtained.
Kp,PR = Kp and Kr = 2Ki
Voltage Controller Design
-
i +V*dc
Vdc,f b
idc Vdc1
2
Figure 4.5: Block diagram for DC voltage regulation
The entire current loop gain is considered unity for voltage controller design. The gain
K1 indicated in the Fig. 4.5 is the quantity that relates the DC current Idc and the AC
current Iac [9].
Using power balance under UPF conditions,
K1 =Vl−l(rms)√
2Vdc(4.7)
Chapter 4. Control Strategy 21
First design a P controller. The actual open loop transfer function is given by
G(s)H(s)C(s) =KvK1K2
sC(4.8)
The desired open loop transfer function is
G(s)H(s)C(s) =1
sτ(4.9)
where τ = 1ωBW
From 4.8 and 4.9
Kv =C
K1K2τ(4.10)
A small amount of integral gain is added to minimize the steady state error.
Table 4.1: Controller Parameters
Voltage Controller Current Controller Compensation Controller
Kp = 25 Kp = 0.5
Main Converter Ki = 50 Kr = 300
ωBW = 60rad/s ωBW = 1500rad/s
Kp = 12.5 Kp = 0.1 Kp = 0.5
Auxilliary Converter Ki = 25 Kr = 100 Kr = 300
ωBW = 60rad/s ωBW = 1500rad/s ωBW = 1500rad/s
4.4 Digital Implementation of Controllers
All the controllers were implemented in FPGA using VHDL. Basically, each transfer func-
tion is first expressed using integrators, gains and adder/subtractor blocks. Then numerical
integration techniques are applied to implement the same in the digital platform. In this
work, Tustin transformation has been used to discretize the integrator blocks. Tustin trans-
formation is prefered as it is easy to implement and gives accurate results with minimum
distortion in this case [10].
Chapter 4. Control Strategy 22
SOGI
The SOGI transfer functions are
p(s)
u(s)=
kωos
s2 + kωos+ ω2o
(4.11)
q(s)
u(s)=
kω2o
s2 + kωos+ ω2o
(4.12)
This can be represented as follows
Figure 4.6: SOGI
p(k) = p(k − 1) +e(k − 1) + e(k)
2kωTs −
q(k − 1) + q(k)
2ωTs (4.13)
q(k) = q(k − 1) +p(k − 1) + p(k)
2ωTs (4.14)
These difference equations can easily be implemented in FPGA.
PI controller
Y (s)
U(s)= kp +
kis
(4.15)
The PI controller can be represented by the following difference equations which are
implemented in FPGA.
x(k) = x(k − 1) +u(k) + u(k − 1)
2kiTs (4.16)
y(k) = kpu(k) + x(k) (4.17)
Chapter 4. Control Strategy 23
PR controller
Y (s)
U(s)= kp +
krs
s2 + ω2(4.18)
kr
Figure 4.7: Resonant part of PR controller
The PR controller can be represented using the following difference equations which are
implemented using VHDL in FPGA platform.
p(k) = p(k − 1) +u(k − 1) + u(k)
2krTs −
q(k − 1) + q(k)
2ωTs (4.19)
q(k) = q(k − 1) +p(k − 1) + p(k)
2ωTs (4.20)
y(k) = kpu(k) + p(k) (4.21)
Chapter 5
Results
In this chapter, the simulation as well as experimental results are discussed.
5.1 SOGI based PLL
The designed PLL was first tested with a purely sinusoidal input from a function generator.
Later, it was found that the PLL was able to give clean outputs even in the presence of
distorted input with a DC shift. All the waveforms presented are actual experimental results
captured using Digital Storage Oscilloscope.
Vpll
time (5ms/div)
sin cos
Figure 5.1: PLL outputs when input is clean: Vpll - PLL input(scale: 2V/div), cosθ - Quadrature unit
vector(scale: 5V/div), sinθ - In phase unit vector(scale: 5V/div)
The frequency adaptiveness of the PLL was also verified by changing the input frequency
using a function generator. The PLL can safely be used for microgrid, traction applications,
etc. where the frequency variation is quite large.
24
Chapter 5. Results 25
Vpll
time (5ms/div)
sin cos
Figure 5.2: PLL outputs when input is distorted and has DC offset: Vpll - PLL input(scale: 2V/div), cosθ
- Quadrature unit vector(scale: 5V/div), sinθ - In phase unit vector(scale: 5V/div)
time (5ms/div)
sin cos
Vpll
(a) Input frequency is 40Hz
Vpll
time (5ms/div)
sin cos
(b) Input frequency is 60Hz
Figure 5.3: PLL outputs when input frequency varies: Vpll - PLL input(scale: 2V/div), cosθ - Quadrature
unit vector(scale: 5V/div), sinθ - In phase unit vector(scale: 5V/div)
Vpll
time (5ms/div)
Figure 5.4: Vpll - PLL input(scale: 2V/div), θ - Estimated Angle(scale: 360o/div), ω - Estimated fre-
quency(scale: 50Hz/div)
Chapter 5. Results 26
5.2 Main Converter - Standalone mode with current
control
The main converter was run in standalone mode and the current references were generated
from PLL outputs. All the waveforms presented are experimental results captured using
DSO. The controller was found to track different current references perfectly.
Table 5.1: Circuit Parameters of main converter for standalone mode
DC Bus Capacitance, Cdc 33mF
DC bus voltage, Vdc 24V
Transformer turns ratio, N1 : N2 1:16
Output inductance in transformer secondary, L 56µH
Load resistor in transformer primary, R 50Ω
time (5ms/div)
Vg
iinv
(a)
time (5ms/div)
Vg
iinv
(b)
time (5ms/div)
Vg
iinv
(c)
time (5ms/div)
Vg
iinv
(d)
Figure 5.5: Standalone Mode - Current reference generated from PLL outputs: Vg - Sensed grid volt-
age(scale: 2V/div), iinv - Inverter side current(scale: 5A/div)
Chapter 5. Results 27
5.3 Main Converter - Grid Interactive Mode
The main power converter was interfaced with the grid and the working of the DC bus
voltage controller and the current controller were verified under various operating modes of
the converter. All the waveforms presented are experimental results captured using DSO.
Table 5.2: Circuit parameters of main converter for grid interactive mode
Filter Inductance, Lf 56µH
DC Bus Capacitance, Cdc 33mF
DC bus voltage, Vdc 24V
Transformer turns ratio, N1 : N2 1:16
Vg
iinv
time (5ms/div)
(a) AFEC operation at no load
time (5ms/div)
Vg
iinv
(b) STATCOM operation
Vg iinv
time (5ms/div)
(c) ZPF lag operation
Figure 5.6: Grid Interactive Mode: Vg - Sensed grid voltage(scale: 2V/div), iinv - Inverter side cur-
rent(scale: 20A/div)
Chapter 5. Results 28
5.4 Auxilliary Converter - Grid Interactive Mode
The auxilliary power converter was interfaced with the grid and the working of the DC bus
voltage controller and the current controller were verified under various operating modes of
the converter. All the waveforms presented are experimental results captured using DSO.
Table 5.3: Circuit parameters of auxilliary converter for grid interactive mode
Filter Inductance, Lf2 20µH
DC Bus Capacitance, Cdc2 3.3mF
DC bus voltage, Vdc2 15V
Transformer turns ratio, N1 : N2 1:23
Vg
iinv
time (5ms/div)
(a) AFEC operation at no load
time (5ms/div)
Vg iinv
(b) STATCOM operation
Vg iinv
time (5ms/div)
(c) ZPF lag operation
Figure 5.7: Grid Interactive Mode: Vg - Sensed grid voltage(scale: 2V/div), iinv - Inverter side cur-
rent(scale: 5A/div)
Chapter 5. Results 29
5.5 DC Bus Current Ripple Reduction
The validity of the proposed topology as well as the ripple reduction algorithm have been
experimentally verified. The main converter was run as a STATCOM, a lagging load and as
a front end rectifier. In all these cases, the simulation and experimental waveforms with and
without the filter is presented. The simulations were done in PSIM.
Table 5.4: Circuit parameters used in the proposed topology
Main Converter Parameters
Filter Inductance, Lf 250µH
DC Bus Capacitance, Cdc 33mF
DC bus voltage, Vdc 30V
Transformer turns ratio, N1 : N2 1:16
Auxilliary Converter Parameters
Filter Inductance, Lf2 20µH
DC Bus Capacitance, Cdc2 3.3mF
DC bus voltage, Vdc2 15V
Transformer turns ratio, N1 : N2 1:23
Filter Parameters
Link Capacitor, C1 33mF
Filter Inductor, L 270µH
Chapter 5. Results 30
5.5.1 STATCOM Mode
The simulation as well as experimental results for STATCOM mode when no compensation
current is injected is shown in Fig. 5.8.
Vg
iinv
icomp
idc
(a) PSIM Simulation Results
Vg
iinv
icomp
idc
(b) Experimental Results
Figure 5.8: Without Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter
side current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2: idc - Main DC bus
capacitor current(scale: 20A/div)
The simulation as well as experimental results for STATCOM mode with compensation
is shown in Fig. 5.9. The capacitor current waveform is modified in this case.
Vg
iinv
icomp
idc
(a) PSIM Simulation Results
Vg
iinv
icomp
idc
(b) Experimental Results
Figure 5.9: With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter side
current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2: idc - Main DC bus
capacitor current(scale: 20A/div)
Fig. 5.10 shows the actual 100Hz component in the main DC bus and the 100Hz com-
ponent injected into the auxilliary DC bus when compensation is enabled.
Chapter 5. Results 31
Vg
iact
iinj
(a) PSIM Simulation Results
Vg
iact
iinj
(b) Experimental Results
Figure 5.10: With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH2: iact - Actual DC
bus current ripple(scale: 10A/div), CH3: iinj - Injected DC bus current ripple(scale: 10A/div)
The experimental FFT of the DC bus capacitor current with and without compensation
is shown in Fig. 5.11. Clearly the 100 Hz component has reduced when compensation is
applied.
0 100 200 300 400 5000
1
2
3
4
5
6FFT for DC bus current
Frequency (Hz)
Mag
nitu
de
(a) Without compensation
0 100 200 300 400 5000
1
2
3
4
5
6FFT for DC bus current
Frequency (Hz)
Mag
nitu
de
(b) With compensation
Figure 5.11: FFT of DC bus capacitor current
Chapter 5. Results 32
5.5.2 ZPF Lag Mode
The simulation as well as experimental results for ZPF lag mode when no compensation
current is injected is shown in Fig. 5.12.
Vg
iinv
icomp
idc
(a) PSIM Simulation Results
Vg
iinv
icomp
idc
(b) Experimental Results
Figure 5.12: Without Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter
side current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2: idc - Main DC bus
capacitor current(scale: 20A/div)
The simulation as well as experimental results for ZPF lag mode with compensation is
shown in Fig. 5.13. The capacitor current waveform is modified in this case.
Vg
iinv
icomp
idc
(a) PSIM Simulation Results
Vg
iinv
icomp
idc
(b) Experimental Results
Figure 5.13: With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter
side current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2: idc - Main DC bus
capacitor current(scale: 20A/div)
Fig. 5.14 shows the actual 100Hz component in the main DC bus and the 100Hz com-
Chapter 5. Results 33
ponent injected into the auxilliary DC bus when compensation is enabled.
Vg
iact
iinj
(a) PSIM Simulation Results
Vg
iact
iinj
(b) Experimental Results
Figure 5.14: With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH2: iact - Actual DC
bus current ripple(scale: 10A/div), CH3: iinj - Injected DC bus current ripple(scale: 10A/div)
The experimental FFT of the DC bus capacitor current with and without compensation
is shown in Fig. 5.15. Clearly the 100 Hz component has reduced when compensation is
applied.
0 100 200 300 400 5000
0.5
1
1.5
2
2.5
3
3.5
4
4.5FFT for DC bus current
Frequency (Hz)
Mag
nitu
de
(a) Without compensation
0 100 200 300 400 5000
0.5
1
1.5
2
2.5
3
3.5
4
4.5FFT for DC bus current
Frequency (Hz)
Mag
nitu
de
(b) With compensation
Figure 5.15: FFT of DC bus capacitor current
Chapter 5. Results 34
5.5.3 AFEC Mode
The simulation as well as experimental results for AFEC mode when no compensation cur-
rent is injected is shown in Fig. 5.16.
Vg
iinv
icomp
idc
(a) PSIM Simulation Results
Vg
iinv
icomp
idc
(b) Experimental Results
Figure 5.16: Without Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter
side current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2: idc - Main DC bus
capacitor current(scale: 20A/div)
The simulation as well as experimental results for AFEC mode with compensation is
shown in Fig. 5.17. The capacitor current waveform is modified in this case.
Vg
iinv
icomp
idc
(a) PSIM Simulation Results
Vg
iinv
icomp
idc
(b) Experimental Results
Figure 5.17: With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH3: iinv - Inverter
side current(scale: 20A/div), CH4: icomp - Compensation current(scale: 50A/div), CH2: idc - Main DC bus
capacitor current(scale: 20A/div)
Fig. 5.18 shows the actual 100Hz component in the main DC bus and the 100Hz com-
ponent injected into the auxilliary DC bus when compensation is enabled.
Chapter 5. Results 35
Vg
iact
iinj
(a) PSIM Simulation Results
Vg
iact
iinj
(b) Experimental Results
Figure 5.18: With Compensation: CH1: Vg - Sensed grid voltage(scale: 2V/div), CH2: iact - Actual DC
bus current ripple(scale: 10A/div), CH3: iinj - Injected DC bus current ripple(scale: 10A/div)
The experimental FFT of the DC bus capacitor current with and without compensation
is shown in Fig. 5.19. Clearly the 100 Hz component has reduced when compensation is
applied.
0 100 200 300 400 5000
0.5
1
1.5
2
2.5
3
3.5
4FFT for DC bus current
Frequency (Hz)
Mag
nitu
de
(a) Without compensation
0 100 200 300 400 5000
0.5
1
1.5
2
2.5
3
3.5
4FFT for DC bus current
Frequency (Hz)
Mag
nitu
de
(b) With compensation
Figure 5.19: FFT of DC bus capacitor current
Chapter 5. Results 36
5.6 Summary of Results
Table 5.5: Peak value of DC bus ripple current
STATCOM ZPF Lag UPF Rectification
No compensation 5.87A 4.29A 3.72A
Experimental Result
With compensation 0.96A 1.33A 1.72A
No compensation 5.53A 5.11A 4.13A
Simulation Result
With compensation 0.83A 0.92A 0.94A
No compensation 5.60A 5.60A 4.26A
Theoretical Result
With compensation 0A 0A 0A
Table 5.5 gives a comparison between the experimental results, simulation results and
theoretical results. The ripple is clearly getting reduced as expected. In ideal analysis, the
small amount of active current drawn by both converters to meet their losses is not consid-
ered. Hence, the small variation in ripple values. The usefulness of the proposed circuit will
become more evident when the power converter is run at higher current levels.
5.7 Comparison of Filters
Table 5.6: Comparison of proposed filter with other filters for a 1 KVA system
Parameter Proposed hybrid filter Purely inductive filter(Active) Purely capacitive filter
Cdc 33mF ≈ 1mF 5F
Clink 33mF nil nil
Lfil 270µH 270µH nil
Icomp(pk)√
Vdc2
Vdc× 150A 150A nil
VA Rating of active switches Vdc2
Vdc× 1000VA 1000VA nil
VA Rating of filter inductor Vdc2
Vdc× 1000VA 1000VA nil
Chapter 5. Results 37
Table 5.6 gives a comparison between the proposed filter and some other filters for a 1
kVA system with 30V DC bus. The DC bus capacitance is chosen such that only 1% of
the ripple current flows into the battery. The battery impedence at 100Hz is assumed to
be 10mΩ. For a purely capacitor flter, the capacitance value needed to achieve this is 5F
whereas in the proposed topology, it is reduced to 33mF. The proposed filter is compared
with the purely inductive based active filter as well. For the same value of filter inductance,
the compensation current to be injected is less in the proposed filter. The VA rating of the
active components is also less in the proposed method.
Chapter 6
Conclusion
The project was aimed at developing a filter topology to handle the DC bus current ripple
in a single phase PWM inverter. Eventhough, a number of filter topologies are discussed in
literature, this project tries to look at the problem from the perspective of energy and to
come up with an optimized solution.
A new hybrid filter topology is proposed to absorb the DC bus ripple current. The DC
ripple stem out of energy fluctuations. The ripple power and DC bus current ripple has
been quantified under various operating modes of the converter. Based on that, the control
problem was formulated. A systematic method is given to choose the ratings of various filter
components. Optimized design can be done with the help of Linear Programming techniques.
A control strategy was developed for the proposed filter and its validity was verified using
simulations in PSIM. The novelty of the proposed topology lies in the fact that there is no
need to sense the DC bus ripple current and still good performance is achieved irrespective
of the operating power factor of the main converter.
Since the main converter was operated in grid interactive mode, a single phase PLL
was developed. The main advantage of the PLL was its frequency adaptiveness. All the
controllers were implemented in FPGA using VHDL. The main power converter was run
both in standalone mode and grid interactive mode to verify the effectiveness of controllers.
Then the filter converter was run separately. Once both the converters were up and running,
the proposed algorithm was validated experimentally. The new topology was found to be
quite effective in compensating the DC bus ripple current. The power converter was operated
in various modes and in all cases, the filtering was good.
38
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