Datasheet - thundercomm.s3-ap-northeast-1.amazonaws.com

Thundercomm Turbox™ C6125/CM6125 SOM

Datasheet

Rev. V1.2 Aug 23, 2021

DN: tc-h-13112

Empowering Every IoT Device with Our Technology

Thundercomm Turbox™ C6125/CM6125 SOM Datasheet

Copyright© 2021 Thundercomm Technology Co., Ltd. All rights reserved.

Revision History

Version Date Description

V1.0 Mar 16, 2021 Initial release.

V1.1 Aug 12, 2021

Add the following sections:

1.5.Stencil design and aperture

1.6.Module laser marking

V1.2 Aug 23, 2021

Change max VBAT/ VBATT_SNS_P from 4.75V to 4.6V in the following sections:

3.1. Absolute maximum ratings

3.2. Operating conditions



Table List

Table 1-1. Key features and performance of QCM6125/QCS625 processor

Table 1-2. Key features and performance of C6125/CM6125 SOM

Table 2-1. Interface parameter definitions

Table 2-2. Pin List

Table 2-3. Power supply pin description

Table 2-4. Signal-control pin description


Table 2-6. Camera pin description

Table 2-7. MIPI display serial interface pin description

Table 2-8. GPIO QUP configuration

Table 2-9. QCM6125 GPIO pad description

Table 2-10. PMIC GPIO pad description

Table 2-11. SDC2 pad description

Table 2-12. UIM pad description

Table 2-13. SWR, SLIMBus and I2S pad description

Table 2-14. RF pad description

Table 3-1. Absolute rating condition

Table 3-2. Operating condition

Table 3-3. Output power specification

Table 3-4. Digital GPIO characteristics

Table 3-5. SD card digital I/O characteristics

Table 3-6. Supported MIPI_CSI standards and exceptions

Table 3-7. Supported MIPI_DSI standards and exceptions

Table 3-8. Supported USB standards and exceptions

Table 3-9. Supported DP standards and exceptions

Table 3-10. Supported SLIMbus standards and exceptions

Table 3-11. Supported SDIO standards and exceptions

Table 3-12. Supported I2S standards and exceptions

Table 3-13. I2S timing characteristics

Table 3-14. Digital microphone parameters

Table 3-15. Supported I2C standards and exceptions


Table 3-17. SPI parameters

Table 3-18. RGB LED parameters

Table 3-19. Flash drive LED parameters

Table 3-20. Thermal test condition

Table 3-21. Thermal test result



About This Document

Illustrations in this documentation might look different from your product.

Depending on the model, some optional accessories, features, and software programs might not be available on

your device.

Depending on the version of operating systems and programs, some user interface instructions might not be

applicable to your device.

Documentation content is subject to change without notice. Thundercomm makes constant improvements on

the documentation of your computer, including this guidebook.


- 1 -

Table of Contents

Chapter 1. Overview .............................................................................................................. - 2 -

1.1. Key features ...................................................................................................................................... - 2 -

1.2. Hardware block diagram .................................................................................................................. - 3 -

1.3. Mechanical size ................................................................................................................................ - 4 -

1.4. Package dimensions ......................................................................................................................... - 4 -

1.5. Stencil design and aperture .............................................................................................................. - 5 -

1.6. Module laser marking ...................................................................................................................... - 5 -

Chapter 2. Interfaces Description ........................................................................................... - 7 -

2.1. Interface parameter definitions ....................................................................................................... - 7 -

2.2. Pin description .................................................................................................................................. - 7 -

Chapter 3. Electrical Characteristics ..................................................................................... - 25 -

3.1. Absolute maximum ratings............................................................................................................. - 25 -

3.2. Operating conditions ...................................................................................................................... - 25 -

3.3. Output power ................................................................................................................................. - 25 -

3.4. Digital-logic characteristics ............................................................................................................. - 26 -

3.5. MIPI ................................................................................................................................................ - 26 -

3.6. USB interface .................................................................................................................................. - 27 -

3.7. Display port .................................................................................................................................... - 27 -

3.8. SLIMbus .......................................................................................................................................... - 27 -

3.9. SD Interface .................................................................................................................................... - 27 -

3.10. I2S ............................................................................................................................................... - 27 -

3.11. Digital microphone PDM interface ............................................................................................. - 29 -

3.12. I2C ............................................................................................................................................... - 29 -

3.13. I3C ............................................................................................................................................... - 29 -

3.14. SPI ............................................................................................................................................... - 29 -

3.15. Fuel gauge ................................................................................................................................... - 30 -

3.16. LEDs ............................................................................................................................................ - 30 -

3.17. PWM ........................................................................................................................................... - 30 -

3.18. Power consumption .................................................................................................................... - 31 -

3.19. Thermal....................................................................................................................................... - 31 -

3.20. RF performance .......................................................................................................................... - 31 -

Appendix 1. Notices ............................................................................................................ - 32 -

Appendix 2. Trademarks ..................................................................................................... - 34 -


- 2 -

Chapter 1. Overview

The CM6125/C6125 SOM is a cost-effective AI computing module to provide highly intelligent experiences for IoT

products. Its design is based on the Qualcomm® QCM6125/QCS6125 platform which can be taken as a successor of

Snapdragon 660 platform. Powered by the third generation Qualcomm AI Engine: Adreno 610 GPU and Hexagon

686 DSP (dual-HVX512), the 6125 platform can provide advanced on-device imaging and computing like smart

cropping, 3D face recognition, and object detection. It is an ideal platform for customers to design smarter and

more engaging products to the market.

1.1. Key features

The following tables present the detailed features and performances on Thundercomm Turbox™ C6125/CM6125

SOM.

Table 1-1. Key features and performance of QCM6125/QCS6125 processor

QCM6125/QCS6125 processor

Application Processor Customized 64-bit Arm v-8.0 compliant applications processor (Qualcomm® Kryo™

260 CPU), qual Kryo Gold 2.0GHz, qual Kryo Silver 1.8GHz

DSP Compute DSP with HVX (dual-HVX512)

GPU Qualcomm® Adreno™ GPU 610 at 950 MHz GPU with 64-bit addressing

Display Interface One 4-lane DSI D-PHY 1.2 at 1.5 Gbps per lane, split link supported, FHD+,

DisplayPort 1.4, Up to FHD+ (1080 × 2520)

Camera Module

Three 4-lane CSIs D-PHY 1.2 at 2.5 Gbps per lane,

2x ISP 14 bit: 16 + 16 MP, and 25 MP at 30 fps ZSL;

Real-time sensor input resolution: 16 + 16 MP;

Connectivity 1x USB 3.1 with DP supported

Table 1-2. Key features and performance of C6125/CM6125 SOM

C6125/CM6125 SOM

Processor QCM6125/QCS6125

Operating System Android Q

Memory

eMCP (either-or):

32GB eMMC v5.1+16Gb LPDDR4X

32GB eMMC v5.1+24Gb LPDDR4X

Display I/F 1x 4-lane DSI D-PHY 1.2

Camera I/F 3x 4-lane CSI D-PHY 1.2

Audio I/F

SLIMBUS

Soundwire

MI2S (up to 4)

USB 1x USB 3.1 with DP supported

WLAN WCN3950, Support 1 x 1, 802.11 a/b/g/n/ac, support Bluetooth + LE5.x + HS


- 3 -

RF Bands

(CM6125 only)

EMEA:

LTE: B1 B2 B3 B4 B5 B7 B8 B20 B28(A+B) B38 B39 B40 B41

WCDMA: B1 B2 B4 B5 B8

GSM: 850/900/1800/1900

CHN:

LTE: B1 B3 B5 B8 B34 B38 B39 B40 B41

WCDMA: B1 B8

GSM: 900/1800

North America:

LTE: B2 B4 B5 B7 B12 B13 B17 B25 B66 B71 B41

WCDMA: B2 B4 B5

Japan:

LTE: B1 B3 B5 B8 B18 B19 B26 B28(A+B) B41

WCDMA: B1 B6 B8 B19

UIM 2 x

QUP Up to 10 on GPIO, support UART, I2C, I3C, SPI

SDIO 1 x 4-bit, SD 3.0, SD/MMC card, eMMC NAND

JTAG On board JTAG test points

Dimensions and Form Factor

Size: 34 mm x 35 mm (C6125), 51 mm x 35mm (CM6125)

Weight: TBD

Interface form factor: LGA

Operating Temperature -20℃ to 70℃

RoHS All hardware components are fully compliant with EU RoHS directive

1.2. Hardware block diagram

Figure 1-1. Turbox™ C(M)6125 SOM Hardware System Block Diagram


- 4 -

1.3. Mechanical size

Turbox C6125 SOM: 34 mm x 35 mm x 3.05 mm.

Figure 1-2. C6125 SOM Dimension

Turbox CM6125 SOM: 51 mm x 35 mm x 3.05 mm.

Figure 1-3. CM6125 SOM Dimension

1.4. Package dimensions

Figure 1-4. CM6125 Package Dimensions


- 5 -

1.5. Stencil design and aperture

To supply sufficient soldering paste and keep reliable soldering joints, add the thickness of stencil partly on

the top surface. The stencil aperture for single sheet cannot be greater than 3.0mm × 4.0mm and the exceeded

part should be divided into smaller apertures with applicable shelves. A clearance of over 2.0mm should be

kept between the outward end of the aperture and the component if there are components around the

module.

NOTE:

For the convenience of heating and repairing, it is recommended that no components should be placed in the area at the backside of the module on PCB.

In order to avoid reverse polarity of the module, it is recommended to use asymmetric pads at the bottom of the module to identify the module polarity during module placement.

It is not recommended to add any silkscreen in the area where the module is mounted to avoid the height that may influence the solder paste printing and soldering quality.

When there is a need to step-up the stencil, all 01005/0201, 0.4mm-pitch and 0.5mm-pitch components should be kept over 5.0mm away from the stepped-up area to avoid solder bridging that is caused by thicker solder paste.

Figure 1-5. Stencil Aperture Diagram

Requirement description

Stencil thickness

Area of the module should be partly stepped-up to 0.13mm-0.15mm.

Pads on four sides

The aperture for each single pad should be centered with area reduced to 75%-85%. And the shape should be rectangle with round chamfers (as shown in the left figure).

Pads at four corners

The stencil aperture should be designed with 60%~65% area of the corresponding pad (as shown in the left figure).

Ground pads at the center

The stencil aperture should be designed with 60%~65% area of the corresponding pad (as shown in the left figure).

Arc-shaped pad

There is no need to design stencil apertures for the arc-shaped pad marked in wathet blue color.

1.6. Module laser marking

Refer to the module laser marking of Turbox C6125/CM6125 as Figure 1-6:


- 6 -

Figure 1-6. Laser Marking of C6125/CM6125 SOM

Table 2-1. Module laser marking description

1. Company name/logo 5. Serial number

2. Product name 6. IMEI number

3. PCBA version 7. QR code

4. Product number

NOTE:

Figure 1-6 is for reference only and may vary with the specific module. The part number may be updated. Please confirm with the supplier about the accurate information.


- 7 -

Chapter 2. Interfaces Description

This chapter introduces all the interfaces definitions, aiming to guide developer to design with Thundercomm Turbox™ C6125/CM6125 SOM.

2.1. Interface parameter definitions

Table 2-1. Interface parameter definitions

Symbol Description

AI Analog input

AO Analog output

B Bidirectional digital with CMOS input

DI Digital input (CMOS)

DO Digital output (CMOS)

H High-voltage tolerant

nppdpukp

Programmable pull resistor. The default pull direction is indicated using capital letters and is a prefix to other programmable options:

NP: pdpukp = default no-pull with programmable options following the colon (:)

PD: nppukp = default pull-down with programmable options following the colon (:)

PU: nppdkp = default pull-up with programmable options following the colon (:)

KP: nppdpu = default keeper with programmable options following the colon (:)

KP Contains an internal weak keeper device (keepers cannot drive external buses)

NP Contains no internal pull

OD Open drain

PD Contains an internal pull-down device

PI Power input

PO Power output

PU Contains an internal pull-up device

2.2. Pin description

Figure 2-1. Turbox™ CM6125/C6125 LGA PIN Map (Top View)

NOTE: The additional pins of CM6125 have been allocated to an independent group at the left side of LGA.


- 8 -

Table 2-2. Pin List

Pin # Pin name Voltage IO Description Wake-up (yes/no)

GPIO#

44 CSI0_A0_CLK_M CSI AI, AO CSI 0, differential clock – minus

45 CSI0_NC_CLK_P CSI AI, AO CSI 0, differential lane 1 – plus

42 CSI0_B0_LN0_P CSI AI, AO CSI 0, differential lane 0 – plus

43 CSI0_C0_LN0_M CSI AI, AO CSI 0, differential lane 0 – minus

13 CSI0_B1_LN1_M CSI AI, AO CSI 0, differential lane 1 – minus

14 CSI0_A1_LN1_P CSI AI, AO CSI 0, differential lane 0 – plus

11 CSI0_C1_LN2_P CSI AI, AO CSI 0, differential lane 1 – plus

12 CSI0_A2_LN2_M CSI AI, AO CSI 0, differential lane 2 – minus



40 CSI1_NC_CLK_P CSI AI, AO CSI 1, differential clock – plus











25 CSI2_NC_CLK_P CSI AI, AO CSI 2, differential clock – plus









35 CCI_I2C_SCL0 1.8 B-PD:nppukp B

Configurable I/O Dedicated camera control interface I2C 0 clock

GPIO_38

36 CCI_I2C_SDA0 1.8 B-PD:nppukp B

Configurable I/O Dedicated camera control interface I2C 0 serial data

GPIO_37

52 CCI_I2C_SCL1 1.8 B-PD:nppukp B

Configurable I/O Dedicated camera control interface I2C 1 clock

GPIO_40

58 CCI_I2C_SDA1 1.8 B-PD:nppukp B

Configurable I/O Dedicated camera control interface I2C 1 serial data

GPIO_39

64 CAM_MCLK0 1.8 B-PD:nppukp DO DO

Configurable I/O Camera master clock 0 QDSS trace data bit 5 A

GPIO_34



GPIO_35



Y GPIO_36

51 CAM_MCLK3 1.8

B-PD:nppukp DO DO DO DI DO

Configurable I/O Camera control interface timer 4 Global general-purpose clock 2 B Camera master clock 3 Camera control interface async 1 QDSS trace data bit 12 A

Y GPIO_44

78 MIPI_DSI0_CLK_P DSI AO DSI0 differential clock – plus

95 MIPI_DSI0_CLK_M DSI AO DSI0 differential clock – minus

96 MIPI_DSI0_L0_P DSI AO DSI0 differential lane 0 – plus

79 MIPI_DSI0_L0_M DSI AO DSI0 differential lane 0 – minus


76 MIPI_DSI0_L1_M DSI AO DSI0 differential lane 1– minus





46 MIPI_DSI1_CLK_P DSI AO DSI1 differential clock – plus

47 MIPI_DSI1_CLK_M DSI AO DSI1 differential clock – minus

276 DP_AUX_P AI, AO DisplayPort auxiliary channel – plus

265 DP_AUX_M AI, AO DisplayPort auxiliary channel – minus

210 USB0_HS_DP AI, AO USB high-speed data – plus

209 USB0_HS_DM AI, AO USB high-speed data – minus

277 USB0_SS_RX0_P AI USB super-speed receive 0 – plus

278 USB0_SS_RX0_M AI USB super-speed receive 0 – minus

279 USB0_SS_TX0_P AI, AO USB super-speed transmit 0 – plus

280 USB0_SS_TX0_M AI, AO USB super-speed transmit 0 – minus

225 USB0_SS_RX1_P AI USB super-speed receive 1 – plus

226 USB0_SS_RX1_M AI USB super-speed receive 1 – minus

227 USB0_SS_TX1_M AI, AO USB super-speed transmit 1 – minus

228 USB0_SS_TX1_P AI, AO USB super-speed transmit 1 – plus

2 SDC2_CMD 1.8/2.97 BH-NP: dpukp

Secure digital controller 2 command

21 SDC2_CLK 1.8/2.97 BH-PD: nppukp

Secure digital controller 2 clock

20 SDC2_DATA_0 1.8/2.97 BH-NP: nppukp

Secure digital controller 2 data bit 0




- 9 -


GPIO#





59 SM_GPIO_00 1.8

B-PD:nppukp DI DI B DO

Configurable I/O QUP 0 SE0, lane 0: SPI_MISO QUP 0 SE0, lane 0: UART_CTS QUP 0 SE0, lane 0: I2C_SDA QDSS trace data bit 6 B

57 SM_GPIO_01 1.8

B-PD:nppukp DO DO B DO

Configurable I/O QUP 0 SE0, lane 1: SPI_MOSI QUP 0 SE0, lane 1: UART_RFR QUP 0 SE0, lane 1: I2C_SCL QDSS trace data bit 7 B

Y

60 SM_GPIO_02 1.8

B-PD:nppukp DO DO DO

Configurable I/O QUP 0 SE0, lane 2: SPI_SCLK QUP 0 SE0, lane 2: UART_TX QDSS trace data bit 8 B

62 SM_GPIO_03 1.8

B-PD:nppukp DO DI DO

Configurable I/O QUP 0 SE0, lane 3: SPI_CS_N QUP 0 SE0, lane 3: UART_RX QDSS trace data bit 9 B

Y

82 SM_GPIO_04 1.8 B-PD:nppukp B

Configurable I/O QUP 0 SE1, lane 0: I2C_SDA

Y


Configurable I/O QUP 0 SE1, lane 1: I2C_SCL

100 SM_GPIO_06 1.8

B-PD:nppukp DI DI B

Configurable I/O QUP 0 SE2, lane 0: SPI_MISO QUP 0 SE2, lane 0: UART_CTS QUP 0 SE2, lane 0: I2C_SDA

119 SM_GPIO_07 1.8

B-PD:nppukp DO DO B

Configurable I/O QUP 0 SE2, lane 1: SPI_MOSI QUP 0 SE2, lane 1: UART_RFR QUP 0 SE2, lane 1: I2C_SCL

114 SM_GPIO_08 1.8 B-PD:nppukp DO DO

Configurable I/O QUP 0 SE2, lane 2: SPI_SCLK QUP 0 SE2, lane 2: UART_TX

101 SM_GPIO_09 1.8 B-PD:nppukp DO DI

Configurable I/O QUP 0 SE2, lane 3: SPI_CS_N QUP 0 SE2, lane 3: UART_RX

Y

128 SM_GPIO_14 1.8

B-PD:nppukp B DO DO

Configurable I/O QUP 0 SE3, lane 0: I2C_SDA QUP 0 SE3, lane 2: UART_TX QDSS trigger output 1 B

Y

139 SM_GPIO_15 1.8

B-PD:nppukp B DI DO

Configurable I/O QUP 0 SE3, lane 1: I2C_SCL QUP 0 SE3, lane 3: UART_RX QDSS trigger output 0 B

Y

138 SM_GPIO_20 1.8


Configurable I/O QUP 1 SE3, lane 2: SPI_SCLK QUP 1 SE3, lane 2: I2S2_DATA0 QDSS trace data bit 4 B

137 SM_GPIO_21 1.8


Configurable I/O QUP 1 SE3, lane 3: SPI_CS_N QUP 1 SE3, lane 3: I2S2_DATA1 QDSS trace data bit 5 B

Y

255 SM_GPIO_22 1.8

B-PD:nppukp DO DO BB DI

Configurable I/O Global general-purpose clock 3 B QUP 1 SE0, lane 0: SPI_MISO QUP 1 SE0, lane 0: I3C_SDA QUP 1 SE0, lane 0: I2C_SDA QUP 1 SE0, lane 0: UART_CTS

Y

267 SM_GPIO_23 1.8

B-PD:nppukp DO BB DO

Configurable I/O QUP 1 SE0, lane 1: SPI_MOSI QUP 1 SE0, lane 1: I3C_SCL QUP 1 SE0, lane 1: I2C_SCL QUP 1 SE0, lane 1: UART_RFR


Configurable I/O QUP 1 SE0, lane 2: SPI_SCLK QUP 1 SE0, lane 2: UART_TX



Y

178 SM_GPIO_26 1.8 B-PD:nppukp DO

Configurable I/O QUP 1 SE0, lane 4: SPI1_CS1

Y


Configurable I/O QUP 1 SE0, lane 5: SPI1_CS2

Y

61 SM_GPIO_30 1.8

B-PD:nppukp DI DI B


55 SM_GPIO_31 1.8

B-PD:nppukp DO DO B


66 SM_GPIO_32 1.8

B-PD:nppukp DO DO DI

Configurable I/O QUP 1 SE1, lane 2: SPI_SCLK QUP 1 SE1, lane 2: UART_TX Boot configuration control bit 2



Y


Configurable I/O QDSS trace data bit 1 A


- 10 -


GPIO#


Configurable I/O Camera control interface timer 2 QDSS trace data bit 8 A

Y

56 SM_GPIO_43 1.8


Configurable I/O Camera control interface timer 1 Global general purpose clock 2 A QDSS trace data bit 2 A

Y

247 SM_GPIO_45 1.8


Configurable I/O Camera control interface timer 0 Global general-purpose clock 1 A QDSS trace data bit 13 A

Y

65 SM_GPIO_46 1.8


Configurable I/O Camera control interface timer 3 Global general-purpose clock 1 B QDSS trace data bit 14 A

73 SM_GPIO_47 1.8 B-PD:nppukp DI DO

Configurable I/O Camera control interface async 0 QDSS trace data bit 15 A

Y


Configurable I/O Camera control interface async 2 QDSS trace data bit 4 A




Configurable I/O Tx level may degrade GNSS receiver (D) PA transmit indicator

230 SM_GPIO_53 1.8

B-PD:nppukp DI B DI

Configurable I/O Tx level may degrade GNSS receiver (A) Generic RF controller bit 1 Boot configuration control bit 13

281 SM_GPIO_54 1.8 B-PD:nppukp B DI

Configurable I/O Generic RF controller bit 2 Boot configuration control bit 14

50 SM_GPIO_55 1.8

B-PD:nppukp DI B DI

Configurable I/O Tx level may degrade GNSS receiver (B) Generic RF controller bit 3 Boot configuration control bit 6


Configurable I/O Generic RF controller bit 5

75 SM_GPIO_58 1.8

B-PD:nppukp DI DO B

Configurable I/O Tx level may degrade GNSS receiver (E) Global general-purpose clock 3 A Generic RF controller bit 8

85 SM_GPIO_59 1.8 B-PD:nppukp DI B

Configurable I/O Tx level may degrade GNSS receiver (F) Generic RF controller bit 9

Y


Configurable I/O MDP vertical sync – primary QDSS trace data bit 0 A

Y


Configurable I/O MDP vertical sync – secondary QDSS trace control A

Y


Configurable I/O MDP vertical sync – external QDSS trace clock A

Y



Y





Y


Configurable I/O Boot configuration control bit 15 QDSS trace data bit 14 B

Y

124 SM_GPIO_87 1.8 B-PD:nppukp DI

Configurable I/O Boot configuration control bit 1

116 SM_GPIO_88 1.8 B-PD:nppukp Configurable I/O Y


Configurable I/O MDP vertical sync – primary

Y

99 SM_GPIO_90 1.8 B-PD:nppukp Configurable I/O


Configurable I/O QDSS trace data bit 10 B

Y



Y

118 SM_GPIO_93 1.8 B-PD:nppukp B-PD:nppukp Y



Y


Configurable I/O QDSS trigger input 0 B

Y

53 SM_GPIO_97 1.8 B-PD:nppukp DI

Configurable I/O MDP vertical sync – secondary B

Y


91 SM_GPIO_100 1.8

B-PD:nppukp DI DI DO

Configurable I/O Boot configuration control bit 4 DP_HOT_PLUG_DETECT QDSS trace data bit 12 B

Y


Configurable I/O Boot configuration control bit 5 QDSS trigger input 1 A

Y


Configurable I/O Primary MI2S clock


Configurable I/O Primary MI2S Word Select QDSS trace control B


- 11 -


GPIO#


Configurable I/O Primary MI2S Data 0 QDSS trace data bit 0 B


Configurable I/O Primary MI2S Data 1 QDSS trace data bit 1 B



282 SM_GPIO_118 1.8

B-PD:nppukp DI DO DO

Configurable I/O Boot configuration control bit 3 Hi-fi DAC Clock 2 QDSS trace data bit 3 B

Y


Configurable I/O Hi-fi DAC Clock 1



Configurable I/O I2S 4 Data 0

Y


Configurable I/O I2S 4 Data 1

Y


Configurable I/O Digital MIC 0 Clock I2S 1 Clock


Configurable I/O Digital MIC 0 Data I2S 1 Word Select

Y


Configurable I/O Digital MIC 1 Clock I2S 1 Data 0


Configurable I/O Digital MIC 1 Data I2S 1 Data 1

Y

144 SM_GPIO_129 1.8

B-PD:nppukp DO DI B





102 SNS_I2C_SDA 1.8 B-PD:nppukp B

Configurable I/O QUP 1 SE2, lane 0: I2C_SDA

GPIO_28

103 SNS_I2C_SCL 1.8 B-PD:nppukp B

Configurable I/O QUP 1 SE2, lane 1: I2C_SCL

Y GPIO_29

72 WDOG_DISABLE 1.8

B-PD:nppukp DI B DI

Configurable I/O Tx level may degrade GNSS receiver (C) Generic RF controller bit 4 Boot configuration control bit 0

GPIO_56

120 USB_SS-H_HS-L_SEL 1.8 B-PD:nppukp DI DO

Configurable I/O USB PHY port select QDSS trace clock B

Y GPIO_102

268 FORCED_USB_BOOT 1.8 B-PD:nppukp DO

Configurable I/O Forced USB boot

Y GPIO_99

244 FORCED_USB_BOOT_POL_SEL 1.8 B-PD:nppukp DO D

Configurable I/O I2S 3 data 1 Forced USB boot polarity select

GPIO_104

127 SWR_CLK 1.8


Configurable I/O QUP 1 SE3, lane 0: SWR_CLK QUP 1 SE3, lane 0: SPI_MISO QUP 1 SE3, lane 0: I2S2_SCK

GPIO_18

84 SMR_DATA 1.8


Configurable I/O QUP 1 SE3, lane 1: SWR_DATA QUP 1 SE3, lane 1: SPI_MOSI QUP 1 SE3, lane 1: I2S2_WS

GPIO_19

222 SWR_TX_CLK-SLIMBUS_CLK 1.8

B-PD:nppukp DO DO DO DO

Configurable I/O SoundWire transmit clock Audio SLIMbus clock I2S 3 clock QDSS trigger output 1 A

GPIO_106

223 SWR_TX_DATA1-SLIMBUS_D1 1.8


Configurable I/O SoundWire transmit data 1 Audio SLIMbus data 1 I2S 3 data 0

GPIO_108

224 SWR_TX_DATA0-SLIMBUS_D0 1.8

B-PD:nppukp DO DO DO DO

Configurable I/O SoundWire transmit data 0 Audio SLIMbus data 0 I2S 3 word select QDSS trigger input 1 B

Y GPIO_107

240 SWR_RX_CLK-I2S_4_D2 1.8


Configurable I/O SoundWire receive data 0 I2S 3 data 2 QDSS trigger output 0 A

Y GPIO_110

241 SWR_RX_DATA0-I2S_4_D3 1.8


Configurable I/O SoundWire receive data 0 I2S 3 data 3 QDSS trigger input 0 A

Y GPIO_111

243 SWR_RX_DATA1 1.8 B-PD:nppukp DI

Configurable I/O SoundWire receive data 1

Y GPIO_112

248 RFFE3_CLK 1.8 B-PD:nppukp DO

Configurable I/O RF front-end 3 interface clock

GPIO_65

246 RFFE3_DATA 1.8


Configurable I/O Generic RF controller bit 37 RF front-end 3interface data Boot configuration control bit 8

GPIO_64

271 RFFE6_CLK 1.8 B-PD:nppukp DO


Y GPIO_70


- 12 -


GPIO#

270 RFFE6_DATA 1.8 B-PD:nppukp DO DI

Configurable I/O RF front-end 6 interface data Boot configuration control bit 7

GPIO_71

141 UIM1_PRESENT 1.8/2.95 B-PD:nppukp DO

Configurable I/O UIM1 presence detection

Y GPIO_79

140 UIM1_RESET 1.8/2.95 B-PD:nppukp DO

Configurable I/O UIM1 reset (dual voltage)

GPIO_78

130 UIM1_CLK 1.8/2.95 B-PD:nppukp DO

Configurable I/O UIM1 clock (dual voltage)

GPIO_77

129 UIM1_DATA 1.8/2.95 B-PD:nppukp DO

Configurable I/O UIM1 data (dual voltage)

GPIO_76

142 UIM2_PRESENT 1.8/2.95 B-PD:nppukp DO

Configurable I/O UIM2 presence detection

Y GPIO_75

194 UIM2_RESET 1.8/2.95 B-PD:nppukp DO

Configurable I/O UIM2 reset (dual voltage)

GPIO_74

132 UIM2_CLK 1.8/2.95 B-PD:nppukp DO

Configurable I/O UIM2 clock (dual voltage)

GPIO_73

131 UIM2_DATA 1.8/2.95 B-PD:nppukp DO

Configurable I/O UIM2 data (dual voltage)

GPIO_72

88 DBG_UART_RX 1.8 B-PD:nppukp DI B

Configurable I/O QUP 0 SE4, lane 3: UART_RX QUP 0 SE4, lane 1: I2C_SCL

Y GPIO_17

104 DBG_UART_TX 1.8 B-PD:nppukp DO B

Configurable I/O QUP 0 SE4, lane 2: UART_TX QUP 0 SE4, lane 0: I2C_SDA

GPIO_16

263 VREG_L5A_2P96 1.8/2.96 PO L5A LDO regulated output

170 VREG_L9A_1P8 1.8 PO L9A LDO regulated output

187 VREG_L10A_1P8 1.8 PO L10 LDO regulated output




264 VREG_L19A_1P8_UIM1 1.8/2.95 PO Power source for UIM1

86 VREG_L20A_1P8_UIM2 1.8/2.95 PO Power source for UIM2

251 VREG_L22A_2P96 1.8/2.96 PO L22 LDO regulated output

208 VDISP_P_OUT PO Display bias plus: positive LCD regulated output voltage

121 VDISP_M_OUT PO Display bias minus: negative LCD regulated output

207 VIB_DRV_LDO_P PO Power supply for Haptics drive

218 VCOIN 3V PI,PO Coin-cell charge and supply

163 USB_CC1 AI

OTG mode enable or CC1 pin for the USB Type-C connector (user programmable). Requires IEC protection.

149 USB_CC2 AI CC2 pin for the USB Type-C connector. Requires IEC protection.

205,206 USB_VBUS_CONN PI,PO

Input power from the source (USB), or output during USB-OTG. This is a power entry node for the charger and connects to the OVP circuitry.

195,196,197,202, VBATT PI,PO

Battery voltage node, connects to BATFET. Output is for charging, and input is for all other operations

198 BATT_THERM AI

Battery temperature input to ADC for measuring the pack temperature. It is used for charger safe operation and BMS/Qualcomm battery gauge.

153 VBATT_VSNS_P AI

Battery voltage sense input plus. Connect to the battery positive remote sense node or connect this directly to the battery positive node.

167 VBATT_VSNS_M AI

Battery voltage sense input minus. Connect to the battery negative remote sense node or connect this directly to the battery negative node.

181 BATT_ID AI Battery ID input to the ADC. It can be used for missing battery detection.

182,183,184, VPH_PWR PI,PO Primary system supply node, SCHG regulated node

150 SMB_VCHG_P MV Configurable; default digital input with 10 µA pull-down.

PMI_GPIO7

151 SMB_VCHG_M MV Configurable; default digital input with 10 µA pull-down.

PMI_GPIO8

199 PMI_GPIO_01_USB_CONN_THERM MV Configurable; default digital input with 10 µA pull-down.

165 PMI_GPIO_02 MV Configurable; default digital input with 10 µA pull-down.

189 PMI_GPIO_03_CHG_SKIN_THERM MV Configurable; default digital input with 10 µA pull-down.

169 PMI_GPIO_04_SMB_THERM MV Configurable; default digital input with 10 µA pull-down.

188 PMI_GPIO_05 LV Configurable; default digital input with 10 µA pull-down.

164 PMI_GPIO_06 LV Configurable; default digital input with 10 µA pull-down.

257 PM_GPIO_01_WCD_DIV_CLK1 LV Configurable; default digital input with 10 µA pull-down.


- 13 -


GPIO#

152 PM_GPIO_02 LV Configurable; default digital input with 10 µA pull-down.

275 PM_GPIO_03_CAM_FLASH_THERM LV Configurable; default digital input with 10 µA pull-down.

166 PM_GPIO_04 LV Configurable; default digital input with 10 µA pull-down.

215 PM_GPIO_07_PA1_THERM MV Configurable; default digital input with 10 µA pull-down.

154 PM_GPIO_08_BL_PWM_OUT MV Configurable; default digital input with 10 µA pull-down.

168 PM_GPIO_09 MV Configurable; default digital input with 10 µA pull-down.

216 CBL_PWR_N DI Cable power-on ground switch (200 kΩ internal PU)

176 BOOT_PWR AO

Auxiliary low dropout (LDO) output – 50 mA (minimum) output supply. Also used to supply BOOT_CAP.

185 PM_OPTION AI Option hardware configuration control

159 LN_BB_CLK3 DO NFC clock

122 PMI_DISP_HW_EN DI Hardware enable for LCD display

201 PMI_USB_OPTION DI Option pin is used to select different PON options based on pull-down (PD) resistor value

193 KYPD_PWR_N DI Power-on key ground switch

200 KYPD_VOL_UP_N LV Configurable; default digital input with 10 µA pull-down

PM_GPIO_05

155 KYPD_VOL_DOWN_N DI Reset input to PM

177 RED_LED AO RGB LED high-side current source for the red LED

191 GREEN_LED AO RGB LED high-side current source for the green LED

204 BLUE_LED AO RGB LED high-side current source for the blue LED

180 FLASH_LED1 AO Flash high-side curent source for LED1. It connects to a node of flash LED.

211 FLASH_LED2 AO Flash high-side current source for LED2. It connects to a node of flash LED.

87 ANT_FM_RX RF_IN FM antenna

146 ANT_2G_5G_WLAN RF_IO WIFI antenna

98,145,147,286,287,288,289,290,291,292,293,294,295, GND Ground

15,16,17,32,33,34,48,49,69,70,71,92,107,109,110,111,112,113,123,134,135,136,157,158,160,161,171,172,173,174,175,190,203,214,217,219,220,221,234,235,236,237,238,239,245,252,253,256,269

NC No connection

CM6125 version only

2 ANT_DRX RF_IO Diversity Antenna

4 SM_GPIO_32



5 SDR_GRFC_0

6 SDR_GRFC_1

7 SDR_GRFC_2

8 RFFE3_DATA


GRFC37 RFFE3_DATA BOOT_CONFIG(8)

GPIO_64

9 RFFE3_CLK B-PD:nppukp DO


GPIO_65

10 RFFE6_DATA B-PD:nppukp DO DI


GPIO_71

11 RFFE6_CLK B-PD:nppukp DO


GPIO_70

13 ANT_GPS_L1_IN RF_IN GPS_ANTENNA

15 SDR_GRFC_5

16 SDR_GRFC_6

17 SDR_GRFC_7

18 RFFE5_CLK B-PD:nppukp DO DO

Configurable I/O Generic RF controller bit 35 RF front-end 5 interface clock

GPIO_69

19 RFFE5_DATA


Configurable I/O Generic RF controller bit 32 RF front-end 5 interface data Boot configuration control bit 12

GPIO_68

20 SM_GPIO_118



21 SM_GPIO_87 B-PD:nppukp DI


48 ANT_PRI Primary_Antenna

1,3,12,14,47,49,54,56,57,58,59 GND

22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,

NC


- 14 -

2.2.1. Power supply interface

Below table describes all interfaces of SOM power supply. For the detailed parameters, please refer Chapter 3. Electrical Characteristics.

Table 2-3. Power supply pin description

Pin Name Pin# Type Description

VREG_L20A_1P8_UIM2 86 PO UIM2 (1.8/2.95)

VREG_L14A_1P8 106 PO WCD_VDD_BUCK (1.8 V)

VREG_L12A_1P8 156 PO Camera sensors (1.8 V)

VREG_L9A_1P8 170 PO LPDDR4x_VDD1 (1.8), VDD_PX3, VDD_PX7, WCD (1.8 V), WCN (1.8 V),

Sensors (1.8 V), RFFE (1.8 V), WSA (1.8 V)

VREG_L15A_3P104 186 PO USB3 (3.1)

VREG_L10A_1P8 187 PO USB2 (1.8 V), USB3.1 (1.8 V), QFPROM (1.8 V), UFS (1.8V), VDDPX_11

VREG_L22A_2P96 251 PO MEM_SD_MMC_VDD (2.96)

VREG_L5A_2P96 263 PO

VREG_L19A_1P8_UIM1 264 PO UIM1 (1.8/2.95)

VPH_PWR 182,183,184 PI Primary system supply node, SCHG regulated node

VBATT 195,196,197,202 PI,PO Battery voltage node

VCOIN 218 PI Coin-cell charge and supply

USB_VBUS_CONN 205,206 PI,PO Input power from the source (USB), or output during USB-OTG.

VDISP_M_OUT 121 PO Display bias minus

VDISP_P_OUT 208 PO Display bias plus

BOOT_PWR 176 AO Auxiliary low dropout (LDO) output

RED_LED 177 PO RGB LED high-side current source for the red LED

FLASH_LED1 180 PO Flash high-side current source for LED1

GREEN_LED 191 PO RGB LED high-side current source for the green LED

BLUE_LED 204 PO RGB LED high-side current source for the blue LED

FLASH_LED2 211 PO Flash high-side current source for LED2

VIB_DRV_LDO_P 207 PO Power supply for Haptics driver

GND 98,145,147,286,287,288,289,2

90,291,292,293,294,295 PI Ground

2.2.2. Signal control interface


PAD Name Pad Voltage Type Description Notes

KYPD_PWR_N 193 1.8 DI Power on/off key signal, internally pulled up to 1.8V Active low level

CBL_PWR_N 216 1.8 DI Cable power-on; internal pull-up to 1.8 V; initiates power-on when grounded

Active low level

KYPD_VOL_DOWN_N 155 PU 1.8 DI Reset input to PM (40 kΩ internal PU)

WDOG_DISABLE 72 1.8 DI Gates the watchdog expired signal

USB_PHY_PS 120 - DI 1.8V push-pull tri-state output indicating CC1 or CC2 connection (orientation)

QCM6125(GPIO102) & PMI632(CC_OUT)

PMI_DISP_HW_EN 122 1.8 DI Hardware enables for LCD display PMI632

VBATT_VSNS_P 153 - AI Battery voltage sense input plus PMI632

VBATT_VSNS_M 167 - AI Battery voltage sense input minus PMI632

BATT_ID 181 - AI Battery ID input to the ADC PMI632

PM_OPTION 185 - AI Option hardware configuration control PM6125


- 15 -

PAD Name Pad Voltage Type Description Notes

BATT_THERM 198 - AI Battery temperature input to ADC for measuring the pack temperature.

PMI632

KYPD_VOL_UP_N 200 - LV Volume + Key PM6125

PMI_USB_OPTION 201 - - To select different PON options based on PD resistor value PMI632

FORCED_USB_BOOT_POL_SEL 244 1.8 B-PD:nppukp DO DI

Forced USB boot polarity select, default SEL=L, FORCE_USB_BOOT=H

QCM6125

FORCED_USB_BOOT 268 Forced a USB boot QCM6125

LN_BB_CLK3 159 - DO Default NFC clock PM6125

BATT_ID is used for the different battery pack (ranges from 7.5k to 450kohm) identification.

BATT_THERM reports the temperature of the battery pack to system. In general, it is recommended to use NTC 100K 1% B=4350 thermistor in the battery pack, and 100Kohm resistance for the non-battery device.

Default settings for USB_PHY_PS and FORCED_USB_BOOT_SEL has been defined in the SOM.

The EDL mode will be enabled once SM_FORCE_USB_BOOT pulled up to 1.8V.

Figure 2-2. Power Signal

2.2.3. USB interface and display port

The SOM supports a USB 3.1 interface and a DisplayPort 1.4 interface.


PAD Name Pad Typ. Description Notes

USB_CC1 163 AI OTG mode enable or CC1 pin for the USB Type-C connector PMI632

USB_CC2 149 AI CC2 pin for the USB Type-C connector. PMI632

USB0_HS_DM 209 AI,AO USB high-speed data – minus QCM6125

USB0_HS_DP 210 AI,AO USB high-speed data – plus QCM6125

USB0_SS_RX1_P 225 AI USB super-speed receive 1 – plus QCM6125

USB0_SS_RX1_M 226 AI USB super-speed receive 1 – minus QCM6125

USB0_SS_TX1_M 227 AO USB super-speed transmit 1 – minus QCM6125

USB0_SS_TX1_P 228 AO USB super-speed transmit 1 – plus QCM6125

USB0_SS_RX0_P 277 AI USB super-speed receive 0 – plus QCM6125

USB0_SS_RX0_M 278 AI USB super-speed receive 0 – minus QCM6125

USB0_SS_TX0_P 279 AO USB super-speed transmit 0 – plus QCM6125

USB0_SS_TX0_M 280 AO USB super-speed transmit 0 – minus QCM6125


- 16 -


DP_AUX_M 265 AI,AO DisplayPort auxiliary channel – minus QCM6125

DP_AUX_P 276 AI,AO DisplayPort auxiliary channel – plus QCM6125

SM_GPIO_100 91 DI DP_HOT_PLUG_DETECT QCM6125

The SOM do not support the USB DP function. If a DP device is detected by SM_GPIO_100, USB SS lanes will be

occupied by display port lanes respectively.

2.2.4. Camera module interface

The SOM supports 3 x 4-lane CSIs D-PHY, 1.2 at 2.5Gbps per lane.

Table 2-6. Camera pin description


CSI2_B2_LN3_P 3

AI, AO

CSI 2, differential lane 3 – plus

MIPI CSI

CSI2_C2_LN3_M 4 CSI 2, differential lane 3 – minus

CSI2_A2_LN2_M 5 CSI 2, differential lane 2 – minus

CSI2_C1_LN2_P 6 CSI 2, differential lane 2 – plus

CSI2_A1_LN1_P 7 CSI 2, differential lane 1 – plus

CSI2_B1_LN1_M 8 CSI 2, differential lane 1 – minus








CSI2_B0_LN0_P 23 CSI 2, differential lane 0 – plus

CSI2_A0_CLK_M 24 CSI 2, differential clock – minus

CSI2_NC_CLK_P 25 CSI 2, differential clock – plus















CAM_MCLK1 37

DO

Camera master clock 1

CAM_MCLK3 51 Camera master clock 3



CCI_I2C_SCL0 35 B-PD:nppukp B

Dedicated camera control interface I2C 0 serial clock

SOM internal 2.2k pull-up to 1.8V CCI_I2C_SDA0 36 Dedicated camera control interface I2C 0 serial data

CCI_I2C_SCL1 52 Dedicated camera control interface I2C 1 serial clock

CCI_I2C_SDA1 58 Dedicated camera control interface I2C 1 serial data

CCI I2C have 2.2kΩ pulled-up inside. In general, there are no external pulled-up be required.

3x CSI interfaces can set up multiple combination dependently with the use case.

Furthermore, the 4 lanes of CSI interface can be configured as 2-lane plus 1-lan interfaces or 1-lan plus 1-lane interface. Refer to the combination below.

DCLK➔DCLK_A DCLK➔DCLK_A DLN0➔DLN0_A DLN0➔DLN0_A


- 17 -

DLN1➔DLN1_A DLN2➔DLN0_B DLN2➔DLN0_B DLN3➔DCLK_B DLN3➔DCLK_B

2.2.5. MIPI display serial interface

The SOM supports 1 x 4-lane DSI D-PHY, 1.2 at 1.5Gbps per lane.

Table 2-7. MIPI display serial interface pin description

PAD Name Pad Type Description Notes

MIPI_DSI1_CLK_P 46

AO

DSI1 differential clock – plus

MIPI DSI

MIPI_DSI1_CLK_M 47 DSI1 differential clock – minus

MIPI_DSI0_L1_M 76 DSI0 differential lane 1 – minus


MIPI_DSI0_CLK_P 78 DSI0 differential clock – plus


MIPI_DSI0_L3_P 80 DSI0 differential lane 3 – plus



MIPI_DSI0_CLK_M 95 DSI0 differential clock – minus



2.2.6. QCM6125 GPIO interface

These GPIOs of QCM6125 are available as Qualcomm universal peripheral (QUP) interface ports that can be

configured for UART or/and SPI or/and I2C or/and I3C operation (Note: Only one protocol type can be selected in

each QUP engine at the same time).

There are 9 x QUP engines (Serial Engine item in below table).

I2C is a two-wire bus interface that can be routed to multiple devices; each bus line needs to be supplemented by a

2.2kΩ pull-up resistor.

Table 2-8. GPIO QUP configuration

GPIO Serial Engine Lane Multiplexed Interface

QUP0

0

SE0

0 UART_CTS SPI_MISO I2C_SDA

1 1 UART_RFR SPI_MOSI I2C_SCL

2 2 UART_TX SPI_SCLK

3 3 UART_RX SPI_CS_N

4 SE1

0 I2C_SDA

5 1 I2C_SCL

6

SE2





14 SE3

0/2 UART_TX I2C_SDA

15 1/3 UART_RX I2C_SCL

16 SE4

0/2 UART_TX I2C_SDA

17 1/3 UART_RX I2C_SCL

QUP1

22

SE0

0 UART_CTS SPI_MISO I2C_SDA I2C3_SDA

23 1 UART_RFR SPI_MOSI I2C_SCL I2C3_SCL



26 4 SPI1_CS1

27 5 SPI1_CS2

30

SE1





28 SE2 0 I2C_SDA


- 18 -

GPIO Serial Engine Lane Multiplexed Interface

29 1 I2C_SCL

18

SE3

0 SPI_MISO SWR_CLK I2S2_SCK

19 1 SPI_MOSI SWR_DATA I2S2_WS

20 2 SPI_SCLK I2S2_DATA0

21 3 SPI_CS_N I2S2_DATA1

Table 2-9. QCM6125 GPIO pad description

PAD Name PAD Voltage Wake-up Description

SM_GPIO_55 50 1.8V


SM_GPIO_97 53 Y Configurable I/O

SM_GPIO_33 54 Y Configurable I/O QUP 1 SE1, lane 3: SPI_CS_N QUP 1 SE1, lane 3: UART_RX

SM_GPIO_31 55


SM_GPIO_43 56 Y

Configurable I/O Camera control interface timer 1 Global general purpose clock 2 A QDSS trace data bit 2 A

SM_GPIO_01 57 Y

Configurable I/O QUP 0 SE0, lane 1: SPI_MOSI QUP 0 SE0, lane 1: UART_RFR QUP 0 SE0, lane 1: I2C_SCL QDSS trace data bit 7 B

SM_GPIO_00 59

Configurable I/O QUP 0 SE0, lane 0: SPI_MISO QUP 0 SE0, lane 0: UART_CTS QUP 0 SE0, lane 0: I2C_SDA QDSS trace data bit 6 B

SM_GPIO_02 60

Configurable I/O QUP 0 SE0, lane 2: SPI_SCLK QUP 0 SE0, lane 2: UART_TX QDSS trace data bit 8 B

SM_GPIO_30 61


SM_GPIO_03 62 Y

Configurable I/O QUP 0 SE0, lane 3: SPI_CS_N QUP 0 SE0, lane 3: UART_RX QDSS trace data bit 9 B

SM_GPIO_84 63 Configurable I/O QDSS trace data bit 10 A

SM_GPIO_46 65

Configurable I/O Camera control interface timer 3 Global general-purpose clock 1 B QDSS trace data bit 14 A

SM_GPIO_32 66


SM_GPIO_124 67 Y Configurable I/O I2S 4 Data 1

SM_GPIO_123 68 Y Configurable I/O I2S 4 Data 0

SM_GPIO_47 73 Y Configurable I/O Camera control interface async 0 QDSS trace data bit 15 A

SM_GPIO_57 74 Configurable I/O Generic RF controller bit 5

SM_GPIO_58 75

Configurable I/O Tx level may degrade GNSS receiver (E) Global general-purpose clock 3 A Generic RF controller bit 8


- 19 -


SM_GPIO_04 82 1.8V

Y Configurable I/O QUP 0 SE1, lane 0: I2C_SDA

SM_GPIO_05 83 Configurable I/O QUP 0 SE1, lane 1: I2C_SCL

SM_GPIO_59 85 Y Configurable I/O Tx level may degrade GNSS receiver (F) Generic RF controller bit 9


SM_GPIO_52 90 Configurable I/O Tx level may degrade GNSS receiver (D) PA transmit indicator

SM_GPIO_100 91 Y Configurable I/O Boot configuration control bit 4 QDSS trace data bit 12 B

SM_GPIO_90 99 Configurable I/O

SM_GPIO_06 100



SM_GPIO_27 105 Y Configurable I/O QUP 1 SE0, lane 5: SPI1_CS2

SM_GPIO_85 108 Y Configurable I/O QDSS trace data bit 11 A

SM_GPIO_08 114 Configurable I/O QUP 0 SE2, lane 2: SPI_SCLK QUP 0 SE2, lane 2: UART_TX





SM_GPIO_07 119


SM_GPIO_87 124 Configurable I/O Boot configuration control bit 1

SM_GPIO_101 125 Y Configurable I/O Boot configuration control bit 5 QDSS trigger input 1 A

SM_GPIO_92 126 Y Configurable I/O QDSS trace data bit 11 B

SM_GPIO_14 128 Y

Configurable I/O QUP 0 SE3, lane 0: I2C_SDA QUP 0 SE3, lane 2: UART_TX QDSS trigger output 1 B

SM_GPIO_80 133 Y Configurable I/O MDP vertical sync – primary QDSS trace data bit 0 A

SM_GPIO_21 137 Y

Configurable I/O QUP 1 SE3, lane 3: SPI_CS_N QUP 1 SE3, lane 3: I2S2_DATA1 QDSS trace data bit 5 B

SM_GPIO_20 138

Configurable I/O QUP 1 SE3, lane 2: SPI_SCLK QUP 1 SE3, lane 2: I2S2_DATA0 QDSS trace data bit 4 B

SM_GPIO_15 139 Y

Configurable I/O QUP 0 SE3, lane 1: I2C_SCL QUP 0 SE3, lane 3: UART_RX QDSS trigger output 0 B

SM_GPIO_119 143 Configurable I/O Hi-fi DAC Clock 1


- 20 -


SM_GPIO_129 144 1.8V


SM_GPIO_82 148 Y Configurable I/O MDP vertical sync – external QDSS trace clock A


SM_GPIO_26 178 Y Configurable I/O QUP 1 SE0, lane 4: SPI1_CS1

SM_GPIO_81 179 Y Configurable I/O MDP vertical sync – secondary QDSS trace control A


SM_GPIO_89 212 Y Configurable I/O MDP vertical sync – primary

SM_GPIO_95 213 Y Configurable I/O QDSS trigger input 0 B

SM_GPIO_48 229 Configurable I/O Camera control interface async 2 QDSS trace data bit 4 A

SM_GPIO_53 230

Configurable I/O Tx level may degrade GNSS receiver (A) Generic RF controller bit 1 Boot configuration control bit 13





SM_GPIO_45 247 Y

Configurable I/O Camera control interface timer 0 Global general-purpose clock 1 A QDSS trace data bit 13 A

SM_GPIO_117 249 Configurable I/O QDSS trace data bit 2 B

SM_GPIO_42 250 Y Configurable I/O Camera control interface timer 2 QDSS trace data bit 8 A

SM_GPIO_24 254 Configurable I/O QUP 1 SE0, lane 2: SPI_SCLK QUP 1 SE0, lane 2: UART_TX

SM_GPIO_22 255 Y

Configurable I/O Global general-purpose clock 3 B QUP 1 SE0, lane 0: SPI_MISO QUP 1 SE0, lane 0: I3C_SDA QUP 1 SE0, lane 0: I2C_SDA QUP 1 SE0, lane 0: UART_CTS

SM_GPIO_86 258 Y Configurable I/O Boot configuration control bit 15 QDSS trace data bit 14 B

SM_GPIO_126 259 Y Configurable I/O Digital MIC 0 Data I2S 1 Word Select

SM_GPIO_128 261 Y Configurable I/O Digital MIC 1 Data I2S 1 Data 1

SM_GPIO_114 262 Configurable I/O Primary MI2S Word Select QDSS trace control B


SM_GPIO_23 267

Configurable I/O QUP 1 SE0, lane 1: SPI_MOSI QUP 1 SE0, lane 1: I3C_SCL QUP 1 SE0, lane 1: I2C_SCL QUP 1 SE0, lane 1: UART_RFR


- 21 -


SM_GPIO_125 272 1.8V

Configurable I/O Digital MIC 0 Clock I2S 1 Clock

SM_GPIO_127 273 Configurable I/O Digital MIC 1 Clock I2S 1 Data 0

SM_GPIO_113 274 Configurable I/O Primary MI2S clock

SM_GPIO_54 281 Configurable I/O Generic RF controller bit 2 Boot configuration control bit 14

SM_GPIO_118 282 Y


SM_GPIO_83 283 Y Configurable I/O QDSS trace data bit 9 A

SM_GPIO_116 284 Configurable I/O Primary MI2S Data 1 QDSS trace data bit 1 B

SM_GPIO_115 285 Configurable I/O Primary MI2S Data 0 QDSS trace data bit 0 B

SNS_I2C_SDA 102 Configurable I/O QUP 1 SE2, lane 0: I2C_SDA

SNS_I2C_SCL 103 Configurable I/O QUP 1 SE2, lane 1: I2C_SCL

DBG_UART_RX 88 Configurable I/O QUP 0 SE4, lane 3: UART_RX QUP 0 SE4, lane 1: I2C_SCL

DBG_UART_TX 104 Configurable I/O QUP 0 SE4, lane 2: UART_TX QUP 0 SE4, lane 0: I2C_SDA

SWR_DATA 84

Configurable I/O QUP 1 SE3, lane 1: SWR_DATA QUP 1 SE3, lane 1: SPI_MOSI QUP 1 SE3, lane 1: I2S2_WS

SWR_CLK 127

Configurable I/O QUP 1 SE3, lane 0: SWR_CLK QUP 1 SE3, lane 0: SPI_MISO QUP 1 SE3, lane 0: I2S2_SCK

SWR_TX_CLK-SLIMBUS_CLK 222 SoundWire transmit clock/ Audio SLIMbus clock

SWR_TX_DATA1-SLIMBUS_D1 223 SoundWire transmit data1/ Audio SLIMbus data 1

SWR_TX_DATA0-SLIMBUS_D0 224 SoundWire transmit data0 / Audio SLIMbus data0

SWR_RX_CLK-I2S_4_D2 240 SoundWire receive clock / I2S 3 data 2

SWR_RX_DATA0-I2S_4_D3 241 SoundWire receive data0/ I2S 3 data 3

SWR_RX_DATA1 243 SoundWire receive data1

2.2.7. PMIC GPIO interface

GPIO interfaces of PM6125 and PMI632 are listed as below. GPIO features can be customed on PM6125/PMI632

device (special connections that can exist only in specific GPIO interface).

Table 2-10. PMIC GPIO pad description

PAD Name PAD Voltage Type Special Function Notes

PM_GPIO_02 152 1.8V

DI/DO

AOSS sleep indicator

PM6125 Configurable; default digital input with 10 μA pull-down

PM_GPIO_08_BL_PWM_OUT 154 VPH_PWR PWM_OUT for backlight

PM_GPIO_04 166 1.8V

PM_GPIO_09 168 VPH_PWR Unused

PM_GPIO_07_PA1_THERM 215 VPH_PWR Thermal detection with thermistor.

PM_GPIO_01_WCD_DIV_CLK1 257 1.8V Codec MCLK 9.6 MHz


- 22 -

PAD Name PAD Voltage Type Special Function Notes

PM_GPIO_03_CAM_FLASH_THERM 275 1.8V CAM/FLASH_THERM

PMI_GPIO_06 164 1.8V

Configurable; default digital input with 10 μA pull-down

PMI632

PMI_GPIO_02 165 VPH_PWR PMI632

PMI_GPIO_04_SMB_THERM 169 VPH_PWR PMI632

PMI_GPIO_05 188 1.8V PMI632

PMI_GPIO_03_CHG_SKIN_THERM 189 VPH_PWR PMI632

PMI_GPIO_01_USB_CONN_THERM 199 VPH_PWR PMI632

SMB_VCHG_P 150 VPH_PWR PMI632

SMB_VCHG_M 151 VPH_PWR PMI632

It is recommended to select 100K 1% B=4250 thermistor for temperature monitoring. Unused pin can be floating

for special features not implemented.

2.2.8. SD card slot

The SOM supports one 4-lane SDIO SD card slot.

Table 2-11. SDC2 pad description

PAD Name PAD Voltage Type Description Notes

SDC2_DATA_1 1

1.8 V or 2.95 V

BH-PD: nppukp


SDC2_CMD 2 BH-PD: nppukp

Secure digital controller 2 command

SDC2_DATA_3 18 BH-PD: nppukp






SDC2_CLK 21 BH-NP: dpukp

Secure digital controller 2 clock

SD_CARD_DET_N 233 1.8V B-PD:nppukp Configurable I/O GPIO_98

The SD_CARD_DET_N is used for SD card detection. The power signal becomes GND once the card been installed.

Figure 2-3. Power Signal

2.2.9. UIM

The SOM supports 2 x dual-voltage UIM (User Identifier Module).

Table 2-12. UIM pad description

PAD Name PAD Voltage Type Description

UIM1_DATA 129 1.8 V or 2.95 V B-PD:nppukp UIM1 data (dual voltage)


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PAD Name PAD Voltage Type Description

UIM1_CLK 130 DO UIM1 clock (dual voltage)

UIM1_RESET 140 UIM1 reset (dual voltage)

UIM1_PRESENT 141 UIM1 presence detection

UIM2_DATA 131

1.8 V or 2.95 V

UIM2 data (dual voltage)

UIM2_CLK 132 UIM2 clock (dual voltage)

UIM2_PRESENT 142 UIM1 presence detection

UIM2_RESET 194 UIM2 reset (dual voltage)

The UIM1_PRESENT and UIM2_PRESENT are high-level respectively for inserting SIM1 and SIM2 card.

2.2.10. SWR, SLIMbus and I2S

Table 2-13. SWR, SLIMBus and I2S pad description

PAD Name PAD Voltage GPIO# Description

SWR_CLK 127

1.8

GPIO_18 SWR_CLK I2S2_SCK

SMR_DATA 84 GPIO_19 SWR_DATA I2S2_WS

SWR_TX_CLK-SLIMBUS_CLK 222 GPIO_106 SoundWire transmit clock Audio SLIMbus clock I2S 3 clock

SWR_TX_DATA1-SLIMBUS_D1 223 GPIO_108 SoundWire transmit data 1 Audio SLIMbus data 1 I2S 3 data 0

SWR_TX_DATA0-SLIMBUS_D0 224 GPIO_107 SoundWire transmit data 0 Audio SLIMbus data 0 I2S 3 word select

SWR_RX_CLK-I2S_4_D2 240 GPIO_110 SoundWire receive data 0 I2S 3 data 2

SWR_RX_DATA0-I2S_4_D3 241 GPIO_111 SoundWire receive data 0 I2S 3 data 3

SWR_RX_DATA1 243 GPIO_112 SoundWire receive data 1

SM_GPIO_20 138 I2S2_DATA0

SM_GPIO_21 137 I2S2_DATA1

SM_GPIO_104 244 I2S 3 data 1

SM_GPIO_113 274 PRI_MI2S_SCK

SM_GPIO_114 262 PRI_MI2S_WS

SM_GPIO_115 285 PRI_MI2S_DATA0

SM_GPIO_116 284 PRI_MI2S_DATA1

SM_GPIO_125 272 I2S 1 SCK

SM_GPIO_126 259 I2S 1 WS

SM_GPIO_127 273 I2S 1 DATA0

SM_GPIO_128 261 I2S 1 DATA1

Some pins are shared mutually by SWR (Voltage Standing Wave Ratio), SLIMBus and I2S (Inter-IC Sound) features.

2.2.11. RF (Radio Frequency)

Table 2-14. RF pad description


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PAD Name PAD Voltage Type Description Notes

ANT_FM_RX 87 RF_IN FM headset antenna. If not used, connect to ground

WCN3950

ANT_2G_5G_WLAN 146 RF_IO WIFI 2G/5G antenna WCN3950

RFFE3_DATA 246, 8



8th pin is CM6125 RF only

RFFE3_CLK 248, 9 B-PD:nppukp DO



RFFE6_CLK 270,11 B-PD:nppukp DO



RFFE6_DATA 271,10

B-PD:nppukp DO DI



GND 1, 3, 12, 14, 47, 49, 54, 55, 56, 57, 58, 59

- Ground CM6125 RF only

ANT_DRX 2 Antenna DRX CM6125 RF only

SM_GPIO_32 4



CM6125 RF only

SDR_GRFC_0 5 CM6125 RF only



RFFE3_DATA 8



CM6125 RF only

RFFE3_CLK 9 B-PD:nppukp DO


CM6125 RF only

RFFE6_DATA 10

B-PD:nppukp DO DI


CM6125 RF only

RFFE6_CLK 11 B-PD:nppukp DO


CM6125 RF only

ANT_GPS_L1_IN 13 RF_IN GPS_ANTENNA CM6125 RF only




RFFE5_CLK 18

B-PD:nppukp DO DO

Configurable I/O Generic RF controller bit 35 RF front-end 5 interface clock

CM6125 RF only

RFFE5_DATA 19


Configurable I/O Generic RF controller bit 32 RF front-end 5 interface data Boot configuration control bit 12

CM6125 RF only

SM_GPIO_118 20



CM6125 RF only

SM_GPIO_87 21 B-PD:nppukp DI


CM6125 RF only

ANT_PRI 48 RF_IO Primary_Antenna CM6125 RF only


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Chapter 3. Electrical Characteristics

3.1. Absolute maximum ratings

Refer to the absolute rating conditions required for SOM design below.

Table 3-1. Absolute rating condition

Parameter Min Max Units

Input Power Voltage

USB_IN -0.3 16 V

VBAT 2.7 4.6 V

VPH_PWR -0.3 5.25 V

VBATT_SNS_P 2.7 5.25 V

ESD (electro-static discharge)

ESD-HBM model rating ±2000 V

ESD-CDM model rating ±500 V

NOTE: The ESD related parameters are only valid and available after the module is fully tested and approved in

the initial production stage.

3.2. Operating conditions

Refer to the operating conditions required for SOM design below.

Table 3-2. Operating condition

Parameters Min Typical Max Units

Input power voltage

USB_VBUS 3.6 - 10 V

VBAT 3.2 3.8 4.6 V

VBAT 3 A

VBATT_SNS_P 3.2 3.8 4.6 V

Thermal conditions

Operating temperature -20 25 70 °C

Storage temperature -40 - 70 °C

NOTE: The min and max temperature values for the device and storage are only valid and available after the

module is fully tested and approved in the initial production stage.

3.3. Output power

The SOM shall provide power supply for external devices, such as camera module, SD card, sensor, etc. Refer to the details below.

Table 3-3. Output power specification

Function Default voltage(V) Specific Range(V) Rated current(mA) Expected use

VREG_L20A_1P8_UIM2 1.8 1.65~2.95 150 UIM2

VREG_L14A_1P8 1.8 1.7~1.9 600 WCD_VDD_BUCK


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Function Default voltage(V) Specific Range(V) Rated current(mA) Expected use

VREG_L12A_1P8 1.8 1.7~1.9 300 Camera sensors (1.8 V), USB Redriver, MIPI_VDDIO (1.8V)

VREG_L9A_1P8 1.8 1.504~2.0 - VIO

VREG_L15A_3P104 3.128 2.93~3.23 150 Relevant USB circuity

VREG_L10A_1P8 1.8 1.7~1.89 150 USB2, USB3.1, UFS, VDDPX_11

VREG_L22A_2P96 2.96 2.95~3.3 600 MEM_SD_MMC_VDD

VREG_L5A_2P96 2.96 1.65~3.1 50 Power of pulled-up resistors of TF card

VREG_L19A_1P8_UIM1 1.8 1.65~2.95 150 UIM1

3.4. Digital-logic characteristics

The digital I/O's performance depends on its pad type, usage, and power supply voltage. The SOM IO voltage level is the same with that of VDDPX_3 (except the voltage for SD card and analog input/output interface). The design of I2C, USB, MIPI, and UART interfaces comply with the standards respectively.

3.4.1. Digital GPIO characteristics

Table 3-4. Digital GPIO characteristics

Parameter Description Min Max Units

VIH High-level input voltage, CMOS/Schmitt, 0.7 x VDDPX VDDPX+0.3 V

VIL Low-level input voltage, CMOS/Schmitt, -0.3 0.3 x VDDPX V

VOH High-level output voltage, CMOS VDDPX - 0.45 VDDPX V

VOL Low-level output voltage, CMOS 0.0 0.45 V

RPULL-UP Pull-up resistance 10 K 100 K Ω

RPULL-DOWN Pull-down resistance 10 K 100 K Ω

3.4.2. SD card digital I/O characteristics

The SD card is powered by P2 supplies (1.8V / 2.96V).

Table 3-5. SD card digital I/O characteristics

Parameter Description Min Typical Max Units

VIH High-level input voltage (1.8/2.95V) 1.27/0.7 x VDDPX2 - 2/VDDPX2 + 0.3 V

VIL Low-level input voltage -0.3/-0.3 - 0.58/0.25 x VDDPX2 V

RPULL-UP Pull-up resistance 10 K - 100K Ω

RPULL-DOWN Pull-down resistance 10 K - 100K Ω

VOH High-level output voltage 1.4/0.75 x VDDPX2 - -/VDDPX2 V

VOL Low-level output voltage -/0 - 0.45/0.125 x VDDPX2 V

3.5. MIPI

Table 3-6. Supported MIPI_CSI standards and exceptions

Applicable standard Feature exceptions

MIPI Alliance Specification for DPHY v1.2 Supports only unidirectional data receiving

MIPI Alliance Specification for CPHY v1.0 None

Table 3-7. Supported MIPI_DSI standards and exceptions


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MIPI Alliance Specification for Display Serial Interface None

MIPI Alliance Specification for D-PHY v1.2 None

3.6. USB interface

Table 3-8. Supported USB standards and exceptions

Applicable standard Feature exceptions Device variations

Universal Serial Bus Specification, Revision 3.1

(August 11, 2014 or later). Feature exceptions SS Gen2. None

Universal Serial Bus Specification, Revision 2.0 (April

27, 2000 or later) Low speed is not supported in device mode Operating voltages, system clock, and VBUS

On-The-Go Supplement to the USB 2.0 Specification

(June 24, 2003, Revision 1.0 A or later) Supports the host mode aspect of OTG only None

3.7. Display port

Table 3-9. Supported DP standards and exceptions


VESA DisplayPort V1.4 None

3.8. SLIMbus

Table 3-10. Supported SLIMbus standards and exceptions


Serial Low-power Interchip Media Bus, Version 1.01.01

No support of the CHANGE_CONTENT() message by any of the devices in the component. Only the manager is given the ability to manage data channels in the system

No support for the elemental access mode for information and value elements

No support for the following transport protocols Asynchronous half-duplex Extended asynchronous half-duplex

No support for the locked transport Protocol No support of partial mask in CHANGE_VALUE message

The maximum clock output slew rate might be greater than 20% × VDD [V/ns] for the 15 pF load condition

3.9. SD Interface

Table 3-11. Supported SDIO standards and exceptions


Multi-Media Card Host Specification, version 5.1 None

Secure Digital: Physical Layer Specification version 3.0 None

SDIO Card Specification version 3.0 None

3.10. I2S

Table 3-12. Supported I2S standards and exceptions



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Philips I²S Bus Specifications revised June 5, 1996 None Refer to I2S Timing to the figure below. When an external SCK clock is

used, a duty cycle (values between 45% to 55%) is required.

Figure 3-1. I2S Timing Diagram

Table 3-13. I2S timing characteristics

Parameter Comments Min Typ. Max Unit

Using internal SCK

Frequency – – – 24.576 MHz

T Clock period – 40.69 – – ns

t(HC) Clock high – 0.45 × T – 0.55 × T ns

t(LC) Clock low – 0.45 × T – 0.55 × T ns

t(sr) SD and WS input setup time – 8.14 – – ns

t(hr) SD and WS input hold time – 0 – – ns

t(dtr) SD and WS output delay – – – 6.10 ns

t(htr) SD and WS output hold time delay – 0 – – ns

Using external SCK

Frequency – – – 24.576 MHz

T Clock period – 40.69 – – ns

t(HC) Clock high – 0.45 × T – 0.55 × T ns

t(LC) Clock low – 0.45 × T – 0.55 × T ns

t(sr) SD and WS input setup time – 8.14 – – ns

t(hr) SD and WS input hold time – 0 – – ns

t(dtr) SD and WS output delay – – – 6.10 ns


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3.11. Digital microphone PDM interface

Figure 3-2. DMIC Timing Diagram

Table 3-14. Digital microphone parameters


T DMIC clock period 163 – 1666 ns

t(LSU) Data left setup time to clock falling edge 5 – – ns

t(LH) Data left hold time to clock falling edge 0 – – ns

T(RSU) Data right setup time to clock rising edge 5 – – ns

t(RH) Data right hold time to clock falling edge 0 – – ns

3.12. I2C



I2C Specification, version 3.0 HS mode, slave mode, multi-master mode, and 10-bit addressing feature are not supported.

3.13. I3C



I3C Specification, version 1.0 None

3.14. SPI

The QCM6125 supports SPI as a master only. Only six out of 10 QUP ports can be configured as a SPI master.

Figure 3-3. SPI Timing Diagram


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Table 3-17. SPI parameters


T(SPI clock period) 50MHz max. 20 – – ns

t(ch) Clock high 9 – – ns

t(cl) Clock low 9 – – ns

t(mov) Master output valid -5 – 5 ns

t(mis) Master input setup 5 – – ns

3.15. Fuel gauge

Qualcomm battery gauge is a hybrid of voltage and current based state of charge. The core of PMI632 Qualcomm battery gauge hardware consists of accumulator, which periodically samples, accumulates, and saves Vbatt and Ibatt values into PMIC register to read and process SoC (System on Chip).

The same hardware is reused for an online battery ESR estimation, where V and I readings are run and saved to record pre-ESR and ESR pulse Vbatt and Ibatt values. The software reads the registers for ESR estimation.

3.16. LEDs

3.16.1. RGB LED

The RGB LED can realize independent brightness control of red, green, and blue channels.

Table 3-18. RGB LED parameters


Isource RGB output per channel 12 mA

FPWM PWM frequency 0.0025 4.7 kHz

3.16.2. Flash drive LED

The SOM supports a high-current driver that can work in various concurrency scenarios and get along with different LED configurations

Table 3-19. Flash drive LED parameters


VDD_FLASH Flash driver is enabled and active and charger in boost mode 3.425 10.8 V

Maximum current per LED LED1/LED2 1.5 A

Current resolution programmable options LED1/LED2 5 12.5 12.5 mA

Standby current Flash_en = 1, LED_STROBE1/2 = 0, TA = -35ºC to 85ºC VDD_FLASH = 3 V to 4.8 V

600 1300 uA

3.17. PWM

SOM has 2 PWM output channels: PMI_GPIO_06 is for WLED brightness control (optional), and PM_GPIO_08 is for LED control (optional).


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3.18. Power consumption

TBD

3.19. Thermal

The tables below record thermal test data. It is highly recommended to take the SOM thermal test result into consideration when design products based on C(M)6125 SOM.

Table 3-20. Thermal test condition

Thermal Test Condition

1 Test case TBD

2 HW Version TBD

3 Test points TBD

4 Ambient temperature TBD

Table 3-21. Thermal test result

Thermal Test Result

Test Location Temperature (Max) △T

1 Environment Temperature 25

3.20. RF performance

TBD.


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Appendix 1. Notices

Thundercomm may have patents or pending patent programs covering subject matter described in this document. The furnishing of this document does not give you any license to these patents. You can send license inquiries to [email protected].

THUNDERCOMM PROVIDES THIS PUBLICATION "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Some jurisdictions do not allow disclaimer of express or implied warranties in certain transactions; therefore, this statement may not apply to you.

Changes are made periodically to the information herein; these changes will be incorporated in new editions of the publication. To provide better service, Thundercomm reserves the right to improve and/or modify the products and software programs described in the manuals, and the content of the manual, at any time without additional notice.

The software interface and function and hardware configuration described in the manuals included with your development board or system on module might not match exactly the actual configuration of that you have purchased. For the configuration of the product, refer to the related contract (if any) or product packing list, or consult the distributor for the product sales. Thundercomm may use or distribute any of the information you supply in any way it believes appropriate without incurring any obligation to you.

The products described in this document are not intended for use in implantation or other life support applications where malfunction may result in injury or death to persons. The information contained in this document does not affect or change Thundercomm product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of Thundercomm or third parties. All information contained in this document was obtained in specific environments and is presented as an illustration. The result obtained in other operating environments may vary.

The information of this document should not be as any invitation for offer or any advice to the visitors. Please consult the professional comments from the sales consultant prior to do any actions of invest or purchase.

Thundercomm may use or distribute any of the information you supply in any way it believes appropriate without incurring any obligation to you.

Any references in this publication to non-Thundercomm Web sites are provided for convenience only and do not in any manner serve as an endorsement of those Web sites. The materials at those Web sites are not part of the materials for this Thundercomm product, and use of those Web sites is at your own risk. Thundercomm shall not be responsible for the content of the third party.

Any performance data contained herein was determined in a controlled environment. Therefore, the result obtained in other operating environments may vary significantly. Some measurements may have been made on development-level systems and there is no guarantee that these measurements will be the same on generally available systems. Furthermore, some measurements may have been estimated through extrapolation. Actual results may vary. Users of this document should verify the applicable data for their specific environment.

This document is copyrighted by Thundercomm and the property right of the date mentioned in this document, including but not limited trademarks, patents, copyrights, trade name etc. are not covered by any open-source license. Thundercomm may update this document at any time without notice.

Anyone doesn’t have the right to amend, reprint, republication, reproduce, transmit, distribute or any other way to use this document in business or public purpose without the prior written consent by Thundercomm.

E-mail messages sent to Thundercomm via the Internet are not guaranteed to be completely secure. Thundercomm shall not be liable for any loss incurred by the surfer when transmitting any information over the Internet or for any loss incurred by Thundercomm when sending any information over the Internet at your


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request.

Thundercomm has all rights under other relevant exemptions provided by laws and regulations, and Thundercomm's failure to claim or delay in claiming such rights shall not be deemed to be a waiver of such rights by Thundercomm.

Thundercomm reserves the right of final interpretation of this document.


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Appendix 2. Trademarks

Thundercomm, Thundercomm Turbox, TURBOX, Thundersoft turbox are trademarks of Thundercomm Corporation or its associate companies in China and/or other countries. Intel, Intel SpeedStep, Optane, and Thunderbolt are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Microsoft, Windows, Direct3D, BitLocker, and Cortana are trademarks of the Microsoft group of companies. Mini DisplayPort (mDP), DisplayPort, and VESA are trademarks of the Video Electronics Standards Association. The terms HDMI and HDMI High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries. Wi-Fi, Wi-Fi Alliance, WiGig, and Miracast are registered trademarks of Wi-Fi Alliance. USB-C is a registered trademark of USB Implementers Forum. All other trademarks are the property of their respective owners.

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