FN6412Rev 1.00

Apr 10, 2007

ISL6423BSingle Output LNB Supply and Control Voltage Regulator with I2C Interface for Advanced Satellite Set-Top Box Designs

DATASHEET

The ISL6423B is a highly integrated voltage regulator and interface IC, specifically designed for supplying power and control signals from advanced satellite set-top box (STB) modules to the low noise blocks (LNBs) of singe antenna ports. The device consists of a current-mode boost PWM and a low-noise linear regulator along with the circuitry required for 22kHz tone generation, modulation and I2C device interface. The device makes the total LNB supply design simple, efficient and compact with low external component count.

The current-mode boost converters provides the linear regulator with input voltage that is set to the final output voltages, plus typically 0.8V to insure minimum power dissipation across each linear regulator. This maintains constant voltage drop across the linear pass element while permitting adequate voltage range for tone injection.

The final regulated output voltage is available at output terminals to support the operation of an antenna port for single tuners. The outputs for each PWM can be controlled in two ways, full control from I2C using the VTOP and VBOT bits or set the I2C to the lower range i.e., 13V/14V, and switch to higher range i.e., 18V/19V, with the SELVTOP pin. All the functions on this IC are controlled via the I2C bus by writing 8 bits words onto the System Registers (SR). The same register can be read back, and five I2C bits will report the diagnostic status. Separate enable command sent on the I2C bus provides for standby mode control for the PWM and linear combination, disabling the output and forcing a shutdown mode. The output channel is capable of providing 750mA of continuous current. The overcurrent limit can be digitally programmed to four levels.

The External modulation input EXTM can accept a modulated Diseqc command and transfer it symmetrically to the output. Alternatively the EXTM pin can be used to modulate the continuos internal tone.

The FLT pin serves as an interrupt for the processor when any condition turns OFF the LNB controller (Over Temperature, Overcurrent, Disabled). The nature of the Disable can be read of the I2C registers.

Features Single Chip Power solution

- Operation for 1-Tuner/1-Dish Applications- Integrated DC/DC Converter and I2C Interface

Switch-Mode Power Converter for Lowest Dissipation- Boost PWMs with >92% Efficiency- Selectable 13.3V or 18.3V Outputs- Digital Cable Length Compensation (1V)- I2C and Pin Controllable Output

Output Back Bias Capability of 28V

I2C Compatible Interface for Remote Device Control

Registered Slave Address 0001 00XX

2.5V, 3.3V, 5V Logic Compatible

External Pin to Toggle Between V and H Polarization

Built-In Tone Oscillator Factory Trimmed to 22kHz- Facilitates DiSEqC (EUTELSAT) Encoding- External Modulation Input

Internal Over-Temperature Protection and Diagnostics

Internal OV, UV, Overload and Overtemp Flags(Visible on I2C)

FLT signal

LNB Short-Circuit Protection and Diagnostics

QFN, EPTSSOP Packages

Pb-Free Available (RoHS Compliant)

Applications LNB Power Supply and Control for Satellite Set-Top Box

Ordering InformationPART

NUMBER*PART

MARKINGTEMP.

(C) PACKAGEPKG.

DWG. #

ISL6423BERZ(Note)

6423BERZ -20 to +85 24 Ld 4x4 QFN(Pb-free)

L24.4x4D

ISL6423BEVEZ(Note)

ISL6423BEVEZ -20 to +85 28 Ld EPTSSOP(Pb-free)

M28.173B

NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% mattetin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.Add -T suffix for tape and reel.

FN6412 Rev 1.00 Page 1 of 16Apr 10, 2007

ISL6423B

PinoutsISL6423B

(28 LD EPTSSOP)TOP VIEW

ISL6423B(24 LD QFN)TOP VIEW

VCC

NC

FLTSGND

SGND

TCAP

ADDR0

ADDR1

BYPASS

PGND

GATE

VSW

NC

CS

CPSWIN

CPVOUT

EXTM

SDA

SCL

TDIN

NC

NC

AGND

SELVTOP

TXT

CPSWOUT

TDOUT

VO

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

SGN

D

FLT

VCC

CPS

WIN

CPS

WO

UT

CPV

OU

T

GAT

E

VSW

CS

TXT

SELV

TOP

AG

ND

SGND

TCAP

ADDR0

ADDR1

BYPASS

PGND

EXTM

SDA

SCL

TDOUT

TDIN

VO

1

2

3

4

5

6

18

17

16

15

14

13

24 23 22 21 20 19

7 8 9 10 11 12

FN6412 Rev 1.00 Page 2 of 16Apr 10, 2007

FN6412

Rev 1.00

Page 3 of 16Apr 10, 2007

ISL6423B

3

19

CPVOUT

CHARGE PUMP

THERMALSHUTDOWNOTF

DCL

DR0

AD

DR

0

OU

VF

OUVF

21

CPS

WIN

4

AD

DR

1

ADDR1

FLT

23

TTH

Block Diagram

NOTE:1. Pinouts shown are for the QFN package.

COUNTER OVERCURRENTPROTECTIONLOGIC SCHEME 1

OLF/BCF

DCL

OC1

CLK1

PWMLOGICQ

SGATE

PGND

CS

CSAMP

ILIM1

SLOPECOMPENSATION

18

7

9

16

2

13

22

VO

VCC

SGND

BYP

ASS

ENT1

EXTM

OLF/BCF

SDA

ISELL&H

EN

VTOP VBOT

SCL AD

ENT

OSC.CLK1

I2CINTERFACE

BAND GAPREF VOLTAGE

ADJ1

REFVOLTAGE

TONEINJ

CKT

INTTONE

TCA

P

DIV &WAVE SHAPING

+-

EN1/EN2SOFT-STARTINT 5V

ON CHIPLINEAR

UVLOPOR

SOFT-START

1

8 VSW

+ -

BGV

5

VREF1

+-

SELV

TOP

EXT TONE CKT

MSE

L1

14

15

TDIN

TDOUT

TONEDECODER

SCL

6

17

SDA

20

CPS

WO

UT

11

AGND12

TXT

TTH

10

TXT

24 SGND

FN6412

Rev 1.00

Page 4 of 16Apr 10, 2007

ISL6423B

3k

M6NDS356AP

L4 220H1 2

C15 0.22F

R7 15

EXTM

FLT BAR

TDOUT

RTN

SDA

SCL

SELVTOP

TXT

VLNB

00

00

VIN

RTN

0

D81.5KE24

4k

quired logic level.

Q42N2222A

Typical Application Schematic QFN

R13 4.7k

R2247k

R210

C1610n

Q2TPC6002

1 2 3456

D5

CMS06

D6CMS06

R80.1

R9470

R1018

0D7 CMS06

C1810F

C1910F

C2010F

0

0

0 0

L515H

1

2

C21100pF

0

0

0

C2256F

C2356F

0

C241F

0

L6 4.7H1 2

C25 47n

C26 1F

R11 1

R12 1

C27 0.22FC280.1F

U2ISL6423ER

VSW

8C

S9

SELV

TOP

11TX

T10

AG

ND

12C

PVO

UT

19

EXTM 18

SCL16

TDIN14TDOUT15ADDR0

3

VO 13

CPS

WO

UT

20

ADDR14

BYPASS5

VCC

22C

PSW

IN21

SGND1TCAP2

FLT

23

PGND6

24

SDA 17

GAT

E7

0

C291n

R24.7

NOTE : SDA and SCL require pull up to the re

SGN

D

ISL6423B

Absolute Maximum Ratings Thermal InformationSupply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0V to 18.0VLogic Input Voltage Range

(SDA, SCL, ENT, DSQIN 1 and 2, SEL18V 1 and 2) . -0.5V to 7V

Thermal Resistance (Typical, Notes 2, 3) JA (C/W) JC (C/W)QFN Package (Notes 2, 3) . . . . . . . . . . 38 4.5EPTSSOP Package (Notes 2, 3) . . . . . 35 2.5

Maximum Junction Temperature (Note 4) . . . . . . . . . . . . . . . +150CMaximum Storage Temperature Range . . . . . . . . . . -40C to +150COperating Temperature Range . . . . . . . . . . . . . . . . . -20C to +85C

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of thedevice at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:2. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See

Tech Brief TB379.

3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.4. +150C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150C junction may

trigger the shutdown of the device even before +150C, since this number is specified as typical.

Electrical Specifications VCC = 12V, TA = -20C to +85C, unless otherwise noted. Typical values are at TA = +25C. EN = H, VTOP VBOT = L, ENT = L, DCL = L, IOUT = 12mA, unless otherwise noted. See software description section for I2C access to the system.

PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Operating Supply Voltage Range 8 12 14 V

Standby Supply Current EN = L -