DATASHEET AEM30940 - E-peas · the shutdown of the AEM, the status pin STATUS[1] alerts the user...

DATASHEET AEM30940DATASHEET AEM30940DATASHEET AEM30940

Highly-efficient, regulated dual-output, ambient energy manager

for AC or DC sources with optional primary battery

Features

Ultra-low-power start-up:- Cold start from 380mV input voltage and 3 µW input

power (typical)- RF input power from -18.5 dBm up to 10 dBm (typical)

Ultra-low-power boost regulator:- Open-circuit voltage sensing for MPPT every 0.33 s- Configurable MPPT with 2-pin programming- Selectable Voc ratios of 50, 65 or 80 %- Input voltage operation range from 50 mV to 5 V- MPPT voltage operation range from 50 mV to 5 V- Constant impedance matching (ZMPPT)

Integrated 1.2/1.8 V LDO regulator:- Up to 20 mA load current- Power gated dynamically by external control- Selectable output voltage

Integrated 1.8 V-4.1 V LDO regulator:- Up to 80 mA load current with 300 mV drop-out- Power gated dynamically by external control- Selectable or adjustable output voltage

Flexible energy storage management:- Selectable overcharge and overdischarge protection for any

type of rechargeable battery or (super)capacitor- Fast supercapacitor charging- Warns the load when battery is running low- Warns when output voltage regulators are available

Smallest footprint, smallest BOM:- Only seven passive external components

Optional primary battery:- Automatically switches to the primary battery when the

secondary battery is exhausted

Integrated balun for dual-cell supercapacitor

Applications

• Piezo harvesting • Home automation

• Micro turbine harvesting • Transportation

• RF harvesting • Smart agriculture

• Industrial monitoring

AEM30940QFN28 5x5 mm2

SRC

ZMPP

BUFSRC

SWBOOST

BOOST

SWBUCK

BUCK

ENHV

ENLV

CFG[2

:0]

SELM

PP[1

:0]

GN

D

PRIM

FB PRIM U

FB PRIM D

BATT

BAL

STATUS[2 : 0]

LVOUT

HVOUT

SET

OVCH

SET

CH

RD

Y

SET

OVD

IS

FB

HV

LBUCK

CBUCK

CSRC

LBOOST

CBOOST

Powerreceivingantenna

Matchingnetwork

Rectifier

RZMPP(optional)

Micro-controller

CLV

Radiotransceiver

CHV

Li-ionbattery

Primarybattery

(optional)

R4-R3-R2-R1 (optional)

BOOST HVOUT

R6-R5 (optional)

R7 (optional)

R8 (optional)

BUCK

Description

The AEM30940 is an integrated energy management circuitthat extracts DC power from a piezo generator, a micro turbinegenerator or any high frequency RF input to simultaneouslystore energy in a rechargeable element and supply the systemwith two independent regulated voltages. The AEM30940 al-lows to extend battery lifetime and ultimately eliminates theprimary energy storage element in a large range of wirelessapplications such as industrial monitoring, home automation,transportation and smart agriculture.The AEM30940 harvests the available input current up to110 mA. It integrates an ultra-low power boost converter tocharge a storage element, such as a Li-ion battery, a thin filmbattery, a supercapacitor or a conventional capacitor. Theboost converter operates with input voltages in a range from50 mV to 5 V. With its unique cold-start circuit, it can startoperating with empty storage elements at an input voltage aslow as 380mV and an input power of just 3 µW.The low-voltage supply typically drives a microcontroller at1.2 V or 1.8 V. The high-voltage supply typically drives a ra-dio transceiver at a configurable voltage between 1.8 V and4.1 V. Both are driven by highly-efficient LDO (Low Drop-Out) regulators for low noise and high stability.Configuration pins determine various operating modes by set-ting predefined conditions for the energy storage element (over-charge or overdischarge voltages), and by selecting the voltageof the high-voltage supply and the low-voltage supply. More-over, special modes can be obtained at the expense of a fewconfiguration resistors.The chip integrates all the active elements for powering a typ-ical wireless sensor. Five capacitors and two inductors are re-quired, available in the small 0402 and 0603 size, respectively.With only seven external components, integration is maxi-mum, footprint and BOM are minimum, optimizing the time-to-market and the costs of WSN designs.

Device information

Part number Package Body size

10AEM30940C0000 QFN 28-pin 5mm x 5mm

1DS AEM30940 REV1.1 Copyright c© 2018 e-peas SA 1DS AEM30940 REV1.1 Copyright c© 2018 e-peas SA 1DS AEM30940 REV1.1 Copyright c© 2018 e-peas SA


Contents

1 Introduction 3

2 Absolute Maximum Ratings 5

3 Thermal Resistance 5

4 Typical Electrical Characteristics at 25 C 5

5 Recommended Operation Conditions 6

6 Functional Block Diagram 7

7 Theory of Operation 87.1 Deep sleep & Wake up modes . . . . . . . . . . . 87.2 Normal mode . . . . . . . . . . . . . . . . . . . . 97.3 Overvoltage mode . . . . . . . . . . . . . . . . . 97.4 Primary mode . . . . . . . . . . . . . . . . . . . 107.5 Shutdown mode . . . . . . . . . . . . . . . . . . 107.6 Maximum power point tracking . . . . . . . . . . 107.7 Balun for dual-cell supercapacitor . . . . . . . . 10

8 System Configuration 118.1 Battery and LDOs configuration . . . . . . . . . . 118.2 MPPT configuration . . . . . . . . . . . . . . . . 128.3 Primary battery configuration . . . . . . . . . . . 128.4 ZMPPT configuration . . . . . . . . . . . . . . . 128.5 No-battery configuration . . . . . . . . . . . . . . 128.6 Storage element information . . . . . . . . . . . . 12

9 Typical Application Circuits 139.1 Example circuit 1 . . . . . . . . . . . . . . . . . . 139.2 Example circuit 2 . . . . . . . . . . . . . . . . . . 14

10 Performance Data 1810.1 BOOST conversion efficiency . . . . . . . . . . . 1810.2 Quiescent current . . . . . . . . . . . . . . . . . 1810.3 High-voltage LDO regulation . . . . . . . . . . . 1910.4 Low-voltage LDO regulation . . . . . . . . . . . . 1910.5 High-voltage LDO efficiency . . . . . . . . . . . . 2010.6 Low-voltage LDO efficiency . . . . . . . . . . . . 2010.7 RF path efficiency . . . . . . . . . . . . . . . . . 2110.8 Overall efficiency . . . . . . . . . . . . . . . . . . 22

11 Schematic 23

12 Layout 24

13 Package Information 2513.1 Plastic quad flatpack no-lead (QFN28 5x5mm) . 2513.2 Board layout . . . . . . . . . . . . . . . . . . . . 25

List of Figures

1 Simplified schematic view . . . . . . . . . . . . . . 32 Pinout diagram QFN28 . . . . . . . . . . . . . . . 43 Functional block diagram . . . . . . . . . . . . . . 74 Simplified schematic view of the AEM30940 . . . . 85 Diagram of the AEM30940 modes . . . . . . . . . . 86 Custom configuration resistors . . . . . . . . . . . . 117 Typical application circuit 1 . . . . . . . . . . . . . 138 Typical application circuit 2 . . . . . . . . . . . . . 149 Cold start with a capacitor connected to BATT . . . 1510 Cold start with a battery connected to BATT . . . . 1511 Overvoltage mode . . . . . . . . . . . . . . . . . . 1612 Shutdown mode (without primary battery) . . . . . 1613 Switch to primary battery if the battery is overdis-

charged . . . . . . . . . . . . . . . . . . . . . . . . 1714 Boost efficiency for Isrc at 100 µA, 1 mA, 10 mA

and 100 mA . . . . . . . . . . . . . . . . . . . . . 1815 Quiescent current with LDOs on and off . . . . . . 1816 HVOUT at 3.3 V and 2.5 V . . . . . . . . . . . . . 1917 LVOUT at 1.2 V and 1.8 V . . . . . . . . . . . . . 1918 HVOUT efficiency at 1.8 V, 2.5 V and 3.3 V . . . . 2019 Efficiency of BUCK cascaded with LVOUT at 1.2 V

and 1.8 V . . . . . . . . . . . . . . . . . . . . . . 2020 Efficiency for 863-868 MHz band . . . . . . . . . . 2121 Efficiency for 915-921 MHz band . . . . . . . . . . 2122 Efficiency for 925-960 MHz band . . . . . . . . . . 2123 Efficiency for 1.805-1.880 GHz band . . . . . . . . . 2124 Efficiency for 2.11-2.17 GHz band . . . . . . . . . . 2125 Efficiency for 2.4-2.5 GHz band . . . . . . . . . . . 2126 Overall efficiency (RF path and boost converter) with

VBOOST = 4.5V . . . . . . . . . . . . . . . . . . 2227 Schematic example . . . . . . . . . . . . . . . . . . 2328 Layout example for the AEM30940 and its passive

components . . . . . . . . . . . . . . . . . . . . . . 2429 QFN28 5x5mm . . . . . . . . . . . . . . . . . . . . 2530 Board layout . . . . . . . . . . . . . . . . . . . . . 25

List of Tables

1 Pins description . . . . . . . . . . . . . . . . . . . . 42 Absolute maximum ratings . . . . . . . . . . . . . . 53 Thermal data . . . . . . . . . . . . . . . . . . . . . 54 Electrical characteristics . . . . . . . . . . . . . . . 55 Recommended operating conditions . . . . . . . . . 66 Minimum input power for the cold start (typical).

Results obtained with the matching network and rec-tifier designed by e-peas . . . . . . . . . . . . . . . 8

7 LDOs configurations . . . . . . . . . . . . . . . . . 98 Usage of CFG[2:0] . . . . . . . . . . . . . . . . . . 119 Usage of SELMPP[1:0] . . . . . . . . . . . . . . . . 1210 BOM example for AEM30940 and its required passive

components . . . . . . . . . . . . . . . . . . . . . . 23



AEM30940Powerreceivingantenna

Matchingnetwork

Rectifier

Primarybattery

(optional)

PRIM

5 V MAX

Storage element

• Li-ion cell• Solid state battery• NiMH battery• Supercapacitor• Dual-cell supercapacitor• Capacitor• LiFePO4 battery• ...

BATT

4.5V MAX

Your circuit

HVOUT4.2V-1.8V80mA

LVOUT1.8V\1.2V20mA

Figure 1: Simplified schematic view

1 Introduction

The AEM30940 is a full-featured energy efficient power man-agement circuit able to charge a storage element (battery orsupercapacitor, connected to BATT) from an energy source(connected to SRC) as well as to supply loads at different op-erating voltages through two power supplying LDO regulators(LVOUT and HVOUT).The heart of the AEM30940 is a cascade of two regulatedswitching converters, namely the boost converter and thebuck converter with high-power conversion efficiencies (SeePage 18).At first start-up, as soon as a required cold-start voltage of380 mV and a scant amount of power of just 3 µW availablefrom the harvested energy source, the AEM coldstarts. Afterthe cold start, the AEM can extract the power available fromthe source as long as the input voltage is comprised between50 mV and 5 V.Through three configuration pins (CFG[2:0]), the user can se-lect a specific operating mode from a range of seven modesthat cover most application requirements without any dedi-cated external component. Those operating modes define theLDO output voltages and the protection levels of the storageelement. Note that a custom mode allows the user to de-fine his own storage element protection levels and the outputvoltage of the high-voltage LDO (See Page 11).

The Maximum Power Point (MPP) ratio can be configuredusing two configuration pins (SELMPP[1:0]) (See Page 12).

Two logic control pins are provided (ENLV and ENHV) to dy-namically activate or deactivate the LDO regulators that sup-ply the low- and high-voltage load, respectively. The statuspin STATUS[0] alerts the user that the LDOs are operationaland can be enabled. This signal can also be used to enable anoptional external regulator.

If the battery voltage gets depleted, the LDOs are power gatedand the controller is no longer supplied by the storage elementto protect it from further discharge. Around 600 ms beforethe shutdown of the AEM, the status pin STATUS[1] alertsthe user for a clean shutdown of the system.

However, if the storage element gets depleted and an optionalprimary battery is connected on PRIM, the chip automaticallyuses it as a source to recharge the storage element beforeswitching back to the ambient source. This guarantees con-tinuous operation even under the most adverse conditions (SeePage 10). STATUS[1] is asserted when the primary battery isproviding power.

The status of the MPP controller is reported with one dedi-cated status pin (STATUS[2]). The status pin is asserted whena MPP calculation is being performed.



QFN28Top view

1

2

3

4

5

6

7

8 9 10 11 12 13 14

15

16

17

18

19

20

21

22232425262728

BOOST

SWBUCK

BUCK

CFG[2]

CFG[1]

CFG[0]

SELMPP[1]

SELM

PP[0

]

FB

PRIM

D

FB

PRIM

U

LVO

UT

EN

HV

FB

HV

HVO

UT

BAL

BATT

PRIM

ENLV

STATUS[2]

STATUS[1]

STATUS[0]

SET

OVCH

SET

CH

RD

Y

SET

OVD

IS

ZM

PP

SRC

BU

FSRC

SW

BO

OST

Figure 2: Pinout diagram QFN28

NAME PIN NUMBER FUNCTION

Power pins

BOOST 1 Output of the boost converter.

SWBUCK 2 Switching node of the buck converter.

BUCK 3 Output of the buck converter.

LVOUT 11 Output of the low voltage LDO regulator.

HVOUT 14 Output of the high voltage LDO regulator.

BAL 15Connection to mid-point of a dual-cell supercapacitor (optional).Must be connected to GND if not used.

BATT 16Connection to the energy storage element, battery or capacitor.Cannot be left floating.

PRIM 17Connection to the primary battery (optional).Must be connected to GND if not used.

SRC 26 Connection to the harvested energy source.

BUFSRC 27 Connection to an external capacitor buffering the boost converter input.

SWBOOST 28 Switching node of the boost converter.

Configuration pinsCFG[2] 4 Used for the configuration of the threshold voltages for the

energy storage elementand the output voltage of the LDOs.

See Page 11

CFG[1] 5CFG[0] 6SELMPP[1] 7

Used for the configuration of the MPP ratio.SELMPP[0] 8FB PRIM D 9 Used for the configuration of the primary battery (optional).

Must be connected to GND if not used.FB PRIM U 10

FB HV 13 Used the configuration of the high-voltage LDO in the cus-tom mode (optional). Must be left floating if not used.

SET OVCH 22 Used for the configuration of the threshold voltages forthe energy storage element in the custom mode (optional).Must be left floating if not used.

SET CHRDY 23SET OVDIS 24

ZMPPT 25Used for the configuration of the ZMPPT (optional).Must be left floating if not used.

Control pinsENHV 12 Enabling pin for the high-voltage LDO.

See Page 9ENLV 18 Enabling pin for the low-voltage LDO.

Status pinsSTATUS[2] 19 Logic output. Asserted when the AEM performs a MPP evaluation.

SeePages 8-10

STATUS[1] 20 Logic output. Asserted if the battery voltage falls below Vovdis or

if the AEM is taking energy from the primary battery.

STATUS[0] 21 Logic output. Asserted when the LDOs can be enabled.

Other pinsGND Exposed Pad Ground connection, should be solidly tied to the PCB ground plane.

Table 1: Pins description



2 Absolute Maximum Ratings

Parameter RatingVsrc 5.5VOperating junction temperature -40 C to +125 CStorage temperature -65 C to +150 C

Table 2: Absolute maximum ratings

3 Thermal Resistance

Package θJA θJC UnitQFN28 38.3 2.183 C/W

Table 3: Thermal data

ESD CAUTION

ESD (ELECTROSTATIC DISCHARGE) SENSITIVE DEVICEThese devices have limited built-in ESD protection and damage may thus occur on devicessubjected to high-energy ESD. Therefore, proper ESD precautions should be taken to avoidperformance degradation or loss of functionality.

4 Typical Electrical Characteristics at 25 CSymbol Parameter Conditions Min Typ Max UnitPower conversion

PsrcCS Source power required for cold start. During cold start 3 µW

Vsrc Input voltage of the energy source.During cold start 0.38 5

VAfter cold start 0.05 5

Vboost Output of the boost converter. During normal operation 2.2 4.5V

Vbuck Output of the buck converter. During normal operation 2 2.2 2.5Storage element

Vbatt Voltage on the storage element.Rechargeable battery 2.2 4.5 VCapacitor 0 4.5 V

TcritTime before shutdown after STA-TUS[1] has been asserted.

400 600 800 ms

Vprim Voltage on the primary battery. 0.6 5 V

Vfb prim uFeedback for the minimal voltagelevel on the primary battery.

0.15 1.1 V

VovchMaximum voltage accepted on thestorage element before disabling theboost converter.

see Table 8 2.3 4.5 V

VchrdyMinimum voltage required on thestorage element before enabling theLDOs after a cold start.

see Table 8 2.25 4.45 V

Vovdis

Minimum voltage accepted on thestorage element before switching toprimary battery or entering into ashutdown.


Low-voltage LDO regulator

VlvOutput voltage of the low-voltageLDO.


IlvLoad current from the low-voltageLDO.

0 20 mA

High-voltage LDO regulator

VhvOutput voltage of the high-voltageLDO.

see Table 8 1.8 Vbatt - 0.3 V V

IhvLoad current from the high-voltageLDO.

0 80 mA

Logic output pins

STATUS[2:0] Logic output levels on the statuspins.

Logic high (VOH) 1.98 Vbatt VLogic low (VOL) -0.1 0.1 V

Table 4: Electrical characteristics



5 Recommended Operation Conditions

Symbol Parameter Min Typ Max UnitExternal components

CSRC Capacitor decoupling the input source. 8 10 22 µF

CBOOST Capacitor of the boost converter. 10 22 25 µF

LBOOST Inductor of the boost converter. 4 10 25 µH

CBUCK Capacitor of the buck converter. 8 10 22 µF

LBUCK Inductor of the buck converter. 4 10 25 µH

CLV Capacitor decoupling the low-voltage LDO regulator. 8 10 14 µF

CHV Capacitor decoupling the high-voltage LDO regulator. 8 10 14 µF

CBATTOptional - Capacitor on BATT if no storage elementis connected (see Page 12).

150 µF

RTOptional - Resistor for setting threshold voltage of thebattery in custom mode.Equal to R1 + R2 + R3 + R4 (see Page 11).

1 10 100 MΩ

RVOptional - Resistor for setting the output voltage ofthe high-voltage LDO in custom mode.Equal to R5 + R6 (see Page 11)

1 10 40 MΩ

RZMPPOptional - Resistor for the ZMPPT configuration(see Page 12).

10 1M Ω

RPOptional - Resistor to be used with a primary battery.Equal to R7 + R8 (see Page 12).

100 500 kΩ

Logic input pins

ENHV Enabling pin for the high-voltageLDO1.

Logic high (VOH) 1.75 Vbuck VbuckV

Logic low (VOL) -0.01 0 0.01

ENLV Enabling pin for the low-voltageLDO2.

Logic high (VOH) 1.75 Vbuck VboostV

Logic low (VOL) -0.01 0 0.01

SELMPP[1:0]Configuration pins forthe MPP evaluation (see Table 9).

Logic high (VOH) Connect to BUCK

Logic low (VOL) Connect to GND

CFG[2:0]Configuration pins forthe storage element (see Table 8).

Logic high (VOH) Connect to BUCK


STONBATT Configuration pin to select the en-ergy source during the cold start.

Logic high (VOH) Connect to BATT


Table 5: Recommended operating conditions

Note 1: ENHV can be dynamically driven by a logic signal from the LV domain. For a static usage, connect to BUCK (High)or GND (Low).Note 2: ENLV can be dynamically driven by a logic signal from the HV domain. For a static usage, connect to BUCK orBOOST (High) or GND (Low).



6 Functional Block Diagram

M1

M9

M2

M5

M4

M8

M6M3

M7

Cold Start

Boost

control

Buck

control

LLDO

control

HLDO

control

MPP

control

Finite state machine

Primary

control

Battery

control

Balance

control

State

monitor

Voltage

referenceVboost


Matchingnetwork

Rectifier

Supercapacitor

Vbatt

Vboost

R4

R3

R2

R1

Optional

RZMPP

Optional

VbuckR8 R7

Optional

LBUCK

10 µHCBUCK10 µFVbuck

CBOOST22 µFVboostLBOOST

10 µHCSRC10 µF

Primarybattery

(optional)

CLV10 µF

CHV10 µF HV

Load

R5

R6

Optional

LVLoad

GNDVbuck

GNDVbuck

GNDVbuck

GNDVbuck

GNDVbuck

GNDVbuck

GNDVbuck

PRIM

FB PRIM U

FB PRIM D

SELMPP[1]

SELMPP[0]

ZMPP

SRC

SET OVCH

SET CHRDY

SET OVDIS

CFG[0]

CFG[1]

CFG[2]

GN

D

BATT

BAL

HVOUT

SWBUCK

BUCK

LVOUT

STATUS[2 : 0]

ENHV

ENLV

FB HV

BU

FSRC

SW

BO

OST

BO

OST

Figure 3: Functional block diagram



M1

M2

M7

M8

M9 M3

M4

M6

M5

BUCKBOOST

HLDO

LLDO


Matchingnetwork

Rectifier

Primarybattery

(optional)

Li-ionbattery

LBUCK CBUCK

CBOOSTLBOOSTCSRC

CLV

CHV

SRCHVOUT

LVOUT

BATT

BUCKSWBUCK

SWBOOST BOOSTBUFSRC

PRIM

Figure 4: Simplified schematic view of the AEM30940

7 Theory of Operation

7.1 Deep sleep & Wake up modes

The DEEP SLEEP MODE is a state where all nodes are deeplydischarged and there is no available energy to be harvested.As soon as the required cold-start voltage of 380 mV and asparse amount of power of just 3 µW becomes available onSRC , the WAKE UP MODE is activated. Vboost and Vbuckrises up to a voltage of 2.2 V. Vboost then rises alone up toVovch.

At that stage, both LDOs are internally deactivated. There-fore, STATUS[0] is equal to 0 as shown in Figure 9 and Fig-ure 10.

When Vboost reaches Vovch, two scenarios are possible: inthe first scenario, a super-capacitor or a capacitor having avoltage lower than Vchrdy is connected to the BATT node.In the second scenario, a charged battery is connected to theBATT node.

Frequency [MHz] Pin [dBm] Pin [µW]863-868 -18.2 15.1915-921 -18.5 14.1925-960 -17.8 16.6

1805-1880 -16.4 22.92110-2170 -14 39.82400-2500 -9.5 112.2

Table 6: Minimum input power for the cold start (typical).Results obtained with the matching network and rectifier de-signed by e-peas

Supercapacitor as a storage element

If the storage element is a supercapacitor, the storage elementmay need to be charged from 0 V. The boost converter chargesBATT from the input source and by modulating the conduc-

tance of M2. During the charge of the BATT node, bothLDOs are deactivated and STATUS[0] is de-asserted. WhenVbatt reaches Vchrdy, the circuit enters NORMAL MODE,STATUS[0] is asserted and the LDOs can be activated by theuser using the ENLV and ENHV control pins as shown in Fig-ure 9.

Battery as a storage elementIf the storage element is a battery, but its voltage is lower thanVchrdy, then the storage element first needs to be charged un-til it reaches Vchrdy. Once Vbatt exceeds Vchrdy, or if thebattery was initially charged above Vchrdy, the circuit entersNORMAL MODE. STATUS[0] is asserted and the LDOs canbe activated by the user thanks to ENLV and ENHV as shownin Figure 10.

Normal mode

Deep sleep

mode

Wake up

mode

1

2

If 380 mV and 3 µW on SRC

If BATT > Vchrdy

3

Overvoltage

mode

4

Shutdown

mode

6

Primary mode

5

If BATT > Vovch

If BATT < Vovdis

&

Primary baery connected

If BATT < Vovdis

&

No primary baery

connected

Aer 600 ms

If BATT > Vchrdy

If BATT > Vchrdy

If BATT < Vovch

Figure 5: Diagram of the AEM30940 modes



7.2 Normal mode

Once the AEM enters NORMAL MODE, three scenarios arepossible:

• There is enough power provided by the source to main-tain Vbatt above Vovdis but Vbatt is below Vovch. Inthat case, the circuit remains NORMAL MODE.

• The source provides more power than the load consumes,and Vbatt increases above Vovch, the circuit enters intothe OVERVOLTAGE MODE, as explained in the Over-voltage mode section.

• Due to a lack of power from the source, Vbatt falls be-low Vovdis. In this case, either the circuit enters SHUT-DOWN MODE as explained in Shutdown mode sectionor, if a charged primary battery is connected on PRIM,the circuit enters PRIMARY MODE as explained in thePrimary mode section.

Matching network and rectifier

To connect AC sources to the AEM30940, an external rectifieris required as well as a matching network in the case RF energyharvesting. The objective of the matching network is to modifythe impedance relationship between the RF source and the rec-tifier in order to optimize the power transfer over a frequencyband and an input power range. For RF applications, exter-nal high frequency rectifiers as well as matching networks areavailable 1 for the following RF bands: 828MHz, 915MHz,945MHz (GSM900), 1.84GHz (GSM1800), 2.11GHz (3G),2.45GHz (WiFi).

Boost

The boost (or step-up) converter raises the voltage available atBUFSRC to a level suitable for charging the storage element,in the range of 2.2 V to 4.5 V, according to the system con-figuration. This voltage (Vboost) is available at the BOOSTpin. The switching transistors of the boost converter are M3and M4, with the switching node available externally at SW-BOOST. The reactive power components of this converter arethe external inductor and capacitor LBOOST and CBOOST.

Periodically, the MPP control circuit disconnects the sourcefrom the BUFSRC pin with the transistor M1 in order to mea-sure the open-circuit voltage of the harvester on SRC and de-fine the optimal level of voltage. BUFSRC is decoupled bythe capacitor CSRC, which smooths the voltage against thecurrent pulses induced by the boost converter.

The storage element is connected to the BATT pin, at a volt-age Vbatt. This node is linked to BOOST through the transis-tor M2. In NORMAL MODE, this transistor effectively shortsthe battery to the BOOST node (Vbatt = Vboost). Whenenergy harvesting is occurring, the boost converter delivers acurrent that is shared between the battery and the loads. M2 isopened to disconnect the storage element when Vbatt reachesVovdis. However, in such a scenario, the AEM30940 offers thepossibility of connecting a primary battery to recharge Vbatt

up to the Vchrdy. The transistor M9 connects PRIM to BUF-SRC and the transistor M1 is opened to disconnect the SRCinput pin as explained in the Primary mode section and shownin Figure 13.

BuckThe buck (or step-down) converter lowers the voltage fromVboost to a constant Vbuck value of 2.2 V. This voltage isavailable at the BUCK pin. The switching transistors of thebuck converter are M5 and M6, with the switching node avail-able externally at SWBUCK. The reactive power componentsof the buck converter are the external inductor LBUCK andthe capacitor CBUCK.

LDO outputsTwo LDOs are available to supply loads at different operatingvoltages:Through M7, Vboost supplies the high-voltage LDO that pow-ers its load through HVOUT. This regulator delivers a cleanvoltage (Vhv) with a maximum current of 80 mA on HVOUT.In the built-in configuration modes, an output voltage of 1.8 V,2.5 V or 3.3 V can be selected. In the custom configurationmode, it is adjustable between 2.2 V and Vbatt-0.3 V.Thehigh-voltage output can be dynamically enabled or disabledwith the logic control pin ENHV. The output is decoupled bythe external capacitor CHV.Through M8, Vbuck supplies the low-voltage LDO that pow-ers its load through LVOUT. This regulator delivers a cleanvoltage (Vlv) of 1.8 V or 1.2 V with a maximum current of20 mA on LVOUT. The low-voltage output can be dynami-cally enabled or disabled with the logic control pin ENLV. Theoutput is decoupled by the external capacitor CLV.Status pin STATUS[0] alerts the user when the LDOs can beenabled as explained in the Deep sleep & Wake up modessection and in the Shutdown mode section. The table belowshows the four possible configurations:

ENLV ENHV LV output HV output1 1 Enabled Enabled1 0 Enabled Disabled0 1 Disabled Enabled0 0 Disabled Disabled

Table 7: LDOs configurations

7.3 Overvoltage mode

When Vbatt reaches Vovch, the charge is complete and theinternal logic maintains Vbatt around Vovch with a hysteresisof a few mV as shown in Figure 11 to prevent damage to thestorage element and to the internal circuitry. In this configura-tion, the boost converter is periodically activated to maintainVbatt and the LDOs are still available. Moreover, when theboost converter is not activated, the transistor M1 in Figure 4is opened to prevent current from the source to the storageelement when Vsrc is higher than Vovch.

1Contact [email protected] for additional information



7.4 Primary mode

When Vbatt drops below Vovdis, the circuit compares the volt-age on PRIM with the voltage on FB PRIM U to determinewhether a charged primary battery is connected on PRIM. Thevoltage on FB PRIM U is set thanks to two optional resis-tances as explained in the Primary battery configuration sec-tion. If the voltage on PRIM divided by 4 is higher than thevoltage on FB PRIM U, the circuit considers the primary bat-tery as available and the circuit enters PRIMARY MODE asshown in Figure 13.In that mode, transistor M1 is opened and the primary batteryis connected to BUFSRC through transistor M9 to becomethe source of energy for the AEM30940. The chip remains inthis mode until Vbatt reaches Vchrdy. When Vbatt reachesVchrdy, the circuit enters NORMAL MODE. As long as thechip is in PRIMARY MODE, STATUS[1] is asserted.If no primary battery is used in the application, PRIM,FB PRIM U and FB PRIM D must be tied to GND.

7.5 Shutdown mode

When Vbatt drops below Vovdis and no power is available froma primary battery, the circuit enters SHUTDOWN MODE asshown in Figure 12 to prevent deep discharge potentially lead-ing to damage to the storage element and instability of theLDOs. The circuit asserts STATUS[1] to warn the system thata shutdown will occur. Both LDO regulators remain enabled.If no primary battery is used, this allows the load, whether it ispowered on LVOUT or HVOUT, to be interrupted by the low-to-high transition of STATUS[1], and to take all appropriateactions before power shutdown.If energy at the input source is available and Vbatt recov-ers to Vchrdy within Tcrit (∼ 600 ms), the AEM returns inNORMAL MODE. But if, after Tcrit, Vbatt does not reachVchrdy, the circuit enters DEEP SLEEP MODE. The LDOsare deactivated and BATT is disconnected from BOOST toavoid damaging the battery due to the overdischarge. Fromnow, the AEM will have to go through the wake-up proceduredescribed in the Deep sleep & Wake up modes section.

7.6 Maximum power point trackingDuring NORMAL MODE, SHUTDOWN MODE and a part ofWAKE UP MODE, the boost converter is regulated thanks to

an internal MPPT (Maximum Power Point Tracking) module.Vmpp is the voltage level of the MPP, and depends on theinput power available at the source. The MPPT module eval-uates Vmpp as a given fraction of Voc, the open-circuit voltageof the source. By temporarily disconnecting the source fromCSRC as shown in Figure 4 for 5.12 ms, the MPPT module re-ceives from and maintains knowledge of Vmpp. This samplingoccurs approximatively every 0.33 s .

With the exception of this sampling process, the voltage acrossthe source, Vsrc, is continuously compared to Vmpp. WhenVsrc exceeds Vmpp by a small hysteresis, the boost converteris switched on, extracting electrical charges from the sourceand lowering its voltage. When Vsrc falls below Vmpp by asmall hysteresis, the boost converter is switched off, allowingthe harvester to accumulate new electrical charges into CSRC,which restores its voltage. In this manner, the boost con-verter regulates its input voltage so that the electrical current(or flow of electrical charges) that enters the boost converteryields the best power transfer from the harvester under anyambient conditions. The AEM30940 supports any Vmpp levelin the range from 0.05 V to 5 V. It offers a choice of four valuesfor the Vmpp/Voc fraction or to match the input impedanceof the BOOST converter with an impedance connected to theZMPP terminal through configuration pins SELMPP[1:0] asshown in Table 9. The status of the MPPT controller is re-ported through one dedicated status pins (STATUS[2]). Thestatus pin is asserted when a MPP calculation is being per-formed.

7.7 Balun for dual-cell supercapacitor

The balun circuit allows users to balance the internal volt-age in a dual-cell supercapacitor in order to avoid damagingthe super-capacitor because of excessive voltage on one cell.If BAL is connected to GND, the balun circuit is disabled.This configuration must be used if a battery, a capacitor ora single-cell supercapacitor is connected on BATT. If BAL isconnected to the node between the cells of a supercapacitor,the balun circuit compensates for any mismatch of the twocells that could lead to over-charge of one of both cells. Thebalun circuit ensures that BAL remains close to Vbatt/2. Thisconfiguration must be used if a dual-cell supercapacitor is con-nected on BATT.



8 System Configuration

Configuration pins Storage element threshold voltages LDOs output voltages Typical useCFG[2] CFG[1] CFG[0] Vovch Vchrdy Vovdis Vhv Vlv

1 1 1 4.12 V 3.67 V 3.60 V 3.3 V 1.8 V Li-ion battery1 1 0 4.12 V 4.04 V 3.60 V 3.3 V 1.8 V Solid state battery1 0 1 4.12 V 3.67 V 3.01 V 2.5 V 1.8 V Li-ion/NiMH battery1 0 0 2.70 V 2.30 V 2.20 V 1.8 V 1.2 V Single-cell supercapacitor0 1 1 4.50 V 3.67 V 2.80 V 2.5 V 1.8 V Dual-cell supercapacitor0 1 0 4.50 V 3.92 V 3.60 V 3.3 V 1.8 V Dual-cell supercapacitor0 0 1 3.63 V 3.10 V 2.80 V 2.5 V 1.8 V LiFePO4 battery0 0 0 Custom mode - Programmable through R1 to R6 1.8 V

Table 8: Usage of CFG[2:0]

8.1 Battery and LDOs configuration

Through three configuration pins (CFG[2:0]), the user can seta particular operating mode from a range that covers mostapplication requirements, without any dedicated external com-ponent as shown in Table 8. The three threshold levels aredefined as:

• Vovch : Maximum voltage accepted on the storage ele-ment before disabling the boost converter,

• Vchrdy : Minimum voltage required on the storage ele-ment after a cold start before enabling the LDOs,

• Vovdis : Minimum voltage accepted on the storage ele-ment before considering the storage element as depleted.

See Theory of Operation section for more information aboutthe purposes of these thresholds.The two LDOs output voltages are called Vhv and Vlv forthe high- and low-output voltages, respectively. In the built-inconfiguration mode, seven combinations of these voltage levelsare hardwired and selectable through the CFG[2:0] configura-tion pins, covering most application cases. When a prede-fined configuration is selected, the resistor pins dedicated toa custom configuration should be left floating (SET OVDIS,SET CHRDY, SET OVCH, FB HV).A custom mode allows the user to define the Vovch, Vchrdy,Vovdis and Vhv threshold voltages.

Custom modeWhen CFG[2:0] are tied to GND, the custom mode is selectedand all six configuration resistors shown in Figure 6, must bewired as follows:Vovch, Vchrdy and, Vovdis are defined thanks to R1, R2, R3and R4. If we define the total resistor (R1 + R2 + R3 + R4)as RT, R1, R2, R3 and R4 are calculated as:

• 1 MΩ ≤ RT ≤ 100 MΩ

• R1=RT(1 V/Vovch)

• R2=RT(1 V/Vchrdy - 1 V/Vovch)

• R3=RT(1 V/Vovdis - 1 V/Vchrdy)

• R4=RT(1 - 1 V/Vovdis)

Vhv is defined thanks to R5 and R6. If we define the totalresistor( R5 + R6) as RV, R5 and R6 are calculated as:

• 1 MΩ ≤ RV ≤ 40 MΩ

• R5=RV(1 V/Vhv)

• R6=RV(1 - 1 V/Vhv)

The resistors should have high values to make the additionalpower consumption negligible. Moreover, the following con-straints must be adhered to ensure the functionality of thechip:

• Vchrdy + 0.05 V ≤ Vovch ≤ 4.5 V

• Vovdis + 0.05 V ≤ Vchrdy ≤ Vovch - 0.05 V

• 2.2 V ≤ Vovdis

• Vhv ≤ Vovdis - 0.3 V

AEM

HVOUT

FB_HVHV

Load

BOOST

SET_CHRDY

SET_OVDIS

SET_OVCH

CFG[2:0]R4

R3

R2

R1

R6

R5

CBOOST

CHV

Figure 6: Custom configuration resistors



8.2 MPPT configuration

Two dedicated configuration pins, SELMPP[1:0], allow select-ing the MPP tracking ratio based on the characteristic of theinput power source.

SELMPP[1] SELMPP[0] Vmpp/Voc0 0 50 %0 1 65 %1 0 80 %1 1 ZMPP

Table 9: Usage of SELMPP[1:0]

8.3 Primary battery configuration

To use the primary battery, it is mandatory to determineVprim min, the voltage of the primary battery at which ithas to be considered as empty. During the evaluation ofVprim min, the circuit connects FB PRIM D to GND. The cir-cuit uses a resistive divider between BUCK and FB PRIM D todefine the voltage on FB PRIM U as Vprim min divided by 4.When Vprim min is not evaluated, FB PRIM D is left floatingto avoid quiescent current on the resistive divider. If we definethe total resistor (R7 + R8) as RP, R7 and R8 are calculatedas:

• 100 kΩ ≤ RP ≤ 500 kΩ

• R7= (Vprim min4

* RP)/2.2 V

• R8=RP-R7

Note that FB PRIM U and FB PRIM D must be tied to GNDif no primary battery is used.

8.4 ZMPPT configuration

Instead of working at a ratio of the open-circuit voltage, theAEM30940 can regulate the input impedance of the BOOSTconverter so that it matches a constant impedance connectedto the ZMPP pin (RZMPP). In this case, the AEM30940 reg-ulates Vsrc at a voltage equals to the product of the ZMPPimpedance and the current available at the SRC input.

• 10 Ω ≤ RZMPP ≤ 1 MΩ

8.5 No-battery configuration

If the harvested energy source is permanently available andcovers the application purposes or if the application does notneed to store energy when the harvested energy source is notavailable, the storage element may be replaced by an externalcapacitor CBATT of minimum 150 µF.

8.6 Storage element information

The energy storage element of the AEM30940 can be arechargeable battery, a supercapacitor or a large capacitor(minimum 150 µF). It should be chosen so that its voltagedoes not fall below Vovdis even during occasional peaks of theload current. If the internal resistance of the storage elementcannot sustain this voltage limit, it is advisable to buffer thebattery with a capacitor.The BATT pin that connects the storage element must neverbe left floating. If the application expects a disconnection ofthe battery (e.g. because of a user removable connector), thePCB should include a capacitor of at least 150 µF. The leak-age current of the storage element should be small as leakagecurrents directly impact the quiescent current of the subsys-tem.

External inductors informationThe AEM30940 operates with two standard miniature induc-tors of 10 µH. LBOOST and LBUCK must respectively sustaina peak current of at least 250 mA and 50 mA and a switchingfrequency of at least 10MHz. Low equivalent series resistance(ESR) favors the power conversion efficiency of the boost andbuck converters.

External capacitors informationThe AEM30940 operates with four identical standard minia-ture ceramic capacitors of 10 µF and one miniature ceramic ca-pacitor of 22 µF. The leakage current of the capacitors shouldbe small as leakage currents directly impact the quiescent cur-rent of the subsystem.CSRCThis capacitor acts as an energy buffer at the input of theboost converter. It prevents large voltage fluctuations whenthe boost converter is switching. The recommended value is10 µF +/- 20 %.CBUCKThis capacitor acts as an energy buffer for the buck converter.It also reduces the voltage ripple induced by the current pulsesinherent to the switched mode of the converter. The recom-mended value is 10 µF +/- 20 %.CBOOSTThis capacitor acts as an energy buffer for the boost converter.It also reduces the voltage ripple induced by the current pulsesinherent to the switched mode of the converter. The recom-mended value is 22 µF +/- 20 %.CHV and CLVThese capacitors ensure a high-efficiency load regulation ofthe high-voltage and low-voltage LDO regulators. Closed-loopstability requires the value to be in the range of 8 µF to 14 µF.



9 Typical Application Circuits

9.1 Example circuit 1

AEM30940QFN28


Matchingnetwork

Rectifier

Primarybattery

(optional)

3.5V < Vprim < 5V

Li-ionbattery

3.6V < Vbatt < 4.12V

200 kΩ 300 kΩ

VbuckR8R7

LBUCK

10 µHCBUCK10 µF

CBOOST22 µFLBOOST

10 µHCSRC10 µF

CLV10 µF

CHV10 µF

Micro-controller

Vlv = 1.8V

Level-shifter

Vbuck

Radiotransceiver

Vhv = 3.3V

Vbuck

Vbuck

Vbuck

GND

GND

SRC

ZMPP

BUFSRC

SWBOOST

BOOST

SWBUCK

BUCK

CFG[2]

CFG[1]

CFG[0]

SELMPP[1]

SELMPP[0]

GN

D

FB PRIM U

FB PRIM D

PRIM

BATT

BAL

HVOUT

LVOUT

STATUS[2 : 0]

ENHV

ENLV

SET OVCH

SET CHRDY

SET OVDIS

FB HV

Figure 7: Typical application circuit 1

The energy source is a RF source, and the storage elementis a standard Li-ion battery cell. The radio communicationmakes use of a transceiver that operates from a 3.3 V sup-ply. A micro-controller supplied by a 1.8 V supply controls theapplication.

This circuit uses a pre-defined operating mode, typical of sys-tems that use standard components for radio and energy stor-age.

The operating mode pins are connected to:

• CFG[2:0] = 111

Referring to Table 8, in this mode, the threshold voltages are:

• Vovch = 4.12 V

• Vchrdy = 3.67 V

• Vovdis = 3.60 V

Moreover, the LDOs output voltages are:

• Vhv = 3.3 V

• Vlv = 1.8 V

A primary battery is also connected as a back-up solution. Theminimal level allowed on this battery is set at 3.5 V. Followingequations on Page 12:

• RP = 0.5 MΩ

• R7 = (3.5 V4

*0.5 MΩ)/2.2 V = 200 kΩ

• R8 = 0.5 MΩ-200 kΩ = 300 kΩ

The MPP configuration pins SELMPP[1:0] are tied to GND(logic low), selecting an MPP ratio of 50 %.The ENLV enable pin for the low-voltage LDO is tied to BUCK.The microcontroller will be enabled when Vbatt and Vboostexceed Vchrdy as the low-voltage regulator supplies it.The application software can enable or disable the radiotransceiver with a GPIO connected to ENHV.



9.2 Example circuit 2

AEM30940QFN28

Rectifier

Vboost

R4 38.6MΩ

R3 2.57MΩ

R2 850 kΩ

R1 12MΩ

GND

Supercapacitor

3.6V < Vbatt < 4.12V

GND

GND

LBUCK

10 µHCBUCK10 µF

CBOOST22 µFLBOOST

10 µHCSRC10 µF

CLV10 µF

CHV10 µF

Micro-controller

Vlv = 1.8V

Level-shifter

Vbuck

Sensor

Vhv = 3.3V

R5 10.6MΩ

R6 24.4MΩ

GND

GND

GND

Vbuck

Vbuck

RZMPP

1 kΩ

SRC

ZMPP

BUFSRC

SWBOOST

BOOST

SWBUCK

BUCK

CFG[2]

CFG[1]

CFG[0]

SELMPP[1]

SELMPP[0]

GN

D

FB PRIM U

FB PRIM D

PRIM

BATT

BAL

HVOUT

LVOUT

STATUS[2 : 0]

ENHV

ENLV

SET OVCH

SET CHRDY

SET OVDIS

FB HV

Figure 8: Typical application circuit 2

The energy source is an piezo source, and the storage ele-ment is a dual-cell supercapacitor. The supercapacitor can becompletely depleted during the cold start.Moreover, BAL is connected to the dual-cell supercapacitor tocompensate for any mismatch between the two cells and inthat way protect the supercapacitor.A micro-controller pilots and collects information from a sen-sor. The operating mode pins are connected to:

• CFG[2:0]= 000

The user wants a custom configuration with Vovch, Vchrdyand Vovdis at 4.5 V, 4.2 V and 3.5 V, respectively. The userchoose 54 MΩ for RT. Following the equation in page 11:

• R1=54 MΩ( 1 V

4.5 V)=12 MΩ

• R2=54 MΩ( 1 V

4.2 V- 1 V

4.5 V)=850 kΩ

• R3=54 MΩ( 1 V

3.5 V- 1 V

4.2 V)=2.57 MΩ

• R4=54 MΩ(1- 1 V

3.5 V)=38.6 MΩ

In the custom mode, the Vlv equals 1.8 V and the applica-tion software can enable or disable the sensor with a GPIOconnected to ENLV.On Vhv, the user wants a 3.3 V voltage. As shown in page 11,the user chooses a resistor RV equal to 35 MΩ

• R5=35 MΩ( 1 V

3.3 V)=10.6 MΩ

• R6=35 MΩ(1- 1 V

3.3 V)=24.4 MΩ

The ENHV enable pin for the high-voltage LDO is tied toBUCK. The microcontroller is enabled when Vbatt and Vboostexceeds Vchrdy as the high-voltage regulator supplies it.The MPP configuration pins SELMPP[1:0] are tied to BUCK(logic high), selecting the ZMPPT configuration to match a1 KΩ impedance.No primary battery is connected and the PRIM, FB PRIM Uand FB PRIM D pins are tied to GND.



0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.50

1

2

3

4

5

Time [s]

Voltag

e[V

]VBATT LVOUT HVOUT VBUCK

Vovch

Vchrdy

WAKE UP MODENORMAL

MODE

Voltag

e[V

]

STATUS[0]STATUS[1]STATUS[2]

0

CFG[2:0] = 3’b010, SELMPP[1:0] = 2’b10, Storage element: capacitor (480µF), SRC: current source(2mA) with voltage compliance (1V), ENLV = 1’b1, ENHV = 1’b1, LVOUT load = 100 kΩ, HVOUTload = 100kΩ.

Figure 9: Cold start with a capacitor connected to BATT

0 0.5 1 1.5 2 2.5 3 3.5 40

1

2

3

4

5

Time [s]

Voltag

e[V

]

VBATT LVOUT HVOUT VBUCK

Vovch

Vchrdy

WAKE UP MODE NORMAL MODEOVERVOLTAGE

MODE

Voltag

e[V

]


0

CFG[2:0] = 3’b010, SELMPP[1:0] = 2’b10, Storage element: capacitor (480 µF) pre-charged at 3V,SRC: current source (2mA) with voltage compliance (1 V), ENLV = 1’b1, ENHV = 1’b1, LVOUTload = 100kΩ, HVOUT load = 100kΩ.

Figure 10: Cold start with a battery connected to BATT



0 2 4 6 8 10 12 14 16 18 20 22 240

1

2

3

4

5

Time [s]

Voltag

e[V

]VBATT LVOUT HVOUT VBUCK

Vovch

Vchrdy

NORMAL MODE OVERVOLTAGE MODE NORMAL MODE

Voltag

e[V

]


0

1

CFG[2:0] = 3’b111, SELMPP[1:0] = 2’b00, Storage element: capacitor (4.85mF), SRC: currentsource (1 mA) with voltage compliance (3 V), ENLV = 1’b1, ENHV = 1’b1, LVOUT load = 22 kΩ,HVOUT load = 22 kΩ.

Figure 11: Overvoltage mode

0 1 2 3 4 5 6 7 8 9 10 11 12 130

1

2

3

4

5

Time [s]

Voltag

e[V

]

VBATT LVOUT HVOUT VBUCK

Vovdis

NORMAL MODE SHUTDOWN MODE DEEP SLEEP MODE

Voltag

e[V

]


CFG[2:0] = 3’b010, SELMPP[1:0] = 2’b10, Storage element: capacitor (4.85mF), SRC: currentsource (2 mA) with voltage compliance (1 V), ENLV = 1’b1, ENHV = 1’b1, LVOUT load = 10 kΩ,HVOUT load = 10 kΩ.

Figure 12: Shutdown mode (without primary battery)



0 1 2 3 4 5 6 7 8 9 100

1

2

3

4

5

Time [s]

Voltag

e[V

]VBATT LVOUT HVOUT VPRIM

Vchrdy

Vovdis

NORMAL MODE PRIMARY MODE NORMAL MODE

Voltag

e[V

]


1

CFG[2:0] = 3’b111, SELMPP[1:0] = 2’b10, Storage element: capacitor (4.85mF), SRC: current source(1mA) with voltage compliance (3 V), ENLV = 1’b1, ENHV = 1’b1, LVOUT load = 22 kΩ, HVOUTload = 22 kΩ, PRIM: voltage source (3V) with current compliance (1 mA). R7 = 68 kΩ, R8 = 330kΩ.

Figure 13: Switch to primary battery if the battery is overdischarged



10 Performance Data

10.1 BOOST conversion efficiency

0 0.5 1 1.5 2 2.5 3 3.5 4 4.50

10

20

30

40

50

60

70

80

90

100

VSRC [V] (ISRC = 100µA)

Effi

cien

cy[%

]

VBOOST = 2.6V

VBOOST = 3.6V

VBOOST = 4.1V

0 0.5 1 1.5 2 2.5 3 3.5 4 4.50

10

20

30

40

50

60

70

80

90

100

VSRC [V] (ISRC = 1mA)Effi

cien

cy[%

]

VBOOST = 2.6V

VBOOST = 3.6V

VBOOST = 4.1V

0 0.5 1 1.5 2 2.5 3 3.5 4 4.50

10

20

30

40

50

60

70

80

90

100

VSRC [V] (ISRC = 10mA)

Effi

cien

cy[%

]

VBOOST = 2.6V

VBOOST = 3.6V

VBOOST = 4.1V

0 0.5 1 1.5 2 2.5 3 3.5 4 4.50

10

20

30

40

50

60

70

80

90

100

VSRC [V] (ISRC = 100mA)

Effi

cien

cy[%

]

VBOOST = 2.6V

VBOOST = 3.6V

VBOOST = 4.1V

Figure 14: Boost efficiency for Isrc at 100 µA, 1 mA, 10 mA and 100 mA

10.2 Quiescent current

2.5 3 3.5 4 4.50

0.2

0.4

0.6

0.8

1

VBATT [V]

Quie

scen

tcu

rren

t[µA] LDOs OFF

LDOs ON

Figure 15: Quiescent current with LDOs on and off



10.3 High-voltage LDO regulation

3.4 3.6 3.8 4 4.2 4.4 4.63

3.1

3.2

3.3

3.4

VBATT [V]

VH

VO

UT

[V]

IHVOUT = 10 µAIHVOUT = 10 mA

IHVOUT = 80 mA

3 3.5 4 4.5

2.3

2.4

2.5

2.6

VBATT [V]

VH

VO

UT

[V]


IHVOUT = 80 mA

Figure 16: HVOUT at 3.3 V and 2.5 V

10.4 Low-voltage LDO regulation

2.2 2.3 2.4 2.5 2.6 2.7 2.8

1.16

1.18

1.2

1.22

1.24

VBATT [V]

VLV

OU

T[V

]

ILVOUT = 10 µAILVOUT = 1mA

ILVOUT = 20mA

3 3.5 4 4.5

1.76

1.78

1.8

1.82

1.84

VBATT [V]

VLV

OU

T[V

]


ILVOUT = 20mA

Figure 17: LVOUT at 1.2 V and 1.8 V



10.5 High-voltage LDO efficiency

2 2.5 3 3.5 4 4.50

20

40

60

80

100

VBATT [V] (VHV = 1.8V)

Effi

cien

cy[%

]

IHVOUT = 100 µAIHVOUT = 10mA

IHVOUT = 80mA

3 3.5 4 4.50

20

40

60

80

100


Effi

cien

cy[%

]


IHVOUT = 80 mA

3.8 4 4.2 4.40

20

40

60

80

100


Effi

cien

cy[%

]


IHVOUT = 80 mA

Figure 18: HVOUT efficiency at 1.8 V, 2.5 V and 3.3 V

The theoretical efficiency of a LDO can be simply calculated as VoutVin if quiescent current can be neglected with regards to the

output current. In the case of the high-voltage LDO, the theoretical efficiency is equal to VhvVbatt .

10.6 Low-voltage LDO efficiency

2 2.5 3 3.5 4 4.50

20

40

60

80

100

VBATT [V] (VLV = 1.2V)

Effi

cien

cy[%

]


ILVOUT = 20 mA

3 3.5 4 4.50

20

40

60

80

100

VBATT [V] (VLV = 1.8V)

Effi

cien

cy[%

]


ILVOUT = 20mA

Figure 19: Efficiency of BUCK cascaded with LVOUT at 1.2 V and 1.8 V

The theoretical efficiency of the low-voltage LDO is equal to VlvVbuck . Starting from the battery, the efficiency of the buck

converter has to be taken into account (see Figure 4). The efficiency between Vbatt and Vlv is therefore equal to ηbuckVlv

Vbuck .



10.7 RF path efficiency

−20 −15 −10 −5 0 5 100

10

20

30

Input power [dBm]

RF

pat

heffi

cien

cy[%

]

863MHz

865MHz

868MHz

Figure 20: Efficiency for 863-868 MHz band

−20 −15 −10 −5 0 5 100

10

20

30

40

Input power [dBm]

RF

pat

heffi

cien

cy[%

]

915MHz

918MHz

921MHz


−20 −15 −10 −5 0 5 100

10

20

30

40

Input power [dBm]

RF

pat

heffi

cien

cy[%

]

925MHz

945MHz

960MHz


−20 −15 −10 −5 0 5 100

10

20

30

40

50

Input power [dBm]

RF

pat

heffi

cien

cy[%

]

1.805GHz

1.84GHz

1.88GHz

Figure 23: Efficiency for 1.805-1.880 GHz band

−20 −15 −10 −5 0 5 100

5

10

15

20

25

Input power [dBm]

RF

pat

heffi

cien

cy[%

]

2.11GHz

2.14GHz

2.17GHz


−20 −15 −10 −5 0 5 100

10

20

30

Input power [dBm]

RF

pat

heffi

cien

cy[%

]

2.4GHz

2.45GHz

2.5GHz


The RF path efficiency is defined as the ratio between the power available at the output of the rectifier (SRC) and the powerat the input of the matching network (50Ω single input SMA).



10.8 Overall efficiency

−20 −15 −10 −5 0 5 100

10

20

30

40

Input power [dBm]

Ove

rall

effici

ency

[%]

865MHz

918MHz

945MHz

1.8GHz

2.14MHz

2.45GHz

Figure 26: Overall efficiency (RF path and boost con-verter) with VBOOST = 4.5V

The overall efficiency is defined as the ratio between the power available at the output of the boost converter and the powerat the input of the matching network (50Ω single input SMA).



11 Schematic

Figure 27: Schematic example

Designator Description Quantity Supplier LinkCBOOST Ceramic Cap 22 µF, 10 V, 20 %, X5R 0603 1 Farnell http://be.farnell.com/2426957CBUCK Ceramic Cap 10 µF, 10 V, 20 %, X5R 1 Farnell http://be.farnell.com/2309028CHV Ceramic Cap 10 µF, 10 V, 20 %, X5R 1 Farnell http://be.farnell.com/2309028CLV Ceramic Cap 10 µF, 10 V, 20 %, X5R 1 Farnell http://be.farnell.com/2309028CSRC Ceramic Cap 10 µF, 10 V, 20 %, X5R 1 Farnell http://be.farnell.com/2309028LBOOST Power Inductor 10 µH - 0,55 A - LPS4012 1 Farnell http://be.farnell.com/2408076LBUCK Power Inductor 10 µH - 0,25 A 1 Farnell http://be.farnell.com/2215635U1 AEM30940 - Symbol QFN28 1 order at [email protected]

Table 10: BOM example for AEM30940 and its required passive components



12 Layout

Figure 28: Layout example for the AEM30940 and its passive components

Note: Schematic, symbol and footprint for the e-peas component can be ordered by contactingthe e-peas support: [email protected]



13 Package Information

13.1 Plastic quad flatpack no-lead (QFN28 5x5mm)

3.15 ± 0.10

3.1

5 ±

0.1

0

0.25 ±0.05

0.5 BSC

0.40 ± 0.05

0.4

0 ±

0.0

5

0.55 ± 0.10

3.00 Ref

5.00 ± 0.10

5.0

0 ±

0.1

0

0.85 ± 0.05

0.2 REF

0.02+ 0.03

- 0.02

28

1

R 0.169

0.3

75

Re

f

Figure 29: QFN28 5x5mm

13.2 Board layout

2.7

±

0.0

5

0.3 ± 0.050.825 ± 0.05

0.5 BSC

3.15 ±

0.05

3.1

5 ±

0.0

5

5.7

5 ±

0.0

53

.30

±

0.0

5

Figure 30: Board layout


DATASHEET AEM30940 - E-peas · the shutdown of the AEM, the status pin STATUS[1] alerts the user...

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Transcript of DATASHEET AEM30940 - E-peas · the shutdown of the AEM, the status pin STATUS[1] alerts the user...