DATA SHEET Maintenance/ (planed maintenance type, … · 2017. 5. 30. · ov10 ov9r ov11a dvdd3...
Transcript of DATA SHEET Maintenance/ (planed maintenance type, … · 2017. 5. 30. · ov10 ov9r ov11a dvdd3...
1Publication date: October 2008 SDB00165BEB
DATA SHEET
NN12081APart No.
Package Code No. MBGA111-P2-0808ACA
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NN12081A
2SDB00165BEB
ContentsOverview ………………………………………………….…………………………………………………………. 3
Features ………………………………………………….…………………………………………………………. 3
Applications ……….………………………………………………………………………………………………… 3
Package ……………………………………………………………………………………………………………. 3
Type …………………………………...……………………………………………………………………………. 3
Block Diagram ….………………………………………………………………………..………………………… 4
Pin Descriptions …………………..………………………………………………………………………………. 5
Absolute Maximum Ratings ……………………..……………..…………………………………………………. 9
Operating Supply Voltage Range …………..……………………………………………………………………. 9
Electrical Characteristics ………………….………………….………………….………………………………. 10
Electrical Characteristics (Reference values for design) ………………….………………….………………. 14
Technical Data …………………………………….………………….……………………………………………. 15
1. Serial data control of AFE function block ……………………………………………………………………. 15
2. Serial data control of timing generator block ……………………….………………………………………. 19
3. Recommended pulse timing and signal processing flow ……………………....……………………………. 29
4. Function tables of V-driver block ………...……………..….…………………………………………………. 30
5. I/O block circuit diagrams and Pin function descriptions ……….…………………………………………. 31
Usage Notes ……….…..…………………….………………….…………………………………………………. 37
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NN12081A
3SDB00165BEB
NN12081AAnalog front-end processing IC for digital cameras
OverviewNN12081A is a front-end processing IC which has the built-in CDS, GCA, ADC, TG and V-driver for digital cameras. This product has the built-in high programmability TG and 23-ch. V-driver circuit that generate the vertical and horizontal CCD-
driving pulses and support not only 3 : 1 and 4 : 1 interlace but also 6 : 1 interlace 9 pixels mixing driving for CCD's.
FeaturesAnalog front end (1) CDS maximum input range: 1.2 V (at total gain = –2 dB)
(2) Variable CDS gain: –2 dB, 0 dB, 3 dB, 6 dB(3) Variable GCA gain: 0 dB to 36 dB (linear characteristic at dB scale)
The gain is calculated based on A/D output with full scale = 1 V[p-p](the gain range is 6 dB to 42 dB based on A/D output with 2 V[p-p] full scale)
(4) 12-bit, 45 MHz ADC(5) Variable OB clamp level: 256 steps(6) Pixel settling: 99.9% (by 1 sampling)(7) PSRR: 50 dB
TG and H-driver (1) Complete programmable vertical clocks and horizontal clocks(2) 17 vertical clocks and 12 charge readout clocks(3) Precise phase control of high speed pulses(4) Electronic shutter function(5) Strobe and mechanical shutter function (6) Internal SSG function(7) H-driver (H1 to H4, HL) and RG-driver
V-driver (1) 23-ch. V-driver and 1-ch. SUB-driver
ApplicationsDigital still camerasApplicable image sensorsCCD sensors with horizontal clock up to 45 MHz and with vertical clock up to 23-ch.
Package111 pin fine pitch ball grid array package (BGA type)
TypeCMOS IC
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NN12081A
4SDB00165BEB
Block Diagram
Note) This block diagram is for explaining functions. The part of the block diagram may be omitted, or it may be simplified.
SERIAL
I/O
HDVD
DRVSSDRVDD
DVSS2
OV11BOV11L
OV10OV9R OV11A
DVDD3
DVDD4
R
VRT
OV7BOV9L OSUBOV7A
AVDD1
DC_DET 2
CCDOUT
AVDD1
VRB
DC_DET 1
DC_DET3
AVSS1
CCD timing generator
XI
AVSS1
CCD vertical driver
DVDD3
DVSS4
DVSS3DVSS3
OV11ROV12
VL
EXADCLK
EXDS2
EXDS1
VMSUB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11
RESET
DATA
DCLK
XO ClockGenerator
AVDD2
AVSS2
CS
DVSS2
DVSS2
DVDD1
DVDD2
DVDD2DVDD2
H1
H2
H3
STO
SUBSW1
SHUT
OV9BOV8OV9AOV7S
VL
CH
1to
CH
12
V1
to V
12, V
7S,
V9L
, V9R
, V
11L,
V11
R
SUB
, SU
BC
NT
CLR
DVSS2
J7
D4
K2
J2
K1
K8
L8
L7
K11
L11
K6
K7
L10
L6
L5
C1
E1
D1
D2
A2
B1
J5
K5
B7
L2E2B2
F9
C8
C2
J6
G3
J3
J1
H2
A9
D11
C11
B11
A7
B10A10
B8
D10C10
L9
H4
SSGSW
H4
HL
A11
A8
DVDD3E10
DVSS2F2
DVSS1F8
CLKO TEST1TEST2
TEST3
SUBSW2G2
DVDD2
DVSS2L1
H3
OV6OV2OV5B
OV1AOV1B
OV5AOV3BOV4OV3A
VHH H5VH J4VH D7
DS1
DS2
CPOB
PBLK
ADCLK
Analog front end
E8G10G
9J8K9E9G
11G8
K10J9D8
F11
J10
J11
D9
H9
H8
C9
H10
H11B
9
F10
E11 D5
C7
B6
C6
B5
C5
A6
A5
A4
B4
C4
A3
B3
C3
H1
G1
F1 L3 K4
L4 K3
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5SDB00165BEB
Pin Descriptions
Output
Input
Output
Output
Output
Output
Output
Output
Ground
Power supply
Output
Output
Output
Output
Output
Output
Power supply
Output
Output
Ground
Power supply
Output
Ground
Output
Power supply
Output
Ground
Output
Power supply
Power supply
Ground
Power supply
Input
Ground
Type
A/D outputD11C3
A/D outputD10B3
A/D outputD3C6
A/D outputD2B6
A/D outputD1C7
Digital driver power supply for signal processing blockDRVDDA6
A/D outputD5C5
A/D outputD4B5
A/D outputD7B4
A/D outputD6A4
Digital driver ground for signal processing blockDRVSSA5
A/D outputD8C4
A/D outputD9A3
Crystal oscillator input (FCK or 2FCK)XIA2
Crystal oscillator output (FCK or 2FCK) XOB1
A/D outputD0B7
Power supply for φHL driver and φR driverDVDD4A7
φHL pulse outputHLA8
φR pulse outputRA9
Ground for φHL driver and φR driverDVSS4B8
Power supply for φH1 to φH4 driverDVDD3A10
φH4 pulse outputH4A11
Ground for φH1 to φH4 driverDVSS3C10
φH3 pulse outputH3B11
Power supply for φH1 to φH4 driverDVDD3B10
φH2 pulse outputH2C11
Ground for φH1 to φH4 driverDVSS3D10
φH1 pulse outputH1D11
Power supply for φH1 to H4 driverDVDD3E10
Power supply for timing generator blockDVDD1F9
Ground for timing generator blockDVSS1F8
Analog power supply for signal processing blockAVDD1K11
CDS signal inputCCDOUTL11
Analog ground for signal processing blockAVSS1L10
DescriptionPin namePin No.
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6SDB00165BEB
Pin Descriptions (continued)
—
—
Ground
Power supply
—
—
—
Ground
Power supply
Input
Input
Input
Input
Power supply
Ground
Input / Output
Input / Output
Output
Output
Output
Output
Output
Ground
Power supply
Input / Output
Input / Output
Output
Input
Input
Input
Input
Ground
Power supply
Type
DC level stabilization 2DC_DET2L7
Analog ground for signal processing blockAVSS1K8
Test input 3 (normally set Low)TEST3K3
Master mode (internal VD/HD) or slave mode (external VD/HD) selectSSGSWL3
Power supply for IODVDD2L2
Power supply for signal processing blockAVDD2J5
Test input 1 (normally set Low)TEST1K4
Test input 2 (normally set Low)TEST2L4
Voltage reference (Bottom)VRBL6
Voltage reference (Top)VRTL5
Ground for signal processing blockAVSS2K5
DC level stabilization 3DC_DET3K6
Analog power supply for signal processing blockAVDD1K7
DC level stabilization 1DC_DET1L8
Ground for IO and VM of V-driverDVSS2L1
Data S/H pulse outputEXDS2J2
Pre-charge S/H pulse outputEXDS1K2
A/D converter clock output (or field index output)EXADCLKK1
Strobe trigger outputSTOJ3
SUB bias voltage control pulse output 1SUBSW1H2
Mechanical shutter control pulseSHUTJ1
SUB bias voltage control pulse output 2SUBSW2G2
Ground for IO and VM of V-driverDVSS2F2
Power supply for IODVDD2E2
Vertical sync pulse input / outputVDH1
Horizontal sync pulse input / outputHDG1
FCK clock outputCLKOF1
Data latch input for serial data communicationsCSE1
Clock input for serial data communicationsDCLKD1
Data input for serial data communicationsDATAD2
All clear inputCLRC1
Ground for IO and VM of V-driverDVSS2C2
Power supply for IODVDD2B2
DescriptionPin namePin No.
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NN12081A
7SDB00165BEB
Pin Descriptions (continued)
Ground for IO and VM of V-driverGroundDVSS2C8
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power supply
Ground
Power supply
Power supply
Power supply
Ground
Power supply
Type
(V-driver) φV2 transfer pulse outputOV2B9
(V-driver) φV9R transfer pulse outputOV9RG11
(V-driver) φV9L transfer pulse outputOV9LG8
(V-driver) φV11R transfer pulse outputOV11RG10
(V-driver) φV1A transfer pulse outputOV1AE11
(V-driver) φV1B transfer pulse outputOV1BF10
(V-driver) φV7S transfer pulse outputOV7SF11
(V-driver) φV8 transfer pulse outputOV8D8
(V-driver) φV10 transfer pulse outputOV10E9
(V-driver) φV12 transfer pulse outputOV12E8
(V-driver) φV6 transfer pulse outputOV6D9
(V-driver) φV4 transfer pulse outputOV4C9
(V-driver) φV11L transfer pulse outputOV11LG9
(V-driver) φV3A transfer pulse outputOV3AH11
(V-driver) φV3B transfer pulse outputOV3BH10
(V-driver) φV5A transfer pulse outputOV5AH8
(V-driver) φV5B transfer pulse outputOV5BH9
(V-driver) φV7A transfer pulse outputOV7AJ11
(V-driver) φV7B transfer pulse outputOV7BJ10
(V-driver) φV9A transfer pulse outputOV9AJ9
(V-driver) φV9B transfer pulse outputOV9BK10
(V-driver) φV11A transfer pulse outputOV11AK9
(V-driver) φV11B transfer pulse outputOV11BJ8
(V-driver) φSUB transfer pulse outputOSUBL9
(V-driver) Middle-level power supply for φSUB driverVMSUBJ7
Ground for IO and VM of V-driverDVSS2J6
(V-driver) High-level power supply for φSUB driverVHHH5
(V-driver) High-level power supplyVHJ4
(V-driver) Low-level power supplyVLH4
Ground for IO and VM of V-driverDVSS2G3
Power supply for IODVDD2H3
DescriptionPin namePin No.
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NN12081A
8SDB00165BEB
Pin Descriptions (continued)
(V-driver) High-level power supplyPower supplyVHD7
Output
—
—
—
—
—
—
—
—
Input
Power supply
Type
Middle level for SUB bias voltage control pulse outputMSUBSWG4
Pin connected to DVSS2 inside—F4
Pin connected to DVSS2 inside—F3
Pin connected to DVSS2 inside—E4
Pin connected to DVSS2 inside—E3
Pin connected to DVSS2 inside—D6
Pin connected to DVSS2 inside—D3
Pin connected to nothing insideN.C.H7
Pin connected to nothing insideN.C.H6
(V-driver) Reset inputRESETD4
(V-driver) Low-level power supplyVLD5
DescriptionPin namePin No.
Note) 1. D3, D6, E3, E4, F3, F4 connect to DVSS2 inside.2. N.C. pins (H6, H7) do not connect to internal electric circuits. It is recommended to connect N.C. pins to the ground on PCB.
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NN12081A
9SDB00165BEB
Absolute Maximum Ratings
Operating Supply Voltage Range
V9.5 to 14.0VHSupply voltage 7
V9.5 to 16.0VHHSupply voltage 6
V1.65 to 3.6DRVDDSupply voltage 3
V2.7 to 3.6DVDD2Supply voltage 2
V1.65 to 1.95AVDD1,AVDD2, DVDD1
Supply voltage 1
V2.7 to 3.6DVDD4Supply voltage 5
V2.7 to 3.6DVDD3Supply voltage 4
V–7.0 to –4.5VLSupply voltage 8
VL + 2.0 to 5.0VMSUB
Range
VSupply voltage 9
NoteUnitSymbolParameter
*1V24VHH – VLSupply voltage 66
*1V3.9DVDD4Supply voltage 55
*1V3.9DVDD3Supply voltage 44
*1V3.9DRVDDSupply voltage 33
*1V3.9DVDD2Supply voltage 22
*1V22VH – VLSupply voltage 77
*1V2.0AVDD1, AVDD2,DVDD1
Supply voltage 11
*1V–7.5VLSupply voltage 88
*3°C– 50 to + 125TstgStorage temperature12
NoteUnitRatingSymbolParameterA No.
*3°C– 20 to + 75ToprOperating ambient temperature11
*2mW230.7PDPower dissipation10
*1V–5.5 to 6.0VMSUBSupply voltage 99
Note) *1: The range under absolute maximum ratings, power dissipation.*2: Power dissipation shows the value of only package at Ta = 75°C.
When using this IC, refer to the 6. Power dissipation (technical report) in the Usage Notes and use under the condition not exceeding the allowable value.
*3: Expect for the storage temperature and operating ambient temperature, all ratings are for Ta = 25°C.
Note) The values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
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NN12081A
10SDB00165BEB
—mA0.09—IVHHVHH dynamic current consumption —
*—No missing code—DNLA/D differential nonlinearity
—dB——32.5VIN = 15 mV[p-p]GGCA3Max. GCA gain14
—dB17.51614.5VIN = 50 mV[p-p]GGCA2Mid. GCA gain13
—dB0——VIN = 300 mV[p-p]GGCA1Min. GCA gain12
—LSB307255203VIN : No signalDOB2Max. output OB level11
—LSB520—VIN : No signalDOB1Min. output OB level10
—dB1.10–1.1VIN = 300 mV[p-p], 800 mV[p-p]GIDInput dynamic range9
Analog front end
—μA8——No load circuitIDDSTVHH , VH , VL static current consumption8
7
—mA0.36——SUB = Pulse (600 Hz, DVDD2, GND), CH1 to 12, V1 to 12, V7S, V9L, V9R, V11L, V11R = DVDD2, SUBCNT = GND, load circuit
IVL3VL dynamic current consumption6
—mA1.09——CH1 to 12 = Pulse (600 Hz, DVDD2 , GND), V1, V3, V5, V7, V9, V11 = GND, V2, V4, V6, V8, V10, V12, V7S, V9R, V9L, V11R, V11L, SUB = DVDD2 , SUBCNT = GND, load circuit
IVL2VL dynamic current consumption4
—mA0.24——IVHVH dynamic current consumption5
—dB1.80–3Ratio of 10 MHz XI to 45 MHz XIGCDSCDS sampling capability15
—mA11.9――
V1 to 12, V7S, V9R, V9L, V11R, V11L = Pulse (10 kHz, DVDD2, GND), CH1 to 12, SUB = DVDD2 , SUBCNT = GND, load circuit
IVL1VL dynamic current consumption3
—mA23——XI = 45 MHzIPOWDT
AVDD1, AVDD2, DVDD1 to DVDD4, DRVDD current consumption in power down mode
2
16
—V1.210.8VRT – VRBΔVRA/D reference voltage width17
Power dissipation
—mA126——XI = 45 MHzIVDDAVDD1, AVDD2, DVDD1 to DVDD4, DRVDD current consumption1
Limits
TypUnit
MaxNoteMin
ConditionsSymbolParameterB No.
Electrical Characteristics at AVDD1 = AVDD2 = DVDD1 = 1.8 V, DVDD2 = DVDD3 = DVDD4 = DRVDD = 3.0 V, VHH = 15.0 V, VH = 12.0 V, VL = –6.0 V, VMSUB = GNDNote) Ta = 25°C±2°C unless otherwise specified.
Note) *: The characteristic is reference value derived from the design of the IC and is not guaranteed by inspection.If a problem does occur related to this characteristic, we will respond in good faith to user concerns.
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NN12081A
11SDB00165BEB
Digital inputs and outputs
—VDVDD2—2.2
Digital pin: TEST1, TEST2, TEST3, SSGSW, VD, HD, CS, DCLK, DATA, CLR, EXDS1, EXDS2, XI, EXADCLK, RESET
VDIHHigh-level digital input voltage
—V0.5——IOL = +4 mADigital pin: EXDS1, EXDS2, EXADCLK, CLKO
V3OLLow-level output voltage 328
—V——DVDD2-0.5
IOH = –4 mADigital pin: EXDS1, EXDS2, EXADCLK, CLKO
V3OHHigh-level output voltage 327
—V0.5——
IOL = +2 mADigital pin: STO, SUBSW1, SUBSW2, MSUBSW, VD, HD
V2OLLow-level output voltage 226
—V——DVDD2-0.5
IOH = –2 mADigital pin: STO, SUBSW1, SUBSW2, MSUBSW, VD, HD
V2OHHigh-level output voltage 225
—V0.5——IOL = +2 mADigital pin: D0 to D11V1OLLow-level output voltage 124
—V——DRVDD-0.5
IOH = –2 mADigital pin: D0 to D11V1OHHigh-level output voltage 123
—kΩ110—10Digital pin: CLRRuPull-up resistance22
—kΩ110—10Digital pin: EXDS1, EXDS2, EXADCLKRd2Pull-down resistance 221
—kΩ110—10Digital pin: TEST1,TEST2, TEST3Rd1Pull-down resistance 120
—V0.8—VSS
Digital pin :TEST1, TEST2, TEST3, SSGSW, VD, HD, CS, DCLK, DATA, CLR, EXDS1, EXDS2, XI, EXADCLK, RESET
VDILLow-level digital input voltage19
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Limits
TypUnit
MaxNoteMin
ConditionsSymbolParameterB No.
Electrical Characteristics at AVDD1 = AVDD2 = DVDD1 = 1.8 V, DVDD2 = DVDD3 = DVDD4 = DRVDD = 3.0 V, VHH = 15.0 V, VH = 12.0 V, VL = –6.0 V, VMSUB = GND (continued)Note) Ta = 25°C±2°C unless otherwise specified.
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12SDB00165BEB
—Ω1 280——IOM1 = –1.0 mARONM2OVMiddle-level output ON resistance46
—Ω35——IOM1 = –10 mARONM1Middle-level output ON resistance38
—VVL + 0.1—VLIOL1 = 1 mAVOL1Low-level output voltage37
—VGND—GND –0.1IOM1 = –1 mAVOM1Middle-level output voltage36
V-driver (2-level output pins) OV2, OV4, OV6, OV8, OV10, OV12
—μA±5——VO = Hi-ZVHOLOutput leakage current35
—V0.5——IOL = +48 mADigital pin: H1, H2, H3, H4V6OLLow-level output voltage 634
—V——DVDD3-0.5
IOH = –48 mADigital pin: H1, H2, H3, H4V6OHHigh-level output voltage 633
—V0.5——IOL = +24 mADigital pin: R, HLV5OLLow-level output voltage 532
—V——DVDD4-0.5
IOH = –24 mADigital pin: R, HLV5OHHigh-level output voltage 531
—V0.5——IOL = +8 mADigital pin: SHUTV4OLLow-level output voltage 430
Digital inputs and outputs (continued)
—V——DVDD2-0.5
IOH = –8 mADigital pin: SHUTV4OHHigh-level output voltage 4
—Ω1 280——IOL1 = 1.0 mARONL2OVLow-level output ON resistance47
—VVL + 0.1—VLIOL1 = 0.1 mAVOL2OVLow-level output voltage45
—VGND—GND –0.1IOM1 = –0.1 mAVOM2OVMiddle-level output voltage44
V-driver (2-level output pins) OV9L, OV9R, OV11L, OV11R
—Ω60——IOL1 = 10 mARONL1OVLow-level output ON resistance43
—Ω60——IOM1 = –10 mARONM1OVMiddle-level output ON resistance42
—VVL + 0.1—VLIOL1 = 1 mAVOL1OVLow-level output voltage41
—VGND—GND –0.1IOM1 = –1 mAVOM1OVMiddle-level output voltage40
V-driver (2-level output pins) OV7S
—Ω35——IOL1 = 10 mARONL1Low-level output ON resistance39
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Limits
TypUnit
MaxNoteMin
ConditionsSymbolParameterB No.
Electrical Characteristics at AVDD1 = AVDD2 = DVDD1 = 1.8 V, DVDD2 = DVDD3 = DVDD4 = DRVDD = 3.0 V, VHH = 15.0 V, VH = 12.0 V, VL = –6.0 V, VMSUB = GND (continued)Note) Ta = 25°C±2°C unless otherwise specified.
Mainten
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tinued
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iscont
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includ
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four P
roduct
lifecyc
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(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
13SDB00165BEB
—Ω50——IOL3 = 10 mARONL3Low-level output ON resistance
—VVMSUB—VMSU
B – 0.1IOM3 = –1 mAVOM32Middle-level output voltage
—Ω35——IOM2 = –10 mARONM22Middle-level output ON resistance
—VVHH—VHH –0.1IOHH3 = –1 mAVOHH3High-level output voltage56
V-driver (SUB output pins) OSUB
—Ω35——IOL2 = 10 mARONL2Low-level output ON resistance55
54
—Ω35——IOM2 = 10 mARONM21Middle-level output ON resistance53
—Ω58——IOH2 = –10 mARONH2High-level output ON resistance52
—VVL + 0.1—VLIOL2 = 1 mAVOL2Low-level output voltage51
—VGND—GND –0.1IOM2 = –1 mAVOM22Middle-level output voltage50
—VGND + 0.1—GNDIOM2 = 1 mAVOM21Middle-level output voltage49
—VVH—VH –0.1IOH2 = –1 mAVOH2High-level output voltage48
63
—Ω40——IOM3 = –10 mARONM32Middle-level output ON resistance62
—Ω40——IOM3 = 10 mARONM31Middle-level output ON resistance61
—Ω78——IOHH3 = –10 mARONHH3High-level output ON resistance60
—VVL + 0.1—VLIOL3 = 1 mAVOL3Low-level output voltage59
58
—VVMSUB + 0.1—VMSU
BIOM3 = 1 mAVOM31Middle-level output voltage57
V-driver (3-level output pins) OV1A, OV1B, OV3A, OV3B, OV5A, OV5B, OV7A, OV7B, OV9A, OV9B, OV11A, OV11B
Limits
TypUnit
MaxNoteMin
ConditionsSymbolParameterB No.
Electrical Characteristics at AVDD1 = AVDD2 = DVDD1 = 1.8 V, DVDD2 = DVDD3 = DVDD4 = DRVDD = 3.0 V, VHH = 15.0 V, VH = 12.0 V, VL = –6.0 V, VMSUB = GND (continued)Note) Ta = 25°C±2°C unless otherwise specified.
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
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four P
roduct
lifecyc
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(planed
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ance ty
pe, main
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e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
14SDB00165BEB
TTML4Fall transition time
TPML4Fall propagation delay time82*ns10050—No load circuit
Low-level – Middle-levelTPLM4Rise propagation delay time81
V-driver (SUB output pin) OSUB
*ns1 000——Load circuit(VL = –7.5 V, VH = 9.5 V)TTHM3Fall transition time80
TTHM3Fall transition time79*ns650300—Load circuit
Middle-level – High-levelTTMH3Rise transition time78
TPHHL4Fall propagation delay time
TPMH3Rise propagation delay time
TTLM2Rise transition time70
TPML2Fall propagation delay time69*ns14070—No load circuit
Low-level – Middle-levelTPLM2Rise propagation delay time68
V-driver (2-level output pins) OV9L, OV9R, OV11L, OV11R
TTML1Fall transition time67*ns450170—Load circuit
Low-level – Middle-levelTTLM1Rise transition time66
TPML1Fall propagation delay time65*ns10050—No load circuit
Low-level – Middle-levelTPLM1Rise propagation delay time64
TTML3Fall transition time77*ns450170—Load circuit
Low-level – Middle-levelTTLM3Rise transition time76
*ns10050—No load circuitMiddle-level – High-levelTPHM3Fall propagation delay time75
74
TPML3Fall propagation delay time73*ns10050—No load circuit
Low-level – Middle-levelTPLM3Rise propagation delay time72
V-driver (3-level output pins) OV1A, OV1B, OV3A, OV3B, OV5A, OV5B, OV7A, OV7B, OV9A, OV9B, OV11A, OV11B
*ns450170—Load circuitLow-level – Middle-levelTTML2Fall transition time71
*ns800300—Load circuitLow-level – High-level
TTLHH4Rise transition time87
*
TTHHL4Fall transition time
86
88
*
ns800300—Load circuitLow-level – Middle-level
TTLM4Rise transition time
84
85
ns10050—No load circuitLow-level – High-level
TPLHH4Rise propagation delay time
V-driver (2-level output pins) OV2, OV4, OV6, OV8, OV10, OV12, OV7S
83
Limits
TypUnit
MaxNoteMin
ConditionsSymbolParameterB No.
Note) *: Stipulated at 10% to 90%.
Electrical Characteristics (Reference values for design) at AVDD1 = AVDD2 = DVDD1 = 1.8 V, DVDD2 = DVDD3 = DVDD4 = DRVDD = 3.0 V, VHH = 15.0 V, VH = 12.0 V, VL = –6.0 V, VMSUB = GNDNote) Ta = 25°C±2°C unless otherwise specified.
The characteristics listed below are reference values for design of the IC and are not guaranteed by inspection.If a problem does occur related to these characteristics, Panasonic will respond in good faith to user concerns.
Mainten
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Discon
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Mainten
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iscont
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includ
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four P
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lifecyc
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(planed
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planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
15SDB00165BEB
Technical Data1. Serial data control of AFE function block
1) AFE setting, ADRS: 000h to 00Eh
—
0000000h
—Reserved for test (Do not use.)—[7 : 0]
0031st HSEQ / CS0 (High)Timing core frequencyTCFRQ[9 : 8]
1st HSEQ / CS0 (High)Timing core currentTCCRT[11 : 10]
——Reserved for test (Do not use.)—[27 : 12]
1st HSEQ / CS0 (Valid)NCLP2 valid / invalid settingS_NENACP[25]
1st HSEQ / CS3 (16 pixels)Number of operated clamp pixels for high speed clampNCLP2[15 : 13]
1st HSEQ / CS4 (32 pixels)Number of operated clamp pixels for normal clampNCLP1[12 : 10]
1st HSEQ / CS0 (1VD)Number of averages of rear clamp(Valid at Mode 3, Mode 4)NCLPV[17 : 16]
—
1st HSEQ / CS
1st HSEQ / CS
1st HSEQ / CS
1st HSEQ / CS
1st HSEQ / CS
1st HSEQ / CS
1st HSEQ / CS
1st HSEQ / CS
1st HSEQ / CS
1st HSEQ / CS
1st HSEQ / CS
CS
1st HSEQ / CS
1st HSEQ / CS
1st HSEQ / CS
Latch timing
0000000h
00370AAh
00800E4h
0 (Normal)
0
0
0
3 (TBD MHz)
0 (Mode 1)
2 (16T)
5 (32HD)
2 (4HD)
0 (1 mA)
0 (Normal)
0 (Normal)
0 (Normal)
80h (128LSB)
039h (+2.011 dB)
0 (–2 dB)
Default
For test (Set to 0)
ADC control (The recommended setting value is informed later)
CDS control (The recommended setting value is informed later)
Impedance setting for black level
CDS bias current
Clamp mode setting
Operation time length of rear clamp
Number of averages at rear clamp
Number of averages at front clamp
A/D output drive capability
A/D output disable / enable
A/D output test mode
AFE power save mode
Output OB level
GCA gain
CDS gain
Description
—
ADCCTRL
CDSCTRL
RSW
CDSI
CLPMODE
CPLEN
NAVRR
NAVRF
OUTDRV
NOE
TESTMODE
POWERDOWN
OBLEVEL
GCAGAIN
GCDS
Code
Invalid
—
[27 : 25]
[24 : 22]
[21 : 20]
[19 : 18]
[9 : 8]
[7 : 6]
[5 : 3]
[2 : 0]
[27 : 26]
[24]
[23 : 22]
[22 : 20]
[19 : 12]
[11 : 2]
[1 : 0]
bit
004
005-00E
002
001
ADRS
Note) 1. The register (ADRS: 000h to 010h) is not be transferred continuously.2. The register indicated to be 1st HSEQ / CS can set the application timing in SLAT2 register.3. Do not write in data in test function register (ADRS: 003h, 004h).
Mainten
ance/
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tinued
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four P
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(planed
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pe, main
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e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
16SDB00165BEB
–2 dB (Default)00
0 dB10
1
1
bit 1
3 dB0
6 dB1
CDS gainbit 0
18.062 dB0000000001
36.053 dB0111111111
2.011 dB (Default)1001110000
1
0
0
0
bit 11
1
0
0
0
bit 10
1
0
0
0
bit 9
1
0
0
0
bit 8
1
0
0
0
bit 7
1
0
0
0
bit 6
1
0
0
0
bit 5
1
0
0
0
bit 4
0 dB00
0.035 dB10
1
1
bit 3
0.071 dB0
36.088 dB1
GCA gainbit 2
Ideal GCA gain (dB) = (20 log 64) × (N / 1 024)* Total gain = CDS gain (ADRS: 001h bit 0, bit 1 setting values) + GCA gain (ADRS: 001h bit 2 to bit 11 setting values)* The total gain is calculated based on A/D output with FS = 1 V[p-p].
GCDS (ADRS: 001h bit 1 to bit 0): CDS gain setting
GCAGAIN (ADRS: 001h bit 11 to bit 2): GCA gain setting
OBLEVEL (ADRS: 001h bit 19 to bit 12): Output OB level setting
Technical Data (continued)1. Serial data control of AFE function block (continued)
2) AFE registers
1
0
0
0
1
0
bit 12
1
1
0
1
0
0
bit 13
1
1
0
0
0
0
bit 14
1
1
0
0
0
0
bit 15
1
1
0
0
0
0
bit 16
1
1
0
0
0
0
bit 17
1
1
0
0
0
0
bit 18
1
1
1
0
0
0
bit 19
128 LSB (Default)
254 LSB
0 LSB
1 LSB
2 LSB
255 LSB
OB level
Mainten
ance/
Discon
tinued
Mainten
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iscont
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owing
four P
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(planed
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e type,
planed
discon
tinued
typed,
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tinued
type)
NN12081A
17SDB00165BEB
POWERDOWN (ADRS: 001h bit 21 to bit 20): AFE power save mode setting
Normal00
10
1
1
bit 21
Stand-by0
Power down1
Modebit 20
Normal0
Hi-Z1
Modebit 24
Normal00
Test signal 1 (Code of OBLEVEL register)10
1
1
bit 23
Test signal 2 (D11 to D0 = AAAh)0
Test signal 3 (D11 to D0 = 555h)1
Modebit 22
NOE (ADRS: 001h bit 24): A/D output disable / enable setting
TESTMODE (ADRS: 001h bit 23 to bit 22): A/D output test mode
Technical Data (continued)1. Serial data control of AFE function block (continued)
2) AFE registers (continued)
1 mA00
2 mA10
1
1
bit 27
3 mA0
4 mA1
Drive capabilitybit 26
OUTDRV (ADRS: 001h bit 27 to bit 26): A/D output drive capability
CDSI [3]
CDSI [2]
CDSI [1]
CDSI [0]
Mode
up to TBD MHz
up to TBD MHz
up to TBD MHz
up to TBD MHz
Reference value
00
10
1
1
bit 19
0
1
bit 18
CDSI (ADRS: 002h bit 19 to bit 18): Inside bias current setting for CDS
RSW (ADRS: 002h bit 21 to bit 20): Impedance setting for black levelNote) Please set this register to "0".
RSW [0]00
RSW [1]10
1
1
bit 21
RSW [2]0
RSW [3]1
Drive capabilitybit 20
S_NENACP (ADRS:001h bit25): NCLP2 Valid / Invalid setting
NCLP2 (ADRS: 002h bit15 to 13) Invalid
NCLP2 (ADRS: 002h bit15 to 13) Valid0
1
Modebit 25
Mainten
ance/
Discon
tinued
Mainten
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iscont
inued
includ
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owing
four P
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lifecyc
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e.
(planed
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planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
18SDB00165BEB
NCLAMP (ADRS: 002h bit 7 to bit 0): Clamp loop constant
Mode 4(Recommended at narrow CPOB width)
Mode 3(Recommended at narrow CPOB width)
Mode 2
Mode 1 (Default)
Mode
Front: 1HDRear: 1VD
Front: 1HDRear: 1VD
1HD
1HD
Operated cycle
PBLK
PBLK
After the CPOB
PBLK
Clamp timing
NCLP1 (bit 12 to bit 10) setting period11
CPOB width period00
NCLP1 (bit 12 to bit 10) setting period10
1
bit 9
32 pixels from the front edge of CPOB0
Number of operated pixelsbit 8
Note) Do not write in data in test function register (ADRS: 003h, 004h).
8T10
16T (Default)01
1
0
bit 7
4T0
32T1
Mode (CPLEN)Operation time
length of front clampbit 6
8HD110
4HD010
2HD100
1HD000
1
1
0
0
bit4
32HD (Default)
11
01
1
1
bit 5
16HD0
1
Mode (NAVRR)Number of averages
at rear clampbit 3
32 pixels (Default)Don't care
Don't care1
16 pixels110
1
0
0
bit 11
2 pixels00
4 pixels10
0
bit 12
8 pixels0
NCLP1 : Valid at Mode 2, Mode 4Number of operated pixelsbit 10
CLPMODE (ADRS: 002h bit 9 to bit 8): Clamp mode setting
NCLP1 (ADRS: 002h bit 12 to bit 10): Number of operated pixels for normal clamp
Technical Data (continued)1. Serial data control of AFE function block (continued)
2) AFE registers (continued)
8HD110
4HD (Default)010
2HD100
1HD000
1
1
0
0
bit1
32HD
11
01
1
1
bit 2
16HD0
1
Mode (NAVRF)Number of averages
at front clampbit 0
8VD11
1
0
0
bit 17
1VD (Default)0
2VD1
4VD0
NCLPV: Valid at Mode 3, Mode 4Number of averagesbit 16
NCLPV (ADRS: 002h, bit 17, bit 16):Number of averages of rear clamp
32 pixelsDon't careDon't care1
16 pixels (Default)110
1
0
0
bit 14
2 pixels00
4 pixels10
0
bit 15
8 pixels0
Number of operated pixelsbit 13
It sets up the operation period of high-speed pull-in CPOB clampset in ADRS 024h. Set the value lower than the high-speed pull-in CPOB width (ACPWD: ADRS 024h, bit 23). Setting S_NENACP(ADRS: 001h, bit 25) = "1" makes this function invalid and makes NCLP1 (ADRS: 002h, bit 12 to bi10) valid in the operation mode of high-speed pull-in CPOB clamp as well as the normal CPOB clamp.
NCLP2 (ADRS: 002h, bit 15 to bit 13):Number of operated pixels for high speed clampMain
tenan
ce/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
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(planed
mainten
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pe, main
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e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
19SDB00165BEB
CS2-bitRatio of dividing frequency between master clock and internal operating clockFCKSEL[19 : 18]
CS1-bitSSG synchronous clock switchSYNCSEL[26]
CSVDWD + 1 to 4 095Default VD period setting of inside SSG(Default 16HD)VDINIT[11 : 0]
—00FCSHDWD × 64 + 1
to 16 383Default HD period setting of inside SSG(Default 256T)HDINIT[25 : 12]
1st HSEQ6-bit × 4Mode register 1MODE1[23 : 0]—011
1st HSEQ6-bit × 4Mode register 2MODE2[23 : 0]—012
CS1-bitHD/VD output phase 180° to CLKOHVPHASE[13]
1st HSEQ / CS12-bitCH pulse inhibitCHDEL[27 : 16]
CS1-bitTiming core resetTCRST[23]
CS1-bitSerial data transfer methodSLAT1[20]
CS1-bitFCK resetFCKRST[22]
1st HSEQ / CS6-bitInternal SSG mode VD width (1H steps)VDWD[5 : 0]
—013
1st HSEQ / CS6-bitInternal SSG mode HD width (64T steps)HDWD[11 : 6]
CS1-bitHD/VD polarityHVPOL[12]
CS1-bitSSG resetSSGRST[25]
1-bit
1-bit
1-bit
2-bit
3-bit
Range
CSSerial data application timingSLAT2[21]
CSSoftware resetSOFTRST[24]
CSTG output enableENTGOUT[27]
CSPower savePWSV[2 : 0]
—010
CSMonitor pin controlEXOUT[4 : 3]
Latch timingDescriptionCodebit(SRAM)ADRS
Note) 1. The register (ADRS: 000h to 010h) is not be transferred continuously.2. The register indicated to be 1st HSEQ / CS can set the application timing in SLAT2 register.
ADRS: 00Fh to 013h
Technical Data (continued)2. Serial data control of timing generator block
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
20SDB00165BEB
CS1-bitReverse transfer delay 0.5T stepsHLBLK[23]
CS4-bitReverse transfer delay 0.5T stepsREVDLY[27 : 24]
CS4-bitH1 drive capabilityH1DRV[3 : 0]
—014
CS4-bitH2 drive capabilityH2DRV[7 : 4]
CS4-bitH3 drive capabilityH3DRV[11 : 8]
CS4-bitH4 drive capabilityH4DRV[15 : 12]
CS3-bitHL drive capabilityHLDRV[18 : 16]
CS3-bitR drive capabilityRDRV[22 : 20]
CS6-bitH1 ↑ phaseH1RISE[5 : 0]
—015CS6-bitH1 ↓ phaseH1FALL[11 : 6]
CS6-bitH2 ↑ phaseH2RISE[17 : 12]
CS6-bitH2 ↓ phaseH2FALL[23 : 18]
CS6-bitH3 ↑ phaseH3RISE[5 : 0]
—016CS6-bitH3 ↓ phaseH3FALL[11 : 6]
CS6-bitH4 ↑ phaseH4RISE[17 : 12]
CS6-bitH4 ↓ phaseH4FALL[23 : 18]
CS6-bitHL ↑ phaseHLRISE[5 : 0]
—017CS6-bitHL ↓ phaseHLFALL[11 : 6]
CS6-bitR ↑ phaseRRISE[17 : 12]
CS6-bitR ↓ phaseRFALL[23 : 18]
CS6-bitDS1 ↑ phaseDS1RISE[5 : 0]
—018CS6-bitDS1 ↓ phaseDS1FALL[11 : 6]
CS6-bitDS2 ↑ phaseDS2RISE[17 : 12]
CS6-bitDS2 ↓ phaseDS2FALL[23 : 18]
CS6-bitADCLK ↑ phaseADCRISE[5 : 0]
—019CS6-bitADCLK ↓ phaseADCFALL[11 : 6]
Range Latch timingDescriptionCodebit(SRAM)ADRS
ADRS: 014h to 019h
Technical Data (continued)2. Serial data control of timing generator block (continued)
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
21SDB00165BEB
1st HSEQ / CS1 to 4 0951st MSUBSW toggle lineMSUBSW_LN1[11 : 0]—02B1st HSEQ / CS8 to 16 3831st MSUBSW toggle positionMSUBSW_TOG1[25 : 12]—1st HSEQ / CS1 to 4 0952nd MSUBSW toggle lineMSUBSW_LN2[11 : 0]—02C1st HSEQ / CS8 to 16 3832nd MSUBSW toggle positionMSUBSW_TOG2[25 : 12]—1st HSEQ / CS1-bitSUBCNT toggle linked CH enableSUBCNTSPEN[0]—02D1st HSEQ / CS0 to 63SUBCNT fall timing linked CHSUBCNTSPT1[6 : 1]—1st HSEQ / CS0 to 63SUBCNT rise timing linked CHSUBCNTSPT2[12 : 7]—
1st HSEQ / CS1 to 4 0952nd SUBSW2 toggle lineSUBSW2_LN2[11 : 0]—02A1st HSEQ / CS8 to 16 3832nd SUBSW2 toggle positionSUBSW2_TOG2[25 : 12]—
1st HSEQ / CS8 to 16 3831st SUBSW2 toggle positionSUBSW2_TOG1[25 : 12]—
——Don’t care—[25 : 24]—
—1 to 127High-speed pull-in CPOB stepsNACPOUT[22 : 16]——1-bitHigh-speed pull-in CPOB widthACPWD[23]—
1st HSEQ / CS1-bitMSUBSW polarityMSUBPOL[18]—
Invalid (These register are skipped at SLAT1 = 0.)02E to 040——Don’t care—[27 : 26]—
1st HSEQ / CS1 to 4 0951st SUBSW2 toggle lineSUBSW2_LN1[11 : 0]—029
1st HSEQ / CS1-bitSHUT polaritySHUTPOL[16]—1st HSEQ / CS16-bitTrigger enableTRGEN[15 : 0]—01A
1st HSEQ / CS1 to 4 0954th SUBSW1 toggle lineSUBSW1_LN4[11 : 0]—0281st HSEQ / CS8 to 16 3834th SUBSW1 toggle positionSUBSW1_TOG4[25 : 12]—
1st HSEQ / CS1 to 4 0951st SHUT toggle lineSHUTLN1[11 : 0]—0201st HSEQ / CS8 to 16 3831st SHUT toggle positionSHUTTOG1[25 : 12]—1st HSEQ / CS1 to 4 0952nd SHUT toggle lineSHUTLN2[11 : 0]—0211st HSEQ / CS8 to 16 3832nd SHUT toggle positionSHUTTOG2[25 : 12]—
8 to 16 3831 to 4 0958 to 16 3831 to 4 0958 to 16 3831 to 4 095
1 to 151 to 4 0958 to 16 3831 to 4 0958 to 16 3831 to 4 095
8 to 16 3831 to 4 0958 to 16 3831 to 4 0951 to 16 3838 to 16 3831 to 16 3838 to 16 3831 to 4 0951 to 4 095
1-bit
Range
1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS
1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS
1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS1st HSEQ / CS
1st HSEQ / CS
Latch timing
SUB toggle position 2 (Last line)SUBTOG2[13 : 0]—01DSUB width 2 (Last line)SUBWD2[27 : 14]—
2nd SUBSW1 toggle lineSUBSW1_LN2[11 : 0]—0262nd SUBSW1 toggle positionSUBSW1_TOG2[25 : 12]—3rd SUBSW1 toggle lineSUBSW1_LN3[11 : 0]—0273rd SUBSW1 toggle positionSUBSW1_TOG3[25 : 12]—
High-speed pull-in CPOB output lineACPLN[11 : 0]—024Number of lines of high-speed pull-in CPOB outputNACPLN[15 : 12]—
1st SUBSW1 toggle lineSUBSW1_LN1[11 : 0]—0251st SUBSW1 toggle positionSUBSW1_TOG1[25 : 12]—
1st STO toggle lineSTOLN1[11 : 0]—0221st STO toggle positionSTOTOG1[25 : 12]—2nd STO toggle lineSTOLN2[11 : 0]—0232nd STO toggle positionSTOTOG2[25 : 12]—
1st SUBCNT toggle lineSUBCNTLN1[11 : 0]—01E1st SUBCNT toggle positionSUBCNTTOG1[25 : 12]—2nd SUBCNT toggle lineSUBCNTLN2[11 : 0]—01F2nd SUBCNT toggle positionSUBCNTTOG2[25 : 12]—
SUB toggle position 1SUBTOG1[13 : 0]—01CSUB width 1SUBWD1[27 : 14]—
STO polaritySTOPOL[17]—
SUB output start lineSUBON[11 : 0]—01BNumber of SUB output linesNSUBOUT[23 : 12]—
DescriptionCodebit(SRAM)ADRS
ADRS: 01Ah to 040h
Technical Data (continued)2. Serial data control of timing generator block (continued)
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
22SDB00165BEB
ADRS: 041h to 100h
Technical Data (continued)2. Serial data control of timing generator block (continued)
CS2-bitPAT#1 pattern type (00 : VPAT, 01: HPAT, 1X: CHPAT)VHTYP1[10 : 9]—
Invalid (These register are skipped at SLAT1 = 0.)080 to 10F
——————07F
CS0 to 255Number of PAT#1 stepsNSTEP1[7 : 0][ADRS1]041
CS1-bitPAT#1 pattern type (Step width: 0 = fixed, 1 = variable)PTYP1[8]—
↓
8-bit
Range
CSPAT#1 ADRS[ADRS1]——
Latch timingDescriptionCodebit(SRAM)ADRS
17-bitVPAT#2 output pulse polarity (n + 1)VPOL (n + 1)[16 : 0][+n]
0 to 1 023VPAT#2 STEP width (n + 1)VSTEP (n + 1)[27 : 18]
6-bitVPAT#1 output pulse polarity ((n + 1) × 3 / 2)VPOL ( (n + 1) × 3/2)[5 : 0][+ (n + 1) (even) ]
11-bitVPAT#1 output pulse polarity ((n + 1) × 3 / 2)VPOL ( (n + 1) × 3/2)[27 : 17]
17-bitVPAT#1 output pulse polarity ((n + 1) × 3 / 2 + 1)VPOL ( (n + 1) × 3/2 + 1 )[22 : 6]
↓
17-bitVPAT#2 output pulse polarity 1VPOL(1)[16 : 0][ADRS2]
0 to 1 023VPAT#2 STEP width 1VSTEP(1)[27 : 18]
17-bitVPAT#2 output pulse polarity 2VPOL(2)[16 : 0][+1]
0 to 1 023VPAT#2 STEP width 2VSTEP(2)[27 : 18]
17-bitVPAT#2 output pulse polarity 3VPOL(3)[16 : 0][+2]
0 to 1 023VPAT#2 STEP width 3VSTEP(3)[27 : 18]
17-bitVPAT#1 output pulse polarity 1VPOL(1)[16 : 0][ADRS1]
0 to 1 023VPAT#1 STEP widthVSTEP[27 : 18]
17-bitVPAT#1 output pulse polarity 2VPOL(2)[16 : 0][+1]
11-bitVPAT#1 output pulse polarity 3 (11-bit)VPOL(3)[27 : 17]
6-bitVPAT#1 output pulse polarity 3 (6-bit)VPOL(3)[5 : 0][+2]
17-bitVPAT#1 output pulse polarity 4VPOL(4)[22 : 6]
↓
17-bitVPAT#1 output pulse polarity ((n + 1) × 3 / 2 – 1)VPOL ( (n + 1) × 3/2 – 1)[16 : 0][+ n (odd) ]
RangeDescriptionCodebit(Pattern RAM)
VPAT / HPAT / CHPAT register
V-Pattern setting
Step width fixed patternPTYP = 0
Step width variable patternPTYP = 1
Note) Overwrite at the time of rewriting.
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
23SDB00165BEB
Technical Data (continued)2. Serial data control of timing generator block (continued)
1 to 15Number of HPAT#2 toggles (n + 1)NHTOG (n + 1)[21 : 18]
1 to 15HPAT#2 toggle width (n + 1)HSTEP (n + 1)[17 : 14]
1-bitHPAT#2 reverse transfer ON/OFF (n + 1)ENREV (n + 1)[27]
HON (n) + 3 to 16 383HPAT#2 toggle position (n + 1)HON (n + 1)[13 : 0][+n]
HON (2n) + 3 to 16 383HPAT#1 toggle position (n × 2 + 1)HON (2n + 1)[27 : 14]
↓
HON (2n – 1) + 3 to 16 383HPAT#1 toggle position (n × 2)HON (2n)[13 : 0][+n]
PBLKON + 9 to 16 383HPAT#1 toggle position 1HON(1)[13 : 0][ADRS1]
1 to 15HPAT#1 toggle width 1HSTEP[17 : 14]
1 to 15Number of HPAT#1 toggles 1NHTOG[21 : 18]
1bitHPAT#1 Reverse transfer mode ON/OFF 1ENREV[27]
HON1 + 3 to 16 383HPAT#1 toggle position 2HON(2)[13 : 0][+1]
HON2 + 3 to 16 383HPAT#1 toggle position 3HON(3)[27 : 14]
HON3 + 3 to 16 383HPAT#1 toggle position 4HON(4)[13 : 0][+2]
HON4 + 3 to 16 383HPAT#1 toggle position 5HON(5)[27 : 14]
↓
HON1 + 3 to 16 383HPAT#2 toggle position 2HON(2)[13 : 0][+1]
1 to 15HPAT#2 toggle width 2HSTEP(2)[17 : 14]
1 to 15Number of HPAT#2 toggles 2NHTOG(2)[21 : 18]
1-bitHPAT#2 reverse transfer ON/OFF 2ENREV(2)[27]
1 to 15HPAT#2 toggle width 1HSTEP(1)[17 : 14]
1-bit
1 to 15
PBLKON + 9 to 16 383
Range
HPAT#2 reverse transfer ON/OFF 1ENREV(1)[27]
HPAT#2 toggle position 1HON(1)[13 : 0][ADRS2]
Number of HPAT#2 toggles 1NHTOG(1)[21 : 18]
DescriptionCodebit(Pattern RAM)
H-pattern setting
Step width fixed patternPTYP = 0
Step width variable patternPTYP = 1
Note) 1. Overwrite at the time of rewriting.2. The data can be distinguished any of HPAT, VPAT or CHPAT in VHPAT setting when it is written in the registers. However, it is necessary to
set up the pattern ID correctly in HSEQ register because this VHPAT setting is not recognized while operating.
Mainten
ance/
Discon
tinued
Mainten
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iscont
inued
includ
es foll
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four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
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e type,
planed
discon
tinued
typed,
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tinued
type)
NN12081A
24SDB00165BEB
CHPAT registerThe data in these registers is applied by MODE register (ADRS 011h, 012h) setting or VD. When the data can be changed, the MODE register should be set before 1HD in 1st HSEQ. Then the data is applied from this 1st HSEQ. When the data can be changed but the MODE register cannot be set, the data will be applied in the next VD.
Technical Data (continued)2. Serial data control of timing generator block (continued)
12-bitCHPAT#1 output pulse polarity (n + 1)CHPOL (n + 1)[11 : 0][+n]
0 to 1 023CHPAT#1 STEP width (n + 1)CHSTEP (n + 1)[27 : 18]
↓
12-bitCHPAT#1 output pulse polarity 1CHPOL(1)[11 : 0][ADRS1]
0 to 1 023CHPAT#1 STEP width 1CHSTEP(1)[27 : 18]
12-bitCHPAT#1 output pulse polarity 2CHPOL(2)[11 : 0][+1]
0 to 1 023CHPAT#1 STEP width 2CHSTEP(2)[27 : 18]
12-bitCHPAT#1 output pulse polarity 3CHPOL(3)[11 : 0][+2]
0 to 1 023CHPAT#1 STEP width 3CHSTEP(3)[27 : 18]
RangeDescriptionCodebit(Pattern RAM)
Step width variable patternPTYP = X(Regardless of the PTYP setting)
Note) Overwrite at the time of rewriting.
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
25SDB00165BEB
The data in these registers is latched at 4T after 28-bit in the data block is transferred, and the data is applied from the HSEQ after 2HD.
HSEQ register
Technical Data (continued)2. Serial data control of timing generator block (continued)
Note) *: When the serial data is transfer, it is latched at CS ↑ and the data is applied from next HSEQ.
—6-bitHSEQ#1 5th VPAT IDVIDE1[23:18]
HSEQ *HSEQ#1 1st to 9th VPAT setting(See the next page.)[27 : 0]
015 to
01D
115 to
11D
—4-bit——[27 : 24]
—4-bit——[27 : 24]
—0 to 255HSEQ#1 CPOB widthCPOBWD1[21 : 14]
—4-bitNumber of HSEQ#1 HPAT repeatsHRPTA1[16 : 13]
—0 to 255HSEQ#1 HD multi-cycle settingNMULT1[21 : 14]
—6-bitHSEQ#1 HPAT IDHIDA1[27 : 22]
HSEQ *0 to 8 191HSEQ#1 PBLK ON positionPBLKON1[12 : 0]01E11E
—0 to 16 383HSEQ#1 PBLK OFF positionPBLKOFF1[27 : 14]
HSEQ *0 to 8 191HSEQ#1 CPOB ON positionCPOBON1[12 : 0]01F11F
—6-bitHSEQ#1 7th VPAT IDVIDG1[11 : 6]
—6-bitHSEQ#1 9th VPAT IDVIDI1[23 : 18]
—6-bitHSEQ#1 4th VPAT IDVIDD1[17:12]
—6-bitHSEQ#1 3rd VPAT IDVIDC1[11:6]
—13-bit (0 to 8 191)HSEQ#1 H-transfer period (HD)HWD1[12 : 0]012112
HSEQ *14-bitHSEQ#1 HPAT repeat cycleHPLENA1[13 : 0]011111
—14-bit (0 to 16 383)HSEQ#1 H-transfer ON position (T)HON1[27 : 14]
—6-bitHSEQ#1 1st VPAT IDVIDA1[22 : 17]
—5-bit——[27 : 23]
6-bit
6-bit
6-bit
0 to 16 383
Range
—
HSEQ *
HSEQ *
HSEQ *
Latch timing
HSEQ#1 HD periodHLEN1[13 : 0]010110
HSEQ#1 2nd VPAT IDVIDB1[5 : 0]013113
HSEQ#1 6th VPAT IDVIDF1[5 : 0]014114
HSEQ#1 8th VPAT IDVIDH1[17 : 12]
DescriptionCodebitSRAMADRS(hex)
UserADRS(hex)
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
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e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
26SDB00165BEB
The data in these registers is latched at 4T after 28-bit in the data block is transferred, and the data is applied from the HSEQ after 2HD.
HSEQ register (continued)
Technical Data (continued)2. Serial data control of timing generator block (continued)
Note) *: When the serial data is transfer, it is latched at CS ↑ and the data is applied from next HSEQ.
—0 to 4 095Number of HSEQ#1 8th VPAT repeatsVRPTH1[27 : 16]
—0 to 3HSEQ#1 8th VPAT start lineVPSTLNH1[15 : 14]
HSEQ *0 to 16 383HSEQ#1 8th VPAT positionVPOSH1[13 : 0]01C11C
HSEQ *0 to 16 383HSEQ#1 9th VPAT positionVPOSI1[13 : 0]01D11D
—0 to 4 095Number of HSEQ#1 7th VPAT repeatsVRPTG1[27 : 16]
—0 to 3HSEQ#1 7th VPAT start lineVPSTLNG1[15 : 14]
HSEQ *0 to 16 383HSEQ#1 7th VPAT positionVPOSG1[13 : 0]01B11B
—0 to 3HSEQ#1 9th VPAT start lineVPSTLNI1[15 : 14]
—0 to 3HSEQ#1 6th VPAT start lineVPSTLNF1[15 : 14]
HSEQ *0 to 16 383HSEQ#1 6th VPAT positionVPOSF1[13 : 0]01A11A
—0 to 4 095Number of HSEQ#1 9th VPAT repeatsVRPTI1[27 : 16]
—0 to 4 095Number of HSEQ#1 6th VPAT repeatsVRPTF1[27 : 16]
—0 to 4 095Number of HSEQ#1 1st VPAT repeatsVRPTA1[27 : 16]
—0 to 3HSEQ#1 1st VPAT start lineVPSTLNA1[15 : 14]
HSEQ *0 to 16 383HSEQ#1 2nd VPAT positionVPOSB1[13 : 0]016116
HSEQ *0 to 16 383HSEQ#1 1st VPAT positionVPOSA1[13 : 0]015115
—0 to 4 095Number of HSEQ#1 5th VPAT repeatsVRPTE1[27 : 16]
0 to 3
0 to 16 383
0 to 4 095
0 to 3
0 to 16 383
0 to 4 095
0 to 3
0 to 16 383
0 to 4 095
0 to 3
Range
—
HSEQ *
—
—
HSEQ *
—
—
HSEQ *
—
—
Latch timing
HSEQ#1 5th VPAT positionVPOSE1[13 : 0]019119
HSEQ#1 5th VPAT start lineVPSTLNE1[15 : 14]
HSEQ#1 4th VPAT start lineVPSTLND1[15 : 14]
Number of HSEQ#1 4th VPAT repeatsVRPTD1[27 : 16]
HSEQ#1 3rd VPAT positionVPOSC1[13 : 0]017117
HSEQ#1 3rd VPAT start lineVPSTLNC1[15 : 14]
HSEQ#1 2nd VPAT start lineVPSTLNB1[15 : 14]
Number of HSEQ#1 2nd VPAT repeatsVRPTB1[27 : 16]
Number of HSEQ#1 3rd VPAT repeatsVRPTC1[27 : 16]
HSEQ#1 4th VPAT positionVPOSD1[13 : 0]018118
DescriptionCodebitSRAMADRS(hex)
UserADRS(hex)
• ADRS: 115h to 11Dh: 1st to 9th VPAT setting
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
27SDB00165BEB
Technical Data (continued)2. Serial data control of timing generator block (continued)
—0 to 16 383VSEQ#2 2nd CHPAT start timing (T)CHPOSB2[27 : 14]
VSEQ *0 to 16 383VSEQ#2 1st CHPAT start timing (T)CHPOSA2[13 : 0]022122
—0 to 4 095VSEQ#2 2nd CPOB output periodVCPLNB2[23 : 12]
VSEQ *0 to 4 095VSEQ#2 2nd CPOB output start lineVCPONB2[11 : 0]02F12F
—4-bit——[27 : 24]
—0 to 4 095VSEQ#2 1st CPOB output periodVCPLN2[23 : 12]
VSEQ *0 to 2 047VSEQ#2 1st CPOB output start lineVCPON2[10 : 0]02E12E
—4-bit——[27 : 24]
—0 to 4 095VSEQ#2 2nd VBLK OFF periodVBLKLNB2[23 : 12]
VSEQ *0 to 4 095VSEQ#2 2nd VBLK OFF position (Valid start line)VBLKOFFB2[11 : 0]02D12D
—4-bit——[27 : 24]
—4-bit——[27 : 24]
—5-bit——[27 : 23]
VSEQ *0 to 2 047VSEQ#2 1st VBLK OFF position (Valid start line)VBLKOFF2[10 : 0]02C12C
—0 to 4 095VSEQ#2 1st VBLK OFF periodVBLKLN2[23 : 12]
—4-bit——[27 : 24]
25-bit
0 to 4 095
6-bit
6-bit
0 to 2 047
0 to 4 095
Range
VSEQ *VSEQ#2 1st to 9th HSEQ setting(See the next page.)
[24 : 0]023 to02B
123 to12B
VSEQ *VSEQ#2 1st CHPAT IDCHIDA2[5 : 0]021121
—VSEQ#2 2nd CHPAT IDCHIDB2[11 : 6]
—VSEQ#2 1st CHPAT start line (HSTART basis)CHSTLN2[23 : 12]
VSEQ *VSEQ#2 VD periodVLEN2[11 : 0]020120
—VSEQ#2 1st HSEQ start positionHSTART2[22 : 12]
Latch timingDescriptionCodebitSRAM ADRS
User ADRS
Ex.) When ADRS: 120h to 12Fh (ID = 2) is assigned to VSEQVSEQ register
Note) *: When the serial data is transferred, the data in these registers is latched in pattern memory at 3T after 28-bit in the data block is transferred. And it is applied from VSEQ which is changed before or after HSTART-1HD.
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
28SDB00165BEB
VSEQ *6-bitVSEQ#2 9th HSEQ ID (ODD)HSIDOI2[5 : 0]02B12B
—6-bitVSEQ#2 9th HSEQ ID (EVEN)HSIDEI2[11 : 6]—0 to 4 095Number of VSEQ#2 9th HSEQ linesHSLNI2[23 : 12]—1-bitVSEQ#2 9th HSEQ blanking settingHSBLKI2[24]—3-bit——[27 : 25]
—3-bit——[27 : 25]—1-bitVSEQ#2 7th HSEQ blanking settingHSBLKG2[24]—0 to 4 095Number of VSEQ#2 7th HSEQ linesHSLNG2[23 : 12]—6-bitVSEQ#2 7th HSEQ ID (EVEN)HSIDEG2[11 : 6]
VSEQ *6-bitVSEQ#2 7th HSEQ ID (ODD)HSIDOG2[5 : 0]029129
—3-bit——[27 : 25]
—3-bit——[27 : 25]
—3-bit——[27 : 25]
—3-bit——[27 : 25]
—3-bit——[27 : 25]
—1-bitVSEQ#2 6th HSEQ blanking settingHSBLKF2[24]
—1-bitVSEQ#2 5th HSEQ blanking settingHSBLKE2[24]
—1-bitVSEQ#2 4th HSEQ blanking settingHSBLKD2[24]
—1-bitVSEQ#2 3rd HSEQ blanking settingHSBLKC2[24]
—1-bitVSEQ#2 2nd HSEQ blanking settingHSBLKB2[24]
—1-bitVSEQ#2 1st HSEQ blanking settingHSBLKA2[24]
—6-bitVSEQ#2 6th HSEQ ID (EVEN)HSIDEF2[11 : 6]VSEQ *6-bitVSEQ#2 6th HSEQ ID (ODD)HSIDOF2[5 : 0]028128
—0 to 4 095Number of VSEQ#2 6th HSEQ linesHSLNF2[23 : 12]
3-bit1-bit0 to 4 0956-bit6-bit
3-bit
0 to 4 0956-bit6-bit
0 to 4 0956-bit6-bit
0 to 4 0956-bit6-bit
0 to 4 0956-bit6-bit
0 to 4 0956-bit6-bit
Range
—Number of VSEQ#2 8th HSEQ linesHSLNH2[23 : 12]—VSEQ#2 8th HSEQ blanking settingHSBLKH2[24]———[27 : 25]
VSEQ *VSEQ#2 5th HSEQ ID (ODD)HSIDOE2[5 : 0]027127—VSEQ#2 5th HSEQ ID (EVEN)HSIDEE2[11 : 6]—Number of VSEQ#2 5th HSEQ linesHSLNE2[23 : 12]
VSEQ *VSEQ#2 4th HSEQ ID (ODD)HSIDOD2[5 : 0]026126—VSEQ#2 4th HSEQ ID (EVEN)HSIDED2[11 : 6]—Number of VSEQ#2 4th HSEQ linesHSLND2[23 : 12]
VSEQ *VSEQ#2 3rd HSEQ ID (ODD)HSIDOC2[5 : 0]025125—VSEQ#2 3rd HSEQ ID (EVEN)HSIDEC2[11 : 6]—Number of VSEQ#2 3rd HSEQ linesHSLNC2[23 : 12]
VSEQ *VSEQ#2 2nd HSEQ ID (ODD)HSIDOB2[5 : 0]024124—VSEQ#2 2nd HSEQ ID (EVEN)HSIDEB2[11 : 6]—Number of VSEQ#2 2nd HSEQ linesHSLNB2[23 : 12]
VSEQ *VSEQ#2 1st HSEQ ID (ODD)HSIDOA2[5 : 0]023123—VSEQ#2 1st HSEQ ID (EVEN)HSIDEA2[11 : 6]—Number of VSEQ#2 1st HSEQ linesHSLNA2[23 : 12]
———[27 : 25]
VSEQ *VSEQ#2 8th HSEQ ID (ODD)HSIDOH2[5 : 0]02A12A—VSEQ#2 8th HSEQ ID (EVEN)HSIDEH2[11 : 6]
Latch timingDescriptionCodebitSRAM ADRSUser ADRS
Technical Data (continued)2. Serial data control of timing generator block (continued)
• ADRS: 123h to 12Bh: 1st to 9th HSEQ settingVSEQ register (continued)
Note) *: When the serial data is transferred, the data in these registers is latched in pattern memory at 3T after 28-bit in the data block is transferred. And it is applied from VSEQ which is changed before or after HSTART-1HD.
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
29SDB00165BEB
tOD
Note) The above values are reference values for designing and not guaranteed.
——1.2—tAD_s1ns—7.3—tOD
ns——6tDS2_w2
ns——6tDS1_w124.6
Min
ns——tcp
UnitMaxTypSymbol
CCDOUT
DS1
DS2
D11 to D0
ADCLK
D11 to D0
ADCLK(at ADCRISE = 0)
CLKO
tAD
The timing at default state istAD: CLKO ↑ to ADCLK ↑ = 22 × T/48 (T = 1/fck)
The data output timing can be set by the built-in clock generator in (1/48)T steps.
Technical Data (continued)3. Recommended pulse timing and signal processing flow
tODtAD_s1
N N + 1 N + 2 N + 3 N + 9 N + 10 N + 11
tcp
tDS1_w1
tDS2_w2
1 2 93 1110
N – 1 N N + 1N – 10 N – 9 N – 8
8
N – 2N – 11 N – 7
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
30SDB00165BEB
1) OverviewV-driver is controlled by RESET pin and the internal input pulses of the built-in timing generator.
2) Function table
Technical Data (continued)4. Function tables of V-driver block
(3) SUB driver block(1) Input block
VLVMLow
xxHigh
OSUBOVxxRESET
High
VHHLow
Low
VMSUBHighLow
VLHigh
OSUBSUBCNTSUB
(2) Vertical driver block
<2-level transfer pulse signals> <3-level transfer pulse signals>
OV6V6
OV12V12
OV10V10
OV8V8
OV4V4
GNDLow
VLHigh
V2 OV2
GNDLow
VLHighHigh
OV11BCH12CH12
OV11AV11
CH11CH11
Low
High
V9
V7
V5
V3
V1
OV9ACH9CH9
OV7BCH8CH8
OV7ACH7CH7
OV5ACH5CH5
OV3BCH4CH4
OV3ACH3CH3
OV1BCH2CH2
OV9BCH10CH10
OV5BCH6CH6
CH1
Low
CH1
VH
VL
OV1A
OV9RV9R
OV11RV11R
OV11LV11L
OV9LV9L
GNDLow
VLHigh
V7S OV7SMain
tenan
ce/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
31SDB00165BEB
SSGSWDATADCLK
CS
L3,D2,D1,E1
CLRC1
TEST1TEST2TEST3
K4,L4,K3
STOSHUTCLKO
J3,J1,F1
Internal circuitPin namePin No.
Technical Data (continued)5. I/O block circuit diagrams and Pin function descriptionsNote) The characteristics listed below are reference values based on the IC design and are not guaranteed.
DVDD2 DVSS2
Pin C2Pin F2Pin L1Pin G3Pin J6Pin C8
Pin B2Pin E2Pin L2Pin H3
DVDD2 DVSS2
Pin C2Pin F2Pin L1Pin G3Pin J6Pin C8
Pin B2Pin E2Pin L2Pin H3
DVDD2 DVSS2
Pin C2Pin F2Pin L1Pin G3Pin J6Pin C8
Pin B2Pin E2Pin L2Pin H3
DVDD2 DVSS2
Pin C2Pin F2Pin L1Pin G3Pin J6Pin C8
Pin B2Pin E2Pin L2Pin H3
Pin J3, J1, F1
Pin K4,L4,K3
Pin C1
Pin L3,D2,D1,E1
Mainten
ance/
Discon
tinued
Mainten
ance/D
iscont
inued
includ
es foll
owing
four P
roduct
lifecyc
le stag
e.
(planed
mainten
ance ty
pe, main
tenanc
e type,
planed
discon
tinued
typed,
discon
tinued
type)
NN12081A
32SDB00165BEB
RHL
A9,A8
EXADCLK EXDS1EXDS2
K1,K2,J2
VDHD
SUBSW1SUBSW2MSUBSW
H1,G1,H2,G2,G4
Internal circuitPin namePin No.
Technical Data (continued)5. I/O block circuit diagrams and Pin function descriptions (continued)Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
DVDD2 DVSS2
Pin C2Pin F2Pin L1Pin G3Pin J6Pin C8
Pin B2Pin E2Pin L2Pin H3
DVDD2 DVSS2
Pin C2Pin F2Pin L1Pin G3Pin J6Pin C8
Pin B2Pin E2Pin L2Pin H3
DVDD4 DVSS4
Pin B8Pin A7
Pin H1,G1,H2,G2,G4
Pin K1,K2,J2
Pin A9,A8
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NN12081A
33SDB00165BEB
H1H2H3H4
D11,C11,B11,A11
D0D1D2D3D4D5D6D7D8D9D10D11
B7,C7,B6,C6,B5,C5,A4,B4,C4,A3,B3,C3
XOB1
XIA2
Internal circuitPin namePin No.
Technical Data (continued)5. I/O block circuit diagrams and Pin function descriptions (continued)Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
DVDD2 DVSS2
Pin C2Pin F2Pin L1Pin G3Pin J6Pin C8
Pin B2Pin E2Pin L2Pin H3
DVDD2 DVSS2
Pin C2Pin F2Pin L1Pin G3Pin J6Pin C8
Pin B2Pin E2Pin L2Pin H3
DRVDD DRVSS
Pin A6 Pin A5
Pin A2
Pin B1
Pin B7, C7,B6, C6,B5, C5,A4, B4,C4, A3,B3, C3
DVDD3 DVSS3
Pin D10Pin C10
Pin E10Pin B10Pin A10
Pin D11,C11,B11,A11
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NN12081A
34SDB00165BEB
DC_DET2L7
DC_DET3K6
VRTVRB
L5,L6
Internal circuitPin namePin No.
Technical Data (continued)5. I/O block circuit diagrams and Pin function descriptions (continued)Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
AVDD1 AVSS1
Pin K11Pin K7
Pin L10Pin K8
AVDD1 AVSS1
Pin K11Pin K7
Pin L10Pin K8
AVDD1 AVSS1
Pin K11Pin K7
Pin L10Pin K8
Pin L5, L6
Pin K6
Pin L7
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NN12081A
35SDB00165BEB
CCDOUTL11
DC_DET1L8
Internal circuitPin namePin No.
Technical Data (continued)5. I/O block circuit diagrams and Pin function descriptions (continued)Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
AVDD1 AVSS1
Pin K11Pin K7
Pin L10Pin K8
AVDD1 AVSS1
Pin K11Pin K7
Pin L10Pin K8
Pin L8
Pin L11
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NN12081A
36SDB00165BEB
OSUBL9
OV11BOV11AOV9BOV9AOV7BOV7AOV5BOV5AOV3BOV3AOV1BOV1A
J8,K9,
K10,J9,
J10,J11,H9,H8,
H10,H11,F10,E11
OV11LOV11ROV9LOV9ROV7SOV12OV10OV8OV6OV4OV2
G9,G10,G8,
G11,F11,E8,E9,D8,D9,C9,B9
RESETD4
Internal circuitPin namePin No.
Technical Data (continued)5. I/O block circuit diagrams and Pin function descriptions (continued)Note) The characteristics listed below are reference values based on the IC design and are not guaranteed.
Pin G9, G10, G8, G11, F11, E8, E9, D8, D9, C9, B9
DVSS2 VH
VL
Pin J8, K9, K10, J9, J10, J11, H9, H8, H10, H11, F10, E11
VMSUB VHH
VL
DVDD2 DVSS2
Pin C2Pin F2Pin L1Pin G3Pin J6Pin C8
Pin B2Pin E2Pin L2Pin H3
Pin D4
Pin L9
VL
DVSS2
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NN12081A
37SDB00165BEB
Special attention and precaution in using1. This IC is intended to be used for general electronic equipment [Analog front-end processing IC for digital cameras].
Consult our sales staff in advance for information on the following applications:• Special applications in which exceptional quality and reliability are required, or if the failure or malfunction of this IC may
directly jeopardize life or harm the human body.• Any applications other than the standard applications intended.
(1) Space appliance (such as artificial satellite, and rocket)(2) Traffic control equipment (such as for automobile, airplane, train, and ship)(3) Medical equipment for life support(4) Submarine transponder(5) Control equipment for power plant(6) Disaster prevention and security device(7) Weapon(8) Others: Applications of which reliability equivalent to (1) to (7) is required
2. Pay attention to the direction of LSI. When mounting it in the wrong direction onto the PCB (printed-circuit-board), it might smoke or ignite.
3. Pay attention in the PCB (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. In addition, refer to the Pin Description (Page 6 to Page 9) for the pin configuration.
4. Perform a visual inspection on the PCB before applying power, otherwise damage might happen due to problems such as a solder-bridge between the pins of the semiconductor device. Also, perform a full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the LSI during transportation.
5. Take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as output pin –VCC short (power supply fault), output pin – GND short (ground fault), or output-to-output-pin short (load short) . And, safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply.
6. When using the LSI for new models, verify the safety including the long-term reliability for each product.7. When the application system is designed by using this LSI, be sure to confirm notes in this book.
Be sure to read the notes to descriptions and the usage notes in the book.
Usage Notes
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NN12081A
38SDB00165BEB
0 ms or more
DVSS2 (GND)
VHH
VDC
(a) (b)VL
VMSUB
DVDD2 × 0.9
VH
Time
DVSS2 (GND)
VHH
VDC
VL 0 ms or more
(a) (b)VMSUB
DVDD2 × 0.9
VH
Time
Usage Notes (continued)
1. Power-on / power-off sequence(1) Power-on sequence
Follow the CCD power-on procedure to turn on the IC.The V-driver power-on sequence should be as the figure below indicates. After applying the DVDD2 voltages, wait until DVDD2 goes over 90%, and then apply the VHH, VH, VL and VMSUB voltages. If the DVDD2 voltage is not applied to the IC first, the internal logic will be unstable, through currents will flow in the output drivers, and then the IC will be broken down.It is recommended that RESET pin be set to Low after VHH, VH, VL and VMSUB are applied until they rise completely.
(2) Power-off sequenceFollow the CCD power-off procedure to turn off the IC.The V-driver power-off sequence should be as the figure below indicates. After shutting off the VHH,VH,VL and VMSUBvoltages, shut off the DVDD2 voltages. If the DVDD2 voltage is not shut off last, the internal logic will be unstable, through currents will flow in the output drivers and then the IC will be broken down. It is recommended that the RESET pin be set to Low after VHH, VH, VL and VMSUB voltages are shut off and they fall completely.
2. When SUB driver is not used:(1) Connect VMSUB to GND.(2) No connection for OSUB.
3. Middle-level voltage of V-driver is connected to DVSS2 inside.
4. About bypass capacitorConnect bypass capacitors to each of power supply pins as close as possible to the IC pins.Use capacitors of 0.1 μF or more for these bypass capacitors.
5. OthersTake notice of the following items to prevent the IC from damage.(1) Avoid the short-circuit of V-driver output pins to power supply, otherwise the IC may be damaged.(2) Avoid the short-circuit of V-driver output pins to the ground, otherwise the IC may be damaged.(3) Avoid the short-circuit of V-driver output pins to output pin, otherwise the IC may be damaged.(4) Avoid reverse insertion or mounting of the IC, otherwise the IC may be damaged.
Attention and precaution in using
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NN12081A
39SDB00165BEB
Usage Notes (continued)
6. Power dissipation (technical report)Attention and precaution in using (continued)
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NN12081A
40SDB00165BEB
7. Power dissipation (supplementary explanation)
Package
Semiconductor element
Rth (j-c)
Rth (c-a)
Rth (j-a)
Ta
Tc
Tj
PWB
[Definition of each temperature and thermal resistance]Ta : Ambient air temperature
* The temperature of the air is defined at the position where the convection, radiation, etc. don’t affect the temperature value, and it is separated from the heating elements.
Tc : It is the temperature near the center of a package surface. The package surface is defined at the opposite side if the PWB. Tj : Semiconductor element surface temperature (Junction temperature)
Rth (j-c) : The thermal resistance (difference of temperature of per 1 Watts) between a semiconductor element junction part and the package surface
Rth (c-a) : The thermal resistance (difference of temperature of per 1 Watts) between the package surface and the ambient airRth (j-a) : The thermal resistance (difference of temperature of per 1 Watts) between a semiconductor element junction part and the
ambient air.
[Supplementary information of PWB to be used for measurement]The supplement of PWB information for power dissipation data (technical report) are shown below.
FR-44-layer4-layer
FR-41-layerGlass-epoxy
Resin materialTotal layerIndication
[Notes about power dissipation (Thermal resistance) ]Power dissipation values (Thermal resistance) depend on the conditions of the surroundings, such as specification of PWB and a
mounting condition, and a ambient temperature. (Power dissipation (Thermal resistance) is not a fixed value.)The Power dissipation value (Technical report) is the experiment result in specific conditions (evaluation environment of SEMI
standard conformity), and keep in mind that Power dissipation values (Thermal resistance) depend on circumference conditionsand also change.
[Experiment environment] Power dissipation (technical report) is a result in the experiment environment of SEMI standard conformity.(Ambient air temperature (Ta) is 25°C.)
Definition image
[ Definition formula ]
Rth (j-a) = Tj – Ta
P(°C/W)
Rth (c-a) = Tc – Ta
P(°C/W)
Rth (j-c) = Tj – Tc
P(°C/W)
Tj = {Rth (j-c) + Rth (c-a) } × P + Ta
= Rth (j-a) × P + Ta
P: Power (W)
= Rth (j-c) + Rth (c-a)
Usage Notes (continued)Attention and precaution in using (continued)
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Request for your special attention and precautions in using the technical information andsemiconductors described in this book
(1)If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed.
(2)The technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. No license is granted in and to any intellectual property right or other right owned by Panasonic Corporation or any other company. Therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book.
(3)The products described in this book are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications:� Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support
systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the prod-ucts may directly jeopardize life or harm the human body.� Any applications other than the standard applications intended.
(4)The products and product specifications described in this book are subject to change without notice for modification and/or im-provement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements.
(5)When designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). Especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. Otherwise, we will not be liable for any defect which may arise later in your equipment.
Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products.
(6)Comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (ESD, EOS, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. When using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages.
(7)This book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company.
20080805
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