Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San...

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Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger

Transcript of Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San...

Page 1: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Data Criticality in Network-On-Chip Design

Joshua San Miguel

Natalie Enright Jerger

Page 2: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Network-On-Chip Efficiency

2

Efficiency is the ability to produce results with the least amount of waste.

Wasted time NoC accounts for 30-70% of on-chip data access latency

[Z. Li, HPCA 2009][A. Sharifi, MICRO 2012]

Wasted energy NoC accounts for 20-30% of total chip power

[J. D. Owens, IEEE Micro 2007][S. R. Vangal, IEEE JSSC 2008]

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Network-On-Chip Efficiency

3

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Network-On-Chip Efficiency

4

load request

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Network-On-Chip Efficiency

5

data response

load request

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Network-On-Chip Efficiency

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data response

load request

Minimize wasted time Deliver data no later than needed

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Network-On-Chip Efficiency

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Page 8: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Network-On-Chip Efficiency

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load request 0x2

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Network-On-Chip Efficiency

9

data response

0 1 2 3 4 5 6 7

load request 0x2

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Network-On-Chip Efficiency

10

data response

0 1 2 3 4 5 6 7

load request 0x2

Minimize wasted energy Deliver data no earlier than needed

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Network-On-Chip Efficiency

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Why store data in blocks of multiple words?

Exploit spatial locality in applications

Avoid large tag arrays in caches

Improve row buffer utilization in DRAM

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Network-On-Chip Efficiency

12

Why store data in blocks of multiple words?

Exploit spatial locality in applications

Avoid large tag arrays in caches

Improve row buffer utilization in DRAM

Store data at a coarse granularity, but

move data at a fine granularity.

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Network-On-Chip Efficiency

13

01:00

03:00

02:00

04:00

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Network-On-Chip Efficiency

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01:00

03:00

02:00

04:00

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Network-On-Chip Efficiency

15

01:00

03:00

02:00

04:00

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Network-On-Chip Efficiency

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01:00

03:00

02:00

04:00

Arrive no later than needed. But expensive. Wasted money since some arrive too early.

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Network-On-Chip Efficiency

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01:00

03:00

02:00

04:00

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Network-On-Chip Efficiency

18

01:00

03:00

02:00

04:00

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Network-On-Chip Efficiency

19

01:00

03:00

02:00

04:00

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Network-On-Chip Efficiency

20

01:00

03:00

02:00

04:00

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Network-On-Chip Efficiency

21

01:00

03:00

02:00

04:00

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Network-On-Chip Efficiency

22

01:00

03:00

02:00

04:00

Spend just enough money to arrive both no later and no earlier than needed.

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Network-On-Chip Efficiency

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01:00

03:00

02:00

04:00

Spend just enough money to arrive both no later and no earlier than needed.

Deliver data both no later and no earlier than needed Design for data criticality

Page 24: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Outline

24

Defining Criticality Data Criticality

Data Liveness

Measuring Criticality Energy Wasted

Addressing Criticality NoCNoC

Page 25: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Data Criticality

25

Data Criticality is the promptness with which an application uses a data word after fetching it from memory.

Critical: used immediately after being fetched.

Non-critical: used some time later after being fetched.

Defining Criticality

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Data Criticality – blackscholes

26

for (i++) {

... = BlkSchlsEqEuroNoDiv(sptprice[i]);

}

Defining Criticality

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Data Criticality – blackscholes

27

for (i++) {

... = BlkSchlsEqEuroNoDiv(sptprice[i]);

}

Defining Criticality

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

sptprice

i = 0

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Data Criticality – blackscholes

28

for (i++) {

... = BlkSchlsEqEuroNoDiv(sptprice[i]);

}

Defining Criticality

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

sptprice

i = 15

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Data Criticality – blackscholes

29

for (i++) {

... = BlkSchlsEqEuroNoDiv(sptprice[i]);

}

Defining Criticality

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

sptprice

criticality

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Data Criticality – fluidanimate

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for (iparNeigh++) {

if (borderNeigh) {

pthread_mutex_lock();

neigh->a[iparNeigh] -= ...;

pthread_mutex_unlock();

} else {

neigh->a[iparNeigh] -= ...;

}

}

Defining Criticality

Page 31: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Data Criticality

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Data criticality is an inherent consequence of spatial locality and is exhibited by most (if not all) real-world applications.

Examples of non-criticality: Long-running code between accesses

Interference due to thread synchronization

Dependences from other cache misses

Preemption by the operating system

Defining Criticality

Page 32: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Data Criticality vs. Instruction Criticality

32

Instruction (or packet) criticality

Defining Criticality

load miss B

load miss A

load miss C

load miss D

Page 33: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Data Criticality vs. Instruction Criticality

33

Instruction (or packet) criticality

Defining Criticality

load miss B

load miss A

load miss C

load miss D

Page 34: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Data Criticality vs. Instruction Criticality

34

Data criticality

Defining Criticality

load miss B

load miss A

load miss C

load miss D

Page 35: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Data Liveness

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Data Liveness describes whether or not an application uses a data word at all after fetching it from memory.

Live-on-arrival (live): used at least once during its cache lifetime.

Dead-on-arrival (dead): never used during its cache lifetime.

Defining Criticality

Page 36: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Data Liveness – fluidanimate

36

for (iz++)

for (iy++)

for (ix++)

for (j++) {

if (border(ix)) ... = cell->v[j].x;

if (border(iy)) ... = cell->v[j].y;

if (border(iz)) ... = cell->v[j].z;

}

Defining Criticality

Page 37: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Data Liveness – fluidanimate

37

for (iz++)

for (iy++)

for (ix++)

for (j++) {

if (border(ix)) ... = cell->v[j].x;

if (border(iy)) ... = cell->v[j].y;

if (border(iz)) ... = cell->v[j].z;

}

Defining Criticality

x y z x y z x y z x y z x y z

cell->v

Page 38: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Data Liveness – fluidanimate

38

for (iz++)

for (iy++)

for (ix++)

for (j++) {

if (border(ix)) ... = cell->v[j].x;

if (border(iy)) ... = cell->v[j].y;

if (border(iz)) ... = cell->v[j].z;

}

Defining Criticality

x y z x y z x y z x y z x y z

cell->v

Page 39: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Data Liveness

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Data liveness measures the degree of spatial locality in an application.

Examples of dead words: Unused members of structs

Irregular or random access patterns

Heap fragmentation

Padding between data elements

Early evictions due to invalidations, cache pressure or poor replacement policies

Defining Criticality

Page 40: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Outline

40

Defining Criticality Data Criticality

Data Liveness

Measuring Criticality Energy Wasted

Addressing Criticality NoCNoC

Page 41: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality

41 Measuring Criticality

time

load miss A fetch A[i] use A[i]

fetch latency

Page 42: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality

42 Measuring Criticality

time

load miss A fetch A[i] use A[i]

fetch latency

access latency

Page 43: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

𝑛𝑜𝑛−𝑐𝑟𝑖𝑡𝑖𝑐𝑎𝑙𝑖𝑡𝑦 = 𝑎𝑐𝑐𝑒𝑠𝑠 𝑙𝑎𝑡𝑒𝑛𝑐𝑦

𝑓𝑒𝑡𝑐ℎ 𝑙𝑎𝑡𝑒𝑛𝑐𝑦

1x for critical words, >1x for non-critical words

Measuring Criticality

43 Measuring Criticality

time

load miss A fetch A[i] use A[i]

fetch latency

access latency

Page 44: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality

44

Full-system simulations: FeS2, BookSim, DSENT

16 2.0 GHz OoO cores

64 kB private L1 per core, 16-word cache blocks

16 MB shared distributed L2

Baseline NoC configuration: 4 x 4 mesh, 2.0 GHz, 128-bit channels

X-Y routing, 3-stage router pipeline, 6 4-flit VCs per port

Applications: PARSEC and SPLASH-2

Measuring Criticality

Page 45: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality

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Very low criticality

Measuring Criticality

0%

20%

40%

60%

80%

100%

1x 2x 3x 4x 5x 6x 7x 8x 9x 10x

% a

cces

sed

wo

rds

(cu

mu

lati

ve)

access latency / fetch latency

blackscholes bodytrack fluidanimate streamcluster swaptions

Page 46: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality

46

Low criticality

Measuring Criticality

0%

20%

40%

60%

80%

100%

1x 2x 3x 4x 5x 6x 7x 8x 9x 10x

% a

cces

sed

wo

rds

(cu

mu

lati

ve)

access latency / fetch latency

barnes lu_cb water_nsquared water_spatial

Page 47: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality

47

High criticality

Measuring Criticality

0%

20%

40%

60%

80%

100%

1x 2x 3x 4x 5x 6x 7x 8x 9x 10x

% a

cces

sed

wo

rds

(cu

mu

lati

ve)

access latency / fetch latency

fft vips volrend x264

Page 48: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality

48

Very high criticality

Measuring Criticality

0%

20%

40%

60%

80%

100%

1x 2x 3x 4x 5x 6x 7x 8x 9x 10x

% a

cces

sed

wo

rds

(cu

mu

lati

ve)

access latency / fetch latency

canneal cholesky radiosity radix

Page 49: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality – Energy Wasted

49

Estimate energy wasted due to non-criticality

Model an ideal NoC where for each word: 𝑓𝑒𝑡𝑐ℎ 𝑙𝑎𝑡𝑒𝑛𝑐𝑦 ≈ 𝑎𝑐𝑐𝑒𝑠𝑠 𝑙𝑎𝑡𝑒𝑛𝑐𝑦

Measuring Criticality

Page 50: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality – Energy Wasted

50 Measuring Criticality

Estimate energy wasted due to non-criticality

Model an ideal NoC where for each word: 𝑓𝑒𝑡𝑐ℎ 𝑙𝑎𝑡𝑒𝑛𝑐𝑦 ≈ 𝑎𝑐𝑐𝑒𝑠𝑠 𝑙𝑎𝑡𝑒𝑛𝑐𝑦

Page 51: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality – Energy Wasted

51 Measuring Criticality

high criticality

low criticality

Estimate energy wasted due to non-criticality

Model an ideal NoC where for each word: 𝑓𝑒𝑡𝑐ℎ 𝑙𝑎𝑡𝑒𝑛𝑐𝑦 ≈ 𝑎𝑐𝑐𝑒𝑠𝑠 𝑙𝑎𝑡𝑒𝑛𝑐𝑦

Page 52: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality – Energy Wasted

52

e.g., bodytrack:

Measuring Criticality

0%

20%

40%

60%

80%

100%

1x 6x 11x 16x 21x 26x 31x

% a

cces

sed

wo

rds

(cu

mu

lati

ve)

access latency / fetch latency

subnet 1 subnet 2 subnet 3 subnet 4 subnet 5 subnet 6

Page 53: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality – Energy Wasted

53

e.g., bodytrack:

Measuring Criticality

0%

20%

40%

60%

80%

100%

1x 6x 11x 16x 21x 26x 31x

% a

cces

sed

wo

rds

(cu

mu

lati

ve)

access latency / fetch latency

subnet 1 subnet 2 subnet 3 subnet 4 subnet 5 subnet 6

1x – 1.1x

1.1x – 2x

2x – 3.5x

3.5x – 7x

18x - ∞

7x – 18x

Page 54: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality – Energy Wasted

54

e.g., bodytrack:

Measuring Criticality

0%

20%

40%

60%

80%

100%

1x 6x 11x 16x 21x 26x 31x

% a

cces

sed

wo

rds

(cu

mu

lati

ve)

access latency / fetch latency

subnet 1 subnet 2 subnet 3 subnet 4 subnet 5 subnet 6

1x – 1.1x, 2.0 GHz

1.1x – 2x, 1.8 GHz

2x – 3.5x , 1.0 GHz

3.5x – 7x, 571.4 MHz

18x - ∞, 111.0 MHz

7x – 18x, 285.7 MHz

Page 55: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality – Energy Wasted

55

Dynamic energy wasted due to non-criticality

Measuring Criticality

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40%b

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Page 56: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality – Energy Wasted

56

Dynamic energy wasted due to non-criticality

Measuring Criticality

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Page 57: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality – Energy Wasted

57

Dynamic energy wasted due to non-criticality

Measuring Criticality

0%

5%

10%

15%

20%

25%

30%

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40%b

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Page 58: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality – Energy Wasted

58

Dynamic energy wasted due to dead words

Measuring Criticality

0%10%20%30%40%50%60%70%80%90%

100%b

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Page 59: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Measuring Criticality – Energy Wasted

59

Dynamic energy wasted due to dead words

Measuring Criticality

0%10%20%30%40%50%60%70%80%90%

100%b

arn

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68.8% energy wasted due to non-critical and dead words.

Page 60: Data Criticality in Network-On-Chip Design...Data Criticality in Network-On-Chip Design Joshua San Miguel Natalie Enright Jerger Network-On-Chip Efficiency 2 Efficiency is the ability

Outline

60

Defining Criticality Data Criticality

Data Liveness

Measuring Criticality Energy Wasted

Addressing Criticality NoCNoC

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Addressing Criticality

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A criticality-aware NoC design needs to:

1. Predict the criticality of a word prior to fetching it.

2. Separate the fetching of words based on their criticality.

3. Reduce energy consumption in fetching low-criticality words.

4. Eliminate the fetching of dead words.

NoCNoC (Non-Critical NoC)

A proof-of-concept, criticality-aware design

Addressing Criticality

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NoCNoC

62 Addressing Criticality

1. Predict the criticality of a word prior to fetching it.

Binary predictor: either critical or non-critical.

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63 Addressing Criticality

1. Predict the criticality of a word prior to fetching it.

Binary predictor: either critical or non-critical. load miss (requested word 4)

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64 Addressing Criticality

000000000000010X101000000000000

-15 … 0 … 15

instruction address

prediction table

1. Predict the criticality of a word prior to fetching it.

Binary predictor: either critical or non-critical. load miss (requested word 4)

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65 Addressing Criticality

000000000000010X101000000000000

-15 … 0 … 15

instruction address

prediction table

1. Predict the criticality of a word prior to fetching it.

Binary predictor: either critical or non-critical. load miss (requested word 4)

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66 Addressing Criticality

000000000000010X101000000000000

-15 … 0 … 15

instruction address

prediction table

1. Predict the criticality of a word prior to fetching it.

Binary predictor: either critical or non-critical. load miss (requested word 4)

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67 Addressing Criticality

000000000000010X101000000000000

-15 … 0 … 15

instruction address

prediction table

1. Predict the criticality of a word prior to fetching it.

Binary predictor: either critical or non-critical. load miss (requested word 4)

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68 Addressing Criticality

000000000000010X101000000000000

-15 … 0 … 15

instruction address

prediction table

0 … 15

prediction vector (requested word 4)

0010110100000000

1. Predict the criticality of a word prior to fetching it.

Binary predictor: either critical or non-critical. load miss (requested word 4)

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000000000000010X101000000000000

-15 … 0 … 15

instruction address

prediction table

0 … 15

prediction vector (requested word 4)

L1 request packet 0010110100000000

1. Predict the criticality of a word prior to fetching it.

Binary predictor: either critical or non-critical. load miss (requested word 4)

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2. Separate the fetching of words based on their criticality.

Two physical subnetworks: critical and non-critical.

Addressing Criticality

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2. Separate the fetching of words based on their criticality.

Two physical subnetworks: critical and non-critical.

Addressing Criticality

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72 Addressing Criticality

critical

non-critical

2. Separate the fetching of words based on their criticality.

Two physical subnetworks: critical and non-critical.

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3. Reduce energy consumption in fetching low-criticality words.

DVFS in non-critical subnetwork.

Addressing Criticality

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3. Reduce energy consumption in fetching low-criticality words.

DVFS in non-critical subnetwork.

Addressing Criticality

critical

if criticality very low

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3. Reduce energy consumption in fetching low-criticality words.

DVFS in non-critical subnetwork.

Addressing Criticality

critical

if criticality low

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3. Reduce energy consumption in fetching low-criticality words.

DVFS in non-critical subnetwork.

Addressing Criticality

critical

if criticality high

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3. Reduce energy consumption in fetching low-criticality words.

DVFS in non-critical subnetwork.

Addressing Criticality

critical

if criticality very high

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4. Eliminate the fetching of dead words.

Binary predictor: either live or dead.

Addressing Criticality

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4. Eliminate the fetching of dead words.

Binary predictor: either live or dead.

Addressing Criticality

000000000000010X101000000000000

-15 … 0 … 15

instruction address

prediction table

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More details and results in the paper:

DVFS scheme

Prediction tables

Comparison to instruction criticality (Aergia [R. Das, ISCA 2010])

Addressing Criticality

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NoCNoC – Prediction Accuracy

81 Addressing Criticality

80%

85%

90%

95%

100%

criticality liveness

pre

dic

tio

n a

ccu

racy

correct over under

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NoCNoC – Prediction Accuracy

82 Addressing Criticality

80%

85%

90%

95%

100%

criticality liveness

pre

dic

tio

n a

ccu

racy

correct over under

Outperforms prior liveness predictor (70% accuracy) [H. Kim, NOCS 2011]

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NoCNoC – Performance and Energy

83 Addressing Criticality

0.6

0.7

0.8

0.9

1

1.1

dynamic energy runtime

no

rmal

ized

to

bas

elin

e

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Conclusion

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Define Data Criticality Deliver data both no later and no earlier than needed.

Measure Criticality 68.8% energy wasted due to non-critical and dead words.

Address Criticality NoCNoC, a proof-of-concept, criticality-aware design.

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Thank you