Features• Board

– High voltage rail up to 1200 V– Negative gate driving– Onboard isolated DC-DC converters to supply high-side and low-side gate

drivers, fed by VAUX = 5 V, with 5.2 kV maximum isolation– 3.3 V VDD logic supply generated onboard or 5 V (externally applied)– Easy jumper selection of driving voltage configuration:

+15/0 V; +15/-3 V; +19/0 V; +19/-3 V;• Device

– Driver current capability: 4 A source/sink @ 25°C– Separate sink and source for easy gate driving configuration– 6000 V Galvanic isolation– Short propagation delay: 75 ns– UVLO function– Gate driving voltage up to 26 V– 3.3 V, 5 V TTL/CMOS inputs with hysteresis– Temperature shutdown protection– Standby function

DescriptionThe EVALSTGAP2HSM is an isolated single gate driver.

The gate driver is characterized by 4 A current capability and rail-to-rail outputs,making the device suitable also for high power inverter applications such as motordrivers in industrial applications equipped with MOSFET / IGBT power switch.

The separated source and sink outputs allow to independently optimize turn-on andturn-off by using dedicated gate resistors.

The device integrates protection functions: UVLO and thermal shutdown are includedto easily design high reliability systems. Dual input pins allow choosing the controlsignal polarity and also implementing HW interlocking protection in order to avoidcross-conduction in case of controller's malfunction.

The device allows implementing negative gate driving, and the onboard isolated DC-DC converters allow working with optimized driving voltage for MOSFET/IGBT.

The EVALSTGAP2HSM board allows evaluating all the STGAP2HSM features whiledriving a half-bridge power stage with voltage rating up to 1200 V in TO-220 orTO-247 package.

The board allows easily selecting and modifying the values of relevant externalcomponents in order to ease driver performance evaluation under differentapplicative conditions and fine pre-tuning of the final application’s components.

Product status link

EVALSTGAP2HSM

Demonstration board for STGAP2HSM isolated 4 A single gate driver

EVALSTGAP2HSM

Data brief

DB4269 - Rev 1 - September 2020For further information contact your local STMicroelectronics sales office.

www.st.com

1 Schematic diagram

Figure 1. EVALSTGAP2HSM circuit schematic – gate drivers

TO247

TO220

GNDPWR

OUT

HV

GNDISO_H

GND

VDD

IN+_L IN-_L GND

IN-_H IN+_H

IN+_L

VDD

IN-_H

GND IN-_L

IN+_H

EVALSTGAP2HSVersion: R1.0

2HSM2HSCM

GNDISO_L

VAUX

VAUX

10-20R

TO247

TO220

VDD

VDD

VDD VH_H

VDD

VH_L

VH_HVH_L

VH_L

VH_HVAUX

HV

GNDISO_L

GNDISO_H

OUT

C3

1uF 50V

C4

N.M.

TP2

R9 100R

Q2AN.M.

3

1

2

Q1N.M.

3

1

2

C1100nF/50V

TP9

C7 1uF 50V

C12220pF/25V

CN1 TE 928814-1

11

22

TP3

J21234567

R7 100R

R4 100R

C11

N.M.

TP10

TP11

R2 2R2

TP4

JP9CLOSED

R3 100R

C6220pF/25V

CN3 TE 928814-1

11

22

TP8

R1 22R

TP5

VP1 FULL

D2

STTH112A

2 1

U2 STGAP2HSM

VDD1

IN+2

IN-3

GND4 GNDISO 8

GOFF 7

GON 6

VH 5

C8100nF/50V

D1STPS2L40ZFY

12

C9100nF/50V

TP12

U1 STGAP2HSM

VDD1

IN+2

IN-3

GND4 GNDISO 8

GOFF 7

GON 6

VH 5

TP6

VP2 EMPTY

R5

N.M.

JP8 OPEN

Q2N.M.

3

1

2

C14 1uF 50V

JP4 CLOSED

R6 22R

D3STPS2L40ZFY

12

JP2 OPEN

R8 2R2

VP3 EMPTY

JP7CLOSED

J11234567

TP1

Q1AN.M.

3

1

2

C2100nF/50V

JP3CLOSED

C13220pF/25V

TP13

VP4 EMPTY

JP6 OPEN

C5220pF/25V

C10

1uF 50V

JP5 CLOSED

TP7

CN2 TE 928814-1

11

22

JP1CLOSED

GNDPWR

IN+L

IN-L

GL

C_IN+L

C_IN-L

IN-H

IN+H

GNDISO_H

C_IN-H

C_IN+HGH

C_IN+HC_IN-L

C_IN+L C_IN-H

C_IN+HC_IN-HC_IN+LC_IN-L

C_IN-L C_IN-H

C_IN+HC_IN-HC_IN+LC_IN-L

VDD

VDD

GOFCH

GONUH

HV

OUT

OUT

GNDISO_L

GOFCL

GONUL

VAUX

VAUX

GH

GL

EVALSTGAP2HSM Schematic diagram

DB4269 - Rev 1 page 2/12

Figure 2. EVALSTGAP2HSM circuit schematic – supply, connectors and decoupling

GNDISO_HVH_H

GNDISO_LVH_L

3V3

VAUX

Electr. P 7.5/10

SMD 1812

Film P 27.5 Film P 15mmSMD

1812

VH_H

VH_L

VDDVAUXHV

GNDISO_L

GNDISO_H

OUT

C3010uF/25V

JP17CLOSED

C18N.M.

TP17

FB1

BLM21AG471SN1

R121K

C17

1uF/50V

C151uF/50V

C26N.M.

JP15 CLOSED

R14

10M

FB2

BLM21AG471SN1

TP16

TP14

C201uF/50V

JP10 OPEN

D10MMSZ3V3T1G

21

C214.7uF/50V

JP12OPEN

C2933nF/1.25kV

C314.7uF/10V

C27N.M.

C191uF/50V

C22

1uF/50V

R11 0R

R1610M

J3N.M.

1

2

Q42STF1360

3

1

2

C241uF/50V

+ C25N.M.

JP16OPEN

D6BZT585B2V7T

JP18CLOSED 2-3

1

3

2

FB3

BLM21AG471SN1

Q32STF1360

3

1

2

T1 N.M.

2 3

41

FB4

BLM21AG471SN1

R13 0R

D5BZT585B20T

TP15

D8BZT585B16T

D9BZT585B2V7T

R101K

J4N.M.

1

2

JP14 OPEN

U3

MGJ2D051509SC

-Vout 5

+Vin1

-Vin2

0V 6

+Vout 7

JP13CLOSED

T2 N.M.

2 3

41

C28N.M.

R15240R

D7BZT585B20T

C164.7uF/50V

U4

MGJ2D051509SC

-Vout 5

+Vin1

-Vin2

0V 6

+Vout 7

D4BZT585B16T

C23N.M.

JP11

CLOSED

VAUX

GNDISO_HDCDCH-

DCDCL- GNDISO_L

VAUX

VAUX

3V3_REG

GNDPWR

DCDCL+

DCDCH+

EVALSTGAP2HSM Schematic diagram

DB4269 - Rev 1 page 3/12

2 Bill of material

Table 1. Bill of Material – components common to all device variants

Reference Description Value / Generic Part Number

CN1,CN2,CN3 Tab FASTON 250 horizontal TE 928814-1

C1,C2,C8,C9 SMT ceramic capacitor 100 nF/50 V

C3,C7,C10,C14 SMT ceramic capacitor 1 uF/50 V

C4,C11 SMT ceramic capacitor N.M.

C5,C6,C12,C13 SMT ceramic capacitor 220 pF/25 V

C15,C17,C19,C20,C22,C24 SMT ceramic capacitor 1 uF/50 V

C16,C21 SMT ceramic capacitor 4.7 uF/50 V

C18,C23 SMT ceramic capacitor N.M.

C25 THT electrolitic capacitor N.M.

C26,C27 SMT ceramic capacitor N.M.

C28 Film capacitor N.M.

C29 Film capacitor 33 nF/1.25k V

C30 SMT ceramic capacitor 10 uF/25 V

C31 SMT ceramic capacitor 4.7 uF/10 V

D1,D3 Automotive low drop power Schottky rectifier STPS2L40ZFY

D2 High voltage ultrafast rectifier STTH112A

D4,D8 Surface mount precision Zener diode BZT585B16T

D5,D7 Surface mount precision Zener diode BZT585B20T

D6,D9 Surface mount precision Zener diode BZT585B2V7T

D10 Zener voltage regulator 500 mW MMSZ3V3T1G

FB1,FB2,FB3,FB4 Ferrite beads BLM21AG471SN1

JP1,JP3,JP4,JP5,JP7,JP9,JP11,JP13,JP15,JP17 SMT jumper Closed

JP2,JP6,JP8,JP10,JP12,JP14,JP16 SMT jumper Open

JP18 SMT jumper Closed 2-3

J1 Connector terminal block T.H. 7 POS 3.5 mm MORSV-350-7P_screw

J2 Strip connector 7 POS, 2.54 mm STRIP 1x7

J3,J4 Connector terminal block T.H. 2 POS 5.08 mm N.M.

Q1,Q2 N-channel IGBT or MOSFET up to 1700 V N.M.

Q1A,Q2A N-channel IGBT or MOSFET up to 1700 V N.M.

Q3,Q4 Low voltage fast-switching NPN power transistors 2STF1360

R1,R6 SMT resistor 22R

R2,R8 SMT resistor 2R2

R3,R4,R7,R9 SMT resistor 100R

R5 SMT resistor N.M.

R10,R12 SMT resistor 1K

R11,R13 SMT resistor 0R

EVALSTGAP2HSM Bill of material

DB4269 - Rev 1 page 4/12

Reference Description Value / Generic Part Number

R14,R16 SMT resistor 10M

R15 SMT resistor 240R

TP1,TP2,TP3,TP4,TP5,TP6,TP7,TP8,TP11,TP13,TP14,TP15,TP16,TP17

Test point - PCB 1.5 mm diameter T POINT R

TP9,TP10,TP12 THT Ring test point TPTH-ANELLO-1MM

T1,T2 Common mode choke, SMD 4.7x4.5 mm N.M.

U1,U2 Galvanically isolated 4 A single gate driver STGAP2HSM

U3,U4 5.2KVDC isolated 2W Gate Drive DC-DC converters MGJ2D051509SC

VP1 PCB assembly version solder dot Full

VP2,VP3,VP4 PCB assembly version solder dot Empty

P.C.B. EVALSTGAP2HS Rev.1

EVALSTGAP2HSM Bill of material

DB4269 - Rev 1 page 5/12

3 Layout and component placements

Figure 3. EVALSTGAP2HSM – Layout (component placement top view)

Figure 4. EVALSTGAP2HSM – Layout (component placement bottom view)

EVALSTGAP2HSM Layout and component placements

DB4269 - Rev 1 page 6/12

Figure 5. EVALSTGAP2HSM – Layout (top layer)

Figure 6. EVALSTGAP2HSM – Layout (bottom layer)

EVALSTGAP2HSM Layout and component placements

DB4269 - Rev 1 page 7/12

Revision history

Table 2. Document revision history

Date Version Changes

08-Sep-2020 1 Initial release.

EVALSTGAP2HSM

DB4269 - Rev 1 page 8/12

Contents

1 Schematic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

2 Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3 Layout and component placements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

EVALSTGAP2HSM Contents

DB4269 - Rev 1 page 9/12

List of tablesTable 1. Bill of Material – components common to all device variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Table 2. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

EVALSTGAP2HSM List of tables

DB4269 - Rev 1 page 10/12

List of figuresFigure 1. EVALSTGAP2HSM circuit schematic – gate drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Figure 2. EVALSTGAP2HSM circuit schematic – supply, connectors and decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 3. EVALSTGAP2HSM – Layout (component placement top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 4. EVALSTGAP2HSM – Layout (component placement bottom view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 5. EVALSTGAP2HSM – Layout (top layer). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Figure 6. EVALSTGAP2HSM – Layout (bottom layer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

EVALSTGAP2HSM List of figures

DB4269 - Rev 1 page 11/12

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© 2020 STMicroelectronics – All rights reserved

EVALSTGAP2HSM

DB4269 - Rev 1 page 12/12