Dapc Dfm Guide 2.0

Design for Manufacturability Guidelines

Design for Manufacturability

Guidelines

USE FOR REFERENCE ONLY

UNCONTROLLED COPY

PROPRIETARY

PURPOSE / SCOPE This document establishes the procedure for the creation of tooling as performed by the Engineering Department. These standards are expected to yield product in accordance with the customer design criteria and the most current DAPC manufacturing capabilities. These guidelines define the criteria that will allow a part to be processed using a department’s normal operating processes. These guidelines also define the criteria to attain the maximum producible level. Concessions to these requirements are expected to reduce the producible level impacting cost and potentially yield or may require process modifications. The manufacturing tolerances, etch loss characteristics, and drill sizes defined by this standard supports typical product manufactured at DAPC V04.21.2008

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INDEX STANDARD PANEL SIZES .....................................................................................................................6 CONTROLLED IMPEDANCE .................................................................................................................10 CONTROLLED IMPEDANCE MODELING ................................................................................................10 LAYER STACK UP..............................................................................................................................11 MULTILAYER CONSTRUCTION GUIDELINES .........................................................................................14 MULTILAYER CONSTRUCTIONS ..........................................................................................................14 BLIND AND BURIED VIA DESIGN CONSTRAINTS ...................................................................................18 MICROVIAS .......................................................................................................................................19 FILLED VIAS......................................................................................................................................19 CONDUCTIVE FEATURES ...................................................................................................................20 HOLES AND SLOTS............................................................................................................................25 ROUTING ..........................................................................................................................................26 BEVELLING .......................................................................................................................................27 SCORING..........................................................................................................................................28 SOLDERMASK ...................................................................................................................................30 LEGEND MARKING.............................................................................................................................32 SURFACE FINISHES ...........................................................................................................................34 ELECTRICAL TEST.............................................................................................................................36 PCB DATA REQUIREMENTS...............................................................................................................37 CUSTOMER DATA MUST INCLUDE: .....................................................................................................37 COMMON DATA ISSUES .....................................................................................................................39

FIGURES FIGURE 1 - TYPICAL 18 X 24 PANEL .....................................................................................................5 FIGURE 2 - LAYOUT WITHOUT EDGE CONNECTORS .......................................................................................7 FIGURE 3 - GOLD PLATING INTERCONNECTION COMPONENTS .....................................................................8 FIGURE 4 - LAYOUT - EDGE CONNECTORS ....................................................................................................8 FIGURE 5 - LAY-UP WITH RECESSED EDGE CONNECTORS............................................................................9 FIGURE 6 – THROUGH HOLE VIA ..................................................................................................................15 FIGURE 7 – BLIND VIA AND THROUGH HOLE VIA .........................................................................................16 FIGURE 8 – BURIED VIA AND THROUGH HOLE VIA.......................................................................................17 FIGURE 9 – STANDARD TEARDROP ..............................................................................................................21 FIGURE 10- ANNULAR RING / TANGENCY / BREAKOUT ................................................................................21 FIGURE 11- LINE WIDTH & SPACING MEASUREMENT ..................................................................................22 FIGURE 12 - AVOID THERMAL ISOLATION & SLIVERS OF COPPER ..............................................................22 FIGURE 13 - HOLE-TO-COPPER SPACING .....................................................................................................23 FIGURE 14 - VIA-TO-GOLD EDGE CONNECTOR SPACING ..............................................................................24 FIGURE 15 - ROUND THIEVING .....................................................................................................................24 FIGURE 16 - BREAKAWAY TAB SPACING ......................................................................................................27 FIGURE 17 – BEVEL DIAGRAM ......................................................................................................................27 FIGURE 18 - EDGE MILLING DIAGRAM ..........................................................................................................28 FIGURE 19 - SCORING BLADE DIAGRAM.......................................................................................................29 FIGURE 20 – VIA PLUGGING .........................................................................................................................30 FIGURE 21 - SOLDERMASK SMD CLEARANCES...........................................................................................31 FIGURE 22 - FABRICATION DRAWING REQUIREMENTS .........................................................................38 FIGURE 23 – PCB MANUFACTURING PROCESS ..................................................................................41 FIGURE 24 – OUTER LAYER PLATING PROCESSES..............................................................................42 FIGURE 25 – INNER LAYER PROCESS.................................................................................................43

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TABLES TABLE 1 – PANEL SIZE AVAILABILITY....................................................................................................5 TABLE 2 – USEABLE PANEL AREA ........................................................................................................6 TABLE 3 - EDGE CONNECTOR RESTRICTIONS .......................................................................................7 TABLE 4 – AVAILABLE MATERIAL TYPES .............................................................................................11 TABLE 5 - LAMINATE (CORE) TOLERANCES.........................................................................................12 TABLE 6 – PRE-PREG TOLERANCES...................................................................................................12 TABLE 7 - COPPER FOIL EQUIVALENT THICKNESSES...........................................................................12 TABLE 8 – UL LISTING CARD .............................................................................................................13 TABLE 9 – CONDUCTIVE FEATURES ...................................................................................................20 TABLE 10 – HOLES AND SLOTS..........................................................................................................25 TABLE 11 – ROUTING, BEVELING AND SCORING .................................................................................26 TABLE 12 – SOLDERMASK AVAILABILITY.............................................................................................30 TABLE 13 - LEGEND MARKING SPECIFICATIONS ..................................................................................32 TABLE 14 – SURFACE FINISH COMPARISON........................................................................................34 TABLE 15 – SURFACE FINISH REFERENCE GUIDE ...............................................................................35 TABLE 16 – ELECTRICAL TEST PARAMETERS......................................................................................36 TABLE 17 – DATA REQUIREMENTS.....................................................................................................37 TABLE 18 – FILE FORMATS................................................................................................................38 TABLE 19 – PREFERRED README FILE CONTENTS .............................................................................39 TABLE 20 – DESIGN CAPABILITIES .....................................................................................................40 TABLE 21 – ETCH LOSS.....................................................................................................................43

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Introduction This manual provides an overview of the requirements for the Design for Manufacturability (DFM) and reliability for rigid multilayer printed circuit boards. Manufacturability is the practice of designing printed circuit boards that meet not only the capabilities of the customer’s assembly manufacturing process but also the capabilities of the board fabrication process. Some of the benefits of DFM are:

• Higher Quality • Reduced Lead Times • Lower Material Costs • Higher first pass yields • Minimized environmental impact

To achieve these benefits, this manual has been developed to enable a printed circuit board designer to understand the key cost drivers relative to bare board manufacture. The cost drivers are:

• Raw laminate – both panel utilization and material selection • Complexity factors (component / design technology) • Total number of holes • Surface finish requirements • Soldermask requirements • Electrical test complexity • Yield • Minimized environmental impact

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Panelization Specifications Standard Advanced Complex Panel Sizes 16x18, 12x14, 12x18, 18x24, 16x26 Number of layers 2 to 28 2 to 28 or higher 2 to 28 or higher Layer-to-layer registration

+/- 0.004”

Foil types available CAC, Electrodeposited copper

Copper foil elongation

≥ 6% High Temperature Elongation (HTE) - inner layers only

Table 1 – Panel Size Availability

Panelization is the process of placing one or more Printed Circuit Boards (PCB’s) on a manufacturing panel and incorporating features to assist manufacturing (such as tooling holes, fiducials, coupons, resin vents, panel thieving, etc.). This is one of the highest impact factors in the cost of a PCB. The panel area that is available for circuit boards and coupons is called the useable area. The useable area is measured as a percentage (total area for PCB’s divided by the total panel area). PCB’s are arranged in the useable area. Any area outside the useable area is designated for tooling to optimize manufacturing. A target panel utilization of greater than 75% is considered cost effective material utilization. The following pages will outline the provisions and requirements necessary make the best use of the available area in a manufacturing panel.

Useable Panel Area

16.50” x 22.50”

18 inches

16.50 inches

22.5

0 inc

hes

24.0

inch

es

Figure 1 - Typical 18 x 24 Panel

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Raw laminate is the single principal cost constituent of a multilayer PCB. Optimizing panel structure around standard base materials while achieving maximum material utilization on standard panel sizes can have a significant positive impact on multilayer board prices and deliveries.

There are three preferred panel sizes, 16x18 inches, 18x24 inches, and 21x24 inches. Larger panel size typically provides the most effective cost per unit area processed. Other panel sizes are also available for special applications.

The most effective material utilization will be achieved with PCBs or arrays of PCBS that their finished outline fit as efficiently as possible within the usable area of the panel. Test coupons must be within the usable area. The customer may negotiate to have locating holes and/or breakaway tabs for the insertion or surface mount equipment located outside the usable area. This is usually accomplished via the tab-routing process. Material utilization may be increased by employing the scoring process. This process places grooves on opposite sides of the panel between boards for snapping the boards from the panel. This method permits boards can be butted up against each other, eliminating the real estate for rout paths thereby allowing more boards may be placed on the panel.

For single and double-sided product, a 0.500-inch border is required around the periphery of the panel for tooling purposes. For multilayer this allowance is 0.750 inches.

Standard Panel Sizes Use the following table to determine the maximum, single 1-up PCB that can fit into a panel. Panel sizes are sub-divided into “standard” (most common) and “optional” (custom) classifications.

Useable Area Type Panel Size Double / Single Sided Multilayer

Standard 16.00” X 18.00” 15.00” X 17.00” 14.50” X 16.50” Standard 18.00” X 24.00” 17.00” X 23.00” 16.50” X 22.50” Standard 21.00” X 24.00” 20.00” X 23.00” 19.50” X 22.50” Optional 12.00” X 14.00” 11.00” X 13.00” 10.50” X 12.50” Optional 12.00” X 18.00” 11.00” X 17.00” 10.50” X 16.50” Optional 16.00” X 26.00” 15.00” X 25.00” 14.50” X 24.50”

Table 2 – Useable Panel Area

There are three general modifications to a panel, which will reduce the available useable area. These modifications include:

(1) Step-and-repeat requirements (2) Provisions for electroplating edge connectors (3) Coupon requirements

Step-and-Repeat The term ‘step-and-repeat’ describes the process of reproducing successive images onto a panel. For PCBs without gold-plated edge contacts, the standard step-and-repeat spacing between parts is normally 0.100”. A typical lay-up is shown in Figure 03.

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Figure 2 - Layout without Edge Connectors

Gold-Electroplated Edge Connectors

For printed circuit boards with gold-plated edge connectors (a.k.a. tips, fingers, tabs), parts are usually arranged such that the edge connectors are either facing each other or opposite each

other as in Figure 04. When edge connectors face each other, the space between the part outlines should be at minimum of 0.400”. This allows space for extensions to join the connectors

for electroplating and to allow room for a shearing operation to separate the pieces (see When the boundaries opposite the edge connectors are facing each other, the space between the parts can be 0.150” (minimum 0.100”) since there is no gold plating required in this area. Maximum distance between buss bar connections 24” Minimum PCB thickness 0.032” Maximum PCB thickness 0.125” Maximum edge connector recess 4.0” (minimum allowable solution level)

Table 3 - Edge Connector Restrictions

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Printed Circuit Board

Maximum Distance 24.0”

Plating BarExtenders

Pla

ting

Fram

e

Pla

ting

Fram

e

Optional


Maximum Distance 24.0”

Plating Bar

Pla

ting

Fram

e

Pla

ting

Fram

e


Figure 3 - Gold Plating Interconnection Components




5.50”Panel Width

Back-to-Edge

0.400”Typical

Figure 4 - Layout - Edge Connectors

For printed circuit boards with recessed gold-plated edge connectors, the same rules apply as those without recessed edge connectors with one exception. The greatest inboard gold-plated

feature must not exceed 4.00” (see Figure 4). When the gold-plated edge connectors are recessed greater than 4.00” a deep-tank process is required. This process is more expensive and

time consuming.

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2.500”Typical

0.100”Minimum

Usable Area of the Perimeter0.100”

Minimum

Figure 5 - Lay-up with Recessed Edge Connectors

Controlled Impedance Coupons Printed circuit boards with controlled impedance technology are processed with test coupons as part of the lay-up. When a +/- 15 ohms or +/- 20% of nominal impedance tolerance is specified, we recommend using controlled geometry to control impedance (see page 32).This will free area on the panel for parts since the coupons will not be needed. The coupon size and location is dependant on the number of layers and panel utilization. A possible arrangement is shown in Figure 6.

0.100”Minimum

Controlled Impedance Coupon


1.00”Coupon





Coupon

Figure 6 – Controlled Impedance Coupon Placement


Controlled Impedance

Control geometry to assure product conformance > 10% Control impedance to assure product ± 10%

Controlled Impedance Modeling Controlled impedance PCB’s, require specific constructions and tighter manufacturing controls. DAPC has tailored standard impedance equations to precisely calculate PCB constructions.

Controlled Geometry Controlled geometry boards have specified a thickness between certain layers and require no impedance coupons. These constructions do not give much flexibility regarding the materials used, and typically do not have many alternative constructions. DAPC will select the appropriate pre-preg and cores that satisfy the dielectric spacing, tolerance, and overall thickness requirements.

Serialization Serialization is a traceability process for controlled impedance jobs. DAPC adds test coupons to the panel to measure impedance with a TDR. When the impedance has been tested, the coupon and PCB have a serial number printed on them. Serialization adds additional steps to the manufacturing process.

100% Testing All impedance coupons are 100% electrically tested per panel when specified by the customer. After comparison against specified values, the measurements are electronically stored.

Multiple Impedances Some boards require multiple impedances on the same signal layer. DAPC is able to modify impedance coupons to accommodate such a request. The coupon will either be wider than normal (one trace for each impedance feature) or a secondary coupon will be added. However, testing multiple impedances on a given signal layer is not recommended. Whenever possible, designate one target impedance value per layer. Characteristic Impedance The characteristic impedance of a transmission line is dependent on the relationship of the conductor width, conductor thickness, dielectric thickness between conductor and ground-power reference planes, and the dielectric constant of the dielectric medium. It is recommended that the designer contact us to discuss impedance needs during the initial design phase. This will enable mutual understanding of requirements and impact of material characteristics, such as specific Dk (Dielectric Constants) and manufacturing processes, on needed impedance targets and tolerances. The actual impedance may have to be tested via a small prototype build. This is often necessary when tight impedance tolerances are required, or in the case of small line widths and dielectric thicknesses, which are more sensitive to variations. A tolerance swing due to etching variations will be more significant for a 0.005-inch line than for a 0.010-inch line, for example. Line width and dielectric thickness should be documented as reference only. This will allow us to make small adjustments to both parameters in order to match impedance targets. Note: if a line width modification is necessary, it will only be accomplished globally. That is, all of the lines of the same width will be modified on a given layer. No modification will be made without prior consent of the customer. For impedance calculations, it is important to consider the Etch Factor, the effective

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reduction of the line width during the etching process. The exception to this is with boards with an Aspect Ratio ≥ 4.5:1 or with boards ≥ 0.090 inch thick and an Aspect Ratio of ≥ 3:1. No Etch Factor needs to be considered in these cases. The recommended impedance tolerance is ±10%. A lesser tolerance is often achievable, especially with fully embedded Microstrip and Stripline structures. This requirement must be discussed with us for appropriate focus.

Layer Stack Up

Table 4 – Available Material Types

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Standard Material Tolerances

THICKNESS TOLERANCE CLASS

0.0030” ± 0.0007” B 0.0040” ± 0.0007” B 0.0050” ± 0.0010” B 0.0060” ± 0.0010” B 0.0075” ± 0.0015” B 0.0080” ± 0.0015” B 0.0100” ± 0.0015” B 0.0120” ± 0.0015” B 0.0140” ± 0.0020” B 0.0210” ± 0.0020” C 0.0280” ± 0.0020” C 0.0470” ± 0.0030” C 0.0590” ± 0.0030” C

Table 5 - Laminate (Core) Tolerances

Purchased Specifications (IPC 4101)

0.0030” – 0.0075” single ply construction laminate

AVAILABLE PRE-PREG THICKNESS RANGE

106 0.0015” – 0.0021” 1080 0.0025” – 0.0035” 2113 0.0035” – 0.0045” 2116 0.0045” – 0.0055” 7628 0.0065” – 0.0071”

Table 6 – Pre-Preg Tolerances

Copper Foil (Base Copper Weight): Coated copper layer on the board. It can be either characterized by weight or thickness of the coated copper layer. See chart below.

COPPER WEIGHT * THICKNESS (ounce) (mils) **0.25 0.35 **0.375 0.525

0.5 0.7 1 1.4 2 2.8 3 4.2

**4 5.6

Table 7 - Copper Foil Equivalent Thicknesses

*Purchased specifications. Tolerance per IPC-MF-150F

** Non standard stock

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Table 8 – UL Listing Card

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Multilayer Construction Guidelines When designing multilayer constructions for PCBs that do not have controlled impedance requirements, or other distinct specifications, the following guidelines should be used. Design balanced constructions that are symmetrical from the lay-up’s centre outward. Whenever possible, only one core thickness should be used. The maximum B-Stage opening between C-Stages is 0.021”. Note: Each outer layer is typically a signal layer built on 0.5-ounce copper. If the B-Stage opening is greater than 0.016” use filler cores.

Multilayer Constructions 1. Design multilayer boards with an even number of layers. 2. If specifying the dielectric thickness when for example may be required for impedance reasons, the dimensions should be selected from available core or pre-preg thickness. Dielectric thicknesses made up of pre-preg depend on the type or the combination of pre-preg is suitable and of achievable dimensions and tolerances. It is beneficial to discuss special dielectric requirements during the design stage if possible with your PCB vendor. 3. Maintaining a balance lay-up in relation to the z-axis median of the board will assure minimum bow and twist. This balance includes the following: dielectric thickness of layer, copper thickness of layers and its distribution and the location of circuit and plane layers. A higher number of layers normally will mean an increase number of plane layers. It is preferred that planes be balanced around the z-axis median line of the lay-up, and ideally located internal to the board. If accepted multilayer design rules are adhered to, boards will meet a maximum allowable bow and twist specification of 0.010 inch per inch (1%) or better. 4. Outer layer circuitry - circuit area and distribution between the front and back of the board should be balanced as closely as possible. The addition of plating thieving of low pattern density of external plane area should be considered. 5. Thickness tolerance - as the overall thickness of a multilayer board increases, the thickness tolerance should also increase. A good rule is to specify a tolerance of +/- 10% of the overall thickness. Always indicate where the thickness measurement is to be taken. Examples: glass to glass at rail guides, over gold contacts, over solder mask, etc.

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Blind and Buried Via (BBV) Boards

General description

Like through holes in a conventional multilayer board, blind and/or buried vias are plated holes that facilitate connections between copper layers. However, unlike in a conventional multilayer board, blind and buried vias allow circuits of non-planar topography to be connected. This is a significant strategy in order to conserve circuit board real estate because it allows only required layers to be connected.

We use the following terminology to define different types of via interconnection:

A through hole via has access to both external layers.

Figure 7 – Through Hole Via

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A blind hole via does not pass through the entire board, and has access to only one external layer.

Figure 8 – Blind Via and Through Hole Via

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A buried via provides connection within inner layers, it has no access to the external layers.

Figure 9 – Buried Via and Through Hole Via

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Blind and Buried Via Design Constraints

• Core thickness 0.003 minimum

Note: 0.5-ounce copper is required for BBV layers. Individual BBV layers will receive 0.0007 inch electrolytic copper during the through-hole plating process, bringing the total copper thickness to 0.0014 inch.

• Minimum drill size 0.0079 with a maximum aspect ratio of 7:1 for blind/buried via substrates.

Note: all BBV holes will be plugged with epoxy during subsequent lamination cycles.

• The ability to register drilled holes to inner layers is impacted after each lamination cycle.

• Minimum Annular Ring: drilled before first press cycle - 0.004 inch per side

• Drilled after first press cycle - 0.004 inch per side

• Drilled after second press cycle - 0.006 inch per side

• Drilled after third press cycle - 0.009 inch per side

Required information on drawings:

• The hole chart must list plated through holes separately from the Blind and or Buried via holes.

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Microvias

Microvias rules

Process 1 - Standard Conformal Opening

• Micro via diameter maximum - 0.003 inch minimum - 0.006 inch

• Maximum aspect ratio (depth/diameter) 1:1

• Minimum outer layer pad dia. via diameter + 0.008 inch

• Minimum landing layer pad dia. via diameter + 0.008 inch

• Panel thickness maximum - 0.100 inch minimum - 0.030

• Annual ring > 0.004 inch for all above conditions

Filled Vias

Conductive and Non-conductive filled vias have several applications where filled vias may be beneficial. Filled vias can improve routing density, can aid with electrical and thermal performance, and can improve board assembly. These are general design rules for this process.

Guidelines;

• Board thickness 0.020 to 0.120 inch

• Drill size 0.008 inch (min /0.020 inch (max.)

• Copper thickness IPC class II

• Outer layer features 0.004 inch minimum trace / 0.005 inch minimum trace

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Conductive Features

Specification Standard Advanced

Inner layers: Minimum line width / spacing:

½ oz - 0.0035” / 0.0035” 1 oz – 0.004” / 0.004” 2 oz – 0.006” / 0.006” 3 oz – 0.009” / 0.009” 4 oz – 0.011” / 0.011”

0.003” / 0.003” 0.003” / 0.003” 0.005” / 0.005” 0.008” / 0.008” 0.010” / 0.010”

Pad diameters:

Tangency: Add 0.010” to drilled hole diameter

Add 0.009” to drilled hole diameter

Annular ring requirements:

Drilled hole + 0.010” + 2 x min A/R

Drilled hole + 0.008” + 2 x min AR

Outer layers: Minimum line width / spacing:

0.005” / 0.005” (for ½ ounce foil)

0.003” / 0.003”

Pad Diameters: Tangency: Add 0.010” to drilled hole

diameter Add 0.009” to drilled

hole diameter Annular ring requirements:

Drilled hole + 0.009” + 2 x min A/R

Drilled hole + 0.008” + 2 x min AR

NPTH-to-Copper for primary drill:

0.010

Table 9 – Conductive Features

General To increase interconnect reliability on the signal layers, DAPC recommends that all pad-to-trace intersections be tear dropped whenever the pad diameter minus the plated hole diameter is less than 0.020”. This process is designed to provide additional metal at the critical junction of a pad and a run. When an order is drilled and mis-registration occurs, it has been theorized that a long-term reliability issue can arise if the mis-registration occurs at the junction of the pad and the trace. Adding metal at this location helps ensure that an adequate connection is made and maintained. The tear dropping process involves adding secondary pads at the junction of an existing (primary) pad and a circuit run. These secondary pads are sized 0.002 inch smaller than the primary pads, and the centre is placed 0.003 inch away from the centre of the primary pad. This tooling is conducted using IPC standards for tear dropping and has proven to be highly reliable and effective.

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Annular Ring Plated Hole

Teardrop

Trace

Figure 10 – Standard Teardrop

0.001” Annular RingMinimum

Plated HoleDiameter

Drilled HoleDiameter

Tangency

Circuit Pad Area

Breakout

Figure 11- Annular Ring / Tangency / Breakout

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Substrate Material

Line SpaceLine Width

Figure 12- Line Width & Spacing Measurement

Designer Reference Table Internal Power / Ground Layers Provide a layer number and description on the artwork. Clearance pads must be a minimum diameter of 0.020” larger than the nominal finished hole size. When placing thermal pads: Size the outside diameter using this formula: OD = FHS + 0.020” (Minimum: OD = ID + 0.010”) Rotation of thermals and addition of spokes is customer dependant Preferred set would be: rotate each thermal 45° to the plane and add spokes that are 90° apart Spoke width: 0.010” (preferred) or 0.006” (minimum) To prevent exposed copper at board edge of routed panel, keep copper 0.010” away from the PCB’s perimeter. Minimum barrel of hole-to-copper spacing: 0.008” (see Figure 14) To prevent exposed copper at board edge of scored panel, keep copper at 0.025” away from the PCB’s perimeter

Figure 13 - Avoid Thermal Isolation & Slivers of Copper

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Designer Reference Table Internal Signal Layers Preferred trace / space: 0.004” / 0.004” Minimum trace / space: 0.003” / 0.003” Inner signal layers must have a positive polarity Clearly label layer number and description Minimum barrel of hole-to-copper spacing: 0.008” (see Figure 14) No thieving smaller than a 0.030” feature size is allowed Relieve all copper internal to part from route paths by at least 0.010” Provide thieving inside all open and breakaway areas, if permitted by the customer

Figure 14 - Hole-to-copper spacing

Designer Reference Table Outer Layers

Preferred minimum trace / space: 0.004” / 0.004”. Minimum trace / space: 0.003” / 0.003”. Keep all pad edges at least 0.050” from gold features or they will be gold plated On the solder-side, leave a 0.200” x 0.400” area for DAPC to add a date code box, ID, UL logo, and cage code. Layout of circuitry on the board has a major influence on the way the panel actually plates. Try to avoid unbalanced copper area on the outer layers. Solitary traces will over plate, while isolated holes will over plate to yield finished hole sizes under specifications To maximize plating distribution, allow DAPC to add square thieving to low-density areas on the outer layers (such as breakaways or substantial unused spaces within the PCB). For boards with edge connectors, there must be at least 0.050” of soldermask between the soldermask clearance of the nearest via hole and the top of the edge connector area. If this spacing is violated, mask will be extended onto the edge connector until 0.050” is achieved (see Figure 15)

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0.050”

Nickel/Gold Edge Connectors

Vias

Figure 15 - Via-to-gold edge connector spacing

0.030”

Round Thieving

0.050”

0.020”

0.030” 0.050”

Printed Circuit Board Feature

Thieving Inside BGA/SMDArrays Removed Per Request

Low Density Circuit Area

Figure 16 - Round Thieving


Holes and Slots Specification Standard Advanced Complex Holes: Minimum drilled hole diameter:

0.011” 0.008”, 0.006”, 0.004”

Maximum drilled hole diameter:

0.250”

Maximum Aspect ratio: 8:1 16:1 Plated hole diameter tolerance:

+/- 0.003” + 0.002” / - 0.002”

Drilled hole diameter tolerance (NPT):

+/- 0.0015” +/- 0.001”

Hole-to-hole location accuracy:

+/- 0.003” (0.008” DTP)

+/- 0.002” (0.0065” DTP)

Micro Via 0.005” 0.003” – 0.008”

Table 10 – Holes and Slots

General Whenever possible, combine hole diameters that are within 0.002” of each other. Do not add holes that are unnecessary. Clearly indicate on the fabrication drawing if any holes or slots can be optionally plated. The ‘aspect ratio’ is a ratio of the length or depth of a hole to its pre-plated diameter.

Plated Through Holes Standard diameter tolerance: +/- 0.003”. Minimum diameter tolerance: + 0.003” / -0.002”. Minimum backplane hole diameter tolerance: +/- 0.002”. Minimum hole edge-to-hole edge spacing: 0.015”. The tolerance for any via ≤ 0.018” in diameter will be + 0.003” / - nominal hole size.

Plated Slots Minimum size tolerance (length & width): +/- 0.005”. Minimum position tolerance: +/- 0.005”.

Non-Plated Through Holes Minimum drilled hole diameter tolerance: +/- 0.0015”. Minimum second drill diameter tolerance: +/- 0.0015”. Tooling holes should be ≤ 0.250”. The preferred size is 0.125”. Non-plated holes with a diameter greater than 0.250” will be produced during the profile routing sequence (Size tolerance = +/- 0.005” and Position tolerance = +/- 0.005”). Holes with a diameter > 0.250” will be routed. Non-plated holes and slots will be second drilled whenever the required 0.0135” minimum feature clearance cannot be maintained. The positional tolerance of secondary drilled holes to datum ± 0.005”.

Non-Plated Through Slots Non-plated slots will be routed with length, width and positional tolerances of +/- 0.005”.

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Micro Via Maximum panel size: 18” x 24”

Routing, Bevelling and Scoring

Specification Standard Advanced

Routing: Edge-to-edge tolerance: +/- 0.010” +/- 0.008” Edge-to-datum hole tolerance: +/- 0.005” +/- 0.0035” Minimum internal radius: 0.031” 0.0155” Minimum external radius: None None Max. routed hole diameter and tolerance:

1.250” +/- 0.010” 1.250” +/- 0.005”

Min. routed hole diameter and tolerance:

0.250” +/- 0.005” 0.250” +/- 0.003”

Preferred router bits: 0.093”

1/32”, 1/8”, 0.040”, 0.050”, 1mm

Scoring: Minimum web thickness: 0.004” Available scoring angles: 30° 20°, 45°, 60° Spacing between V-sore to copper

25 mils 20 mils

Web thickness tolerance: +/- 0.005” +/- 0.003” Location tolerance: +/- 0.005” Jump score capability: Yes

Edge bevelling: Available angles: 20°, 30°, 35°, 45° 15° - 180° Angle tolerance: +/- 2° Available depths: 0.015” to 0.075” Depth tolerance: +/- 0.010”

Table 11 – Routing, Beveling and Scoring

Routing Minimum drilled datum-to-routed edge tolerance: +/- 0.005”. Minimum routed edge-to-routed edge tolerance: +/- 0.010”. NC Routed slots: Minimum length & width tolerance: +/- 0.005”. Minimum position tolerance: +/- 0.005”. Slots must show a radius at the top and the bottom. Preferred router bits: 0.093”, 0.062” Breakaway tab attachments should be spaced apart between 1.00” and 2.50”.



Breakaway Breakaway

Slots have rounded ends


1.00: - 2.50” BreakawayTab Attachment

Figure 17 - Breakaway Tab Spacing

Minimum tolerance of internally routed features: +/- 0.005”. Minimum individually tooled size : 0.4” x 0.4” PCB. Provide at least 3 non-plated, diagonally placed tooling holes for pinning during profile routing. Minimum distance from tooling hole edge-to-feature edge: 0.015”. Relieve all copper internal to part from route paths by ≥ 0.025”.

Bevelling Maximum length of a bevelled edge: 18”. Minimum bevelled edge-to-opposite edge of PCB dimension: 2.5”. Minimum / maximum PCB thickness: 0.020” / 0.125”.

Depth

Angle

Angle

Width

Figure 18 – Bevel Diagram

Edge bevelling may be performed on the outer edge of the board, a recessed segment of the board, or internal to the board. Inner layer plane layers must be recessed to avoid exposing the

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plane when the boards are bevelled. The following angles and depths may be achieved given sufficient board thickness: 20 degrees by 0.070 inch depth +/-0.015 30 degrees by 0.050 inch depth +/- 0.010 45 degrees by 0.040 inch depth +/- 0.005 Minimum / maximum bevel depth: 0.015” / 0.075”. Bevel angles available: 20, 30, & 45 degrees +/- 5 degrees. Maximum recessed bevel: 1”. Minimum space between gold edge connector and breakaway tab: 0.250”.

Scoring Minimum / maximum panel thickness: 0.020” / 0.250”. Maximum panel size for scoring: 21” x 24” Minimum web thickness tolerance: +/- 0.005”. Score angle: 30 degrees (20 degrees available) Minimum web thickness: 0.004”. Traces should be ≥ 0.050” away from the score line centre on all outer and inner layers. Score line width: 1.15 times the depth. Scoring depth is typically 33% of material thickness. Jump Score: To achieve desired remaining thickness minimum distance of 0.250” for 0.062” thick boards, from scoring start point is required Edge Milling Boards may require edge milling to reduce the circuit board thickness to a specified thickness and tolerance. Typically this is done to allow the board to fit into a card guide when assembled. The milled edge is usually a “step” at the edge of the board. The depth of the step is variable from 0.010” removed to 0.032” remaining. The width of the step is variable from 0.020” to 0.375”. Milling requirements should be limited to simple cuts i.e. two straight edges and simple corners. The path of the mil is limited to a 90 degree turns and internal radii are controlled by cutter diameter (minimum 0.125” and common standard sizes). Double-sided milling is strongly discouraged as edge thickness accuracy is reduced. The finished thickness of the milled edge can be held to +/- 0.008” for a single sided milled edge. For a double-sided milled edge, the finished thickness can be held to +/- 0.010”. The width of the step can be held to +/- 0.010”.

Figure 19 - Edge Milling Diagram

Scoring Section

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This process places grooves on opposite sides of a panel or between boards, for the purpose of de-panellizing by snapping the boards from the panel. Since boards can be ‘butted up” against each other, more boards may be placed on the panel thereby reducing the cost of the board. Design Guidelines Score locations need to be clearly identified on the drawing, with centreline of groove-feature referenced.

• The web thickness (material remaining between opposing grooves) must be specified. Typical web thickness is 0.008” to 0.014”. Minimum web thickness is 0.006”. A different web thickness may be specified within a panel, but not within a single score cut.

• The groove angle should be specified. It is typically 30° however, 20° is also available. • The depth of the groove should not be specified; because it is not controlled, (the web

thickness is controlled). Also, the centering between top and bottom should be specified. • To facilitate depanelization, grooves running to the edge of the panel are recommended. • The groove width for a typical 0.062” board with a 0.013” web is about 0.020” wide at the

surface of the board. Image features need to be pulled back a minimum of 0.040” from the score line centre (image edge) for this board and web thickness.

• Overall board thickness suitable for scoring is 0.030” to 0.125”.

Figure 20 - Scoring Blade Diagram

Achievable Tolerances: Web Thickness……………………………...+/-0.002” Edge to Edge………………………………..+/-0.005” Datum to Edge………………………………+/-0.008”


Soldermask Soldermask Availability A variety of soldermasks have been selected to fill the needs of our customers. The following is a description of the soldermasks currently available. The need for closer tolerances has driven the implementation of Liquid Photoimageable (LPI) Soldermasks.

Specification Standard Advanced LPI Soldermask: Semi-Gloss Matte Average thickness over trace:

0.0005”

Registration tolerance: +/- 0.003” Spacing ( for mask between pads):

0.008” 0.007”

Available colours: Green Clear, Blue, Red, Black Via Plugging: Peel able Soldermask:

PSR 4000MP MacDermid 9490

SR1000

Table 12 – Soldermask Availability

Soldermask is a protective coating that shields selected areas of a PCB from oxidation, handling, and unwanted solder during assembly. When required, allow via plugging to be applied to one side of the board. If Hot Air Solder Levelling is the finish, plugging is preferred after the HASL process. Clearances will be provided for all vias that are tented on the customer soldermask artwork, and the clearance size will be 0.003” per-side over the drilled hole size (with a minimum diameter of 0.020”).

0.003”

Drilled Hole

0.003”

LPI Solder Mask

Outer Layer Pad

ViaVia Plugging Side

Acceptable:0.003” Preferred: to O/L

Drilled Hole

LPI Soldermask(0.020”)

Outer Layer Pad

Non Via Plugging Side

Figure 21 – Via Plugging

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Green is the preferred soldermask colour. Soldermask allows a 0.003” web to be placed between pads in an SMD array, provided the minimum spacing between these pads is 0.007” (by design). Green soldermask allows a 0.003” web to be placed between pads in an SMD array, provided the minimum spacing between these pads is 0.007” (by design). To assure no soldermask on any pad in an SMD array, the minimum soldermask clearance for a surface mount pad is 0.002” per side (not applicable for panel sizes over 18” x 24”). As space permits, a clearance of 0.0025” per side is preferred.

0.0025”Clearance

Green Soldermask(Individual Webs)

0.003”S/M Web

Figure 22 - Soldermask SMD Clearances

Allow 0.030” per-side soldermask clearance for score lines. To prevent soldermask from going into and/or plugging a hole, soldermask clearance should be 0.010” (0.005” per side) larger than the pad size on both sides of the board. The primary coating of LPI soldermask shall not be used to tent holes. Liquid Photoimageable (LPI) Soldermask Liquid Photoimageable soldermask is considered the soldermask of choice for most circuit board product due to its high resolution, excellent electrical properties, and compatibility with surface mount technology. Note: If pads are closer than the minimum, spacing described above, areas between should be free of soldermask, or the hold-down reliability will not be 100%. The strength of soldermask adhesion over gold plating depends on the type of soldermask, type of gold, and the end-user processing conditions. It is recommended that the designer contact us before finalizing design. In certain cases, via plugging on BGA side may be required for tight pitch BGA with electrolytic gold. Tenting of Via Holes with Soldermask Via capping with screened resist Hole “capping/tenting” is available through the via cap process. On boards coated with liquid Photoimageable mask, the vias can be screened with an epoxy or acrylic soldermask material,

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creating a cap over the hole. Artwork modifications necessary for processing are performed as part of the initial tooling. A separate design file must be provided by the customer, which includes only those vias which are to be capped. The customer needs to provide master pad soldermask and via fills, i.e. Soldermask and via pads that are the same size as the outer layer pads. Via capping design constraints The maximum finished hole size for via capping is 0.020” diameter (preferred drill diameter 0.021 inch) Generally, the non-test vias are capped on the topside of the board. Thermal (epoxy) via caps will have a raised surface of approximately 0.0017” +/-0.004” inch above the outer layer copper pad. This is to provide the via hole being capped is not plated shut or plugged with HASL (solder). In this case, due to trapped air between the via cap and plug, the via cap may “dome” during the cure process, thus creating height 0.0035”. UV (acrylic) via cap will have a raised surface of approximately 0.0019” +/-0.0004” inch above the outer layer copper pads. Unlike Thermal (epoxy), UV (acrylic) is not influenced by plated or HASL (solder) plugged holes, therefore the via cap height will remain constant. Note: via cap height thickness measurements may include HASL (solder) and/or permanent soldermask thickness. For product that receives either immersion silver or tin, UV (acrylic) via cap material must be used and applied after the surface finish.

Legend Marking

Specification Standard Advanced Complex Legend: Epoxy Epoxy Epoxy Colours: White Yellow, Black Custom Colours Smallest line width: 0.006” 0.005” 0.004” Location accuracy: +/- 0.010” +/- 0.005” +/-.003”

Table 13 - Legend Marking Specifications

To ensure all letters, numbers, and figures are legible on the finished board, character line widths should be greater than 0.006” and at least 0.030” high. Space letters at least 0.008” apart so they don’t bleed together. No legend nomenclature should overlap a copper pad or plane area. This is especially important for surface mount pads and fiducials. White is the standard legend ink colour. Use the fabrication print notes to specify special features to be screened onto the board. All legend should be kept 0.003” (min) away from soldermask clearance. Nomenclature Letter size: minimum 0.006” line width (screened nomenclature) 0.004” for Photoimageable. Recommended Letter Sizes: Line Width Height and Width 0.004” (LPI) 0.020” 0.005” (LPI) 0.025” 0.006” 0.030” 0.008” 0.035” 0.010” 0.040” Note: nomenclature placed over parallel or heavy copper traces may have poor legibility.

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Colour: white (epoxy) preferred, Yellow (epoxy), Black and White (Liquid Photoimageable Ink (LPI) is also available). Nomenclature over solder (HASL) will have poor adherence Nomenclature placed over bare copper before HASL and immersion silver/tin will have an apparent copper “halo” after the HASL or Immersion Silver/Tin. Artwork needs to be modified if it is not acceptable to the customer.

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Surface Finishes

Table 14 – Surface Finish Comparison

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Table 15 – Surface Finish Reference Guide


Electrical Test

Specification Standard Advanced Electrical test capabilities:

Pitch: 0.020” 0.016”, 0.010” Fixture types: Flying Probe Flying Probe Test voltages available: 10 - 500 volts 10 - 500 volts Resistivity testing: Open resistance: 20 Ω 5 Ω Short resistance: 10 MΩ minimum 25 MΩ Netlist capability: Yes ( Gerber netlist

extraction ) IPC D 356 or Mentor neutral

file reference Hi-pot testing: 500 to 1000 volts 500 to 1000 volts Controlled impedance: 10% ± 5%

Table 16 – Electrical Test Parameters

Electrical testing ensures electrical continuity & isolation of all nets. As the designer, keep in mind the following parameters: Continuity Test Available Continuity Test Specifications: Continuity: 5 to 500Ω. Isolation: 2 to 100 MΩ. Voltage: 10 to 500V

Preferred Continuity Test Specifications: Continuity: 20Ω. Isolation : 10 MΩ. Voltage : 100 V.

Netlist Programs For electrical testing, supply a netlist file from which the required test program will be derived. This should be in IPC-D-356 format or as a Mentor Neutral file. If a netlist isn’t supplied, one will be generated from the Gerber data. All test points should be in the netlist. Hi-Pot Test Available Hi-Pot Test Specifications: Voltage: 500 to 1000 V DC.

Duration: 2 to 30 sec. Preferred Hi-Pot Test Specifications: Voltage: 500 V. Duration: 2 sec. Three main test parameters are of interest to customers: Test Voltage - the amount of power applied to the circuit for testing. Continuity Resistance - the maximum resistance allowable for a circuit. Any higher resistance indicates a possible open circuit.

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Isolation Resistance - the minimum resistance allowable between separate electrical entities. Any lower resistance indicates a possible short. Testable settings for these parameters are system dependant.

PCB Data Requirements

Customer Data Must Include:

README.TXT file , Legible fabrication file , Drill (NC) file , Aperture list ,

All Gerber Files , CAD netlist test data Compression: ZIP, TAR-UNIX Data Format: ODB ++, RS-274-X, RS-274-D with aperture list Drill File: EXCELLON Fabrication Drawing: HPGL, DXF or PDF format Netlist: IPC-D-356 or Mentor Neutral

Table 17 – Data Requirements

Customer Data Must Include: A README.TXT file (See table 10) A legible fabrication print files (see Figure 33). A drill (NC) file. An aperture list file. No hard copies. One for all Gerber files. Rotation, shape, and size of all features must be clearly defined. All Gerber files CAD netlist test data. For a first time order fabrication specification must be sent.

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Notes1)2)3)

Critical outlinedimensions

Legible symbolsfor all hole sizes

Hole chart thatincludes symbol,hole size, qty, plateor no plate, andtolerance

Fabricationdrawing notes

Title block thatincludes part #,revision #,tolerance block,date.

Dielectricdimensions andstack-up order

Figure 23 - Fabrication Drawing Requirements

NOTE: Accurate PCB data is essential to manufacture a perfect PCB. It is important that the blueprint revision, film revision, and drill tape revisions all agree, and that the part numbers on each are identical. Also, any special instructions should be instructed in the README.TXT file.

Preferred Acceptable

Compression ZIP, RAR PKARC, TAR Data Format ODB ++ RS-274-X, RS-274-D

(GERBER) plus an Aperture List

Drill File EXCELLON GERBER Fabrication Drawing HPGL, DXF, AUTOCAD, PDF POSTSCRIPT Netlist IPC-D-356 MENTOR NEUTRAL FILE

Table 18 – File Formats

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File Name: README.TXT Format: ASCII, or MS/Word Contents: Company name Division name (and / or location) List of files in the package Board Part Number and Revision Purpose of the submittal: QUOTATION and/or PRODUCTION? Technical Contact (name and best times to call) Phone number Fax number EMAIL address (If available) Special Instructions

Table 19 – Preferred Readme File Contents

Common Data Issues Two types of data issues are frequently encountered: critical and non-critical. Critical data issues can be substantial enough to stop the tooling process, while non-critical data issues simply result in additional edits that need to be performed. The following lists present the most common errors. Minimization of these issues will decrease tool generation time.

Critical Problems Bad Compression (cannot unzip). Missing FAB prints of files. Formats not recognized. FAB prints are not legible. No README.TXT file. Information does not match. Missing Gerber files. Outside DAPC manufacturing capabilities. Missing Drill Files. Missing Aperture List. Missing “D” codes. Unclear aperture list Revisions do not match.

Non-Critical Problems Netlist not supplied. No README.TXT Design, as supplied, violates the OEM provided specifications / documentation? Design, as supplied, violates the Contract Assemblers provided specifications? Violations on rules that improve yield.

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Table 20 – Design Capabilities

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Figure 24 – PCB Manufacturing Process

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42

Basic Copper Clad

Laminate

LaminateResist

Expose Photo Image

Develop

Etch theCopper

PlateCopper & Tin

Basic Copper Clad

Laminate

Plate AdditionalCopper

LaminateResist

Expose Photo Image

Etch & Strip Develop Image

Pattern Plating Process

Panel Plate Process

Outer Layer Plating Process

Strip the Tin

Strip Resist

Strip - Etch - Strip

Figure 25 – Outer Layer Plating Processes

1. Pattern Plate DAPC fabricates all printed circuit boards with the pattern plating process. This process has major advantages in that only the base copper is required to be etched. This process yields a finer, better defined line. One possible disadvantage is the variations in track height due to surface density. 2. Panel Plate This plating fabrication method eliminates most of the copper plating distribution issues but now the base foil must be etched. This makes maintaining fine line definition and consistency difficult to maintain.


The allowance for etching of plated designs is as follows:

Copper Weight Typical

Reduction in line width from

nominal

Minimum design line

width

0.5 ounce 0.0007” 0.004” 1.0 ounce 0.0014” 0.005” 2.0 ounce 0.0028” 0.008”

Table 21 – Etch Loss

Inner Layer Process

Basic Copper Clad

Laminate

Laminate Resist

Expose Photo Image Which

Polymerized the Resist

Develop StripResist

Etch Copper

Develop - Etch - Strip Figure 26 – Inner Layer Process

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Glossary of Terms

A

Activating: A treatment that renders nonconductive material receptive to Electroless deposition.

Active Components: Semiconductor devices, such as transistors and diodes that can change its basic characteristics in a powered electrical circuit, such as amplifiers and rectifiers.

Additive Process: A process for obtaining conductive patterns by the selective deposition of conductive material on clad or unclad base material.

Analog Circuit: An electrical circuit that provides a continuous quantitative output as a response from its input.

Annular Ring: The width of the conductor pad surrounding a drilled hole.

Aperture Information: This is a text file describing the size and shape of each element on the board. These are also known as the D-code list. These lists are not necessary if your files are saved as Extended Gerber with embedded Apertures (RS274X)

Array: A group of elements or circuits (or circuit boards) arranged in rows and columns on a base material.

Artwork: Printed circuit design. An accurately scaled configuration used to produce the artwork master or production master.

Artwork Master: The photographic film or glass plate that embodies the image of the PCB pattern, usually on a 1:1 scale.

Aspect Ratio: The ratio of the board thickness to the smallest-hole diameter of the printed circuit board.

Assembly: A number of parts, subassemblies, or any combination thereof joined together.

Assembly File: A drawing describing the locations of components on a PCB.

Automated Optical Inspection (AOI): Visual inspection of the circuit board using a machine scanner to assess workmanship quality.

Automated Test Equipment (ATE): Equipment that automatically tests and analyzes functional parameters to evaluate performance of the tested electronic devices.

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B

BBT: Bare Board Test. B-Stage Material: Sheet material impregnated with a resin cure to an intermediate stage (B stage resin) Prepreg is the preferred term.

B-Stage Resin: A thermosetting resin that is in an intermediate state of cure.

Backplanes & Panels: Interconnection panels onto which printed circuits, other panels, or integrated circuit packages can be plugged or mounted. Typical thickness is 0.125” – 0.300”.

Backup Material: A layer composed of phenolic, paper composite, or aluminium foil-clad fibre composite used during fabrication to prevent Burrs and to protect the drill table.

Ball Grid Array (BGA): A SMD package in which solder ball interconnects cover the bottom surface of the package.

Bare Board: An unpopulated PCB.

Barrel: The cylinder formed by plating through a drilled hole.

Base Copper: The thin copper foil portion of a copper-clad laminate for PCB’s. It can be present on one or both sides of the board.

Base Copper Weight: see Copper Foil

Base Laminate: The dielectric material upon which the conductive pattern may be formed. The base material may be rigid or flexible.

Base Material: The insulating material upon which a conductive pattern may be formed. It may be rigid or flexible or both. It may be a dielectric or insulated metal sheet.

Bed-of-nails Fixture: A test fixture consisting of a frame and a holder containing a field of spring-loaded pins that make electrical contact with a planar test object (i.e. a PCB).

Bevel: An angled edge of a printed board.

Bleeding: A condition in which a plated hole discharges process materials of solutions from voids and crevices.

Blind Via: A via hole from an external layer to an internal layer. It is copper plated to enable it to conduct current, but it does not penetrate the board from top to bottom.

Blister: A localized swelling and separation between any of the layers of a laminated base material, or between base material and conductive foil. It is a form of delamination.

Blow Hole: A solder joint void caused by outgassing of process solutions during thermal cycling.

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Board Thickness: Standard base thickness is 1/16 which is also called out as .062 or .059. Other standard sizes are 0.031, 0.093, 0.125 and 0.256. Typical tolerance is 10% of the given thickness. We can generally make any other thickness.

Book: A specified number of stacks of Prepreg plies which are assembled for Curing in a lamination press.

Bond Strength: The force per unit area required to separate two adjacent layers of a board by a force perpendicular to the board surface.

Bow and Twist: The deviation from flatness of a board characterized by a roughly cylindrical or spherical curvature such that if the board is rectangular its four corners are in the same plane.

Breakdown Voltage: The voltage at which an insulator or dielectric ruptures, or at which ionization and conduction take place in a gas or vapour.

Bridging, Electrical: The formation of a conductive path between two insulated conductors such as adjacent traces on a circuit board.

Built-In Self Test: An electrical testing method that allows the tested devices to test itself with specific added-on hardware.

Buried Via: A via hole between internal layers that electrically conducts (by a copper plating process) a current from layer to layer, it does not extend to the surface of the printed board.

Burr: A ridge left on the outside copper surface after drilling.

C

CAD: See Computer Aided Design.

CAM: See Computer Aided Manufacturing.

CAM Files: The files used for manufacturing PCB including Gerber file, NC Drill file and Assembly Drawings.

CEM: A punchable material (paper) used in single-sided boards but not suited for plated through-holes. CEM stands for composite epoxy material.

C-Stage: The condition of a resin polymer when it is solid state with high molecular weight.

Capacitance: The property of a system of conductors and dielectrics that permits storage of electricity when potential difference exists between conductors.

Centre-to-Centre Spacing: The nominal distance between the centres of adjacent features or traces on any layer of a printed circuit board. Also known as “pitch”.

Ceramic Ball Grid Array (CBGA): A ball grid array package with a ceramic substrate.

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Chamfer: A broken corner to eliminate an otherwise sharp edge.

Characteristic Impedance: A compound measurement of the resistance, inductance, conductance and capacitance of a transmission line expressed in ohms. In printing wiring its value depends on the width and the thickness of the conductor, the distance from the conductor to ground plane(s), and the dielectric constant of the insulating media.

Chase: The aluminium frame used in screening inks onto the board surface.

Check Plots: A scaled paper or Mylar image of the database after placement and routing have been completed.

Chip-on-Board (COB): A configuration in which a chip is directly attached to a printed circuit board or substrate by solder or conductive adhesives.

Chip: The individual circuit or component of a silicon wafer, the leadless form of an electronic component. Circuit: The interconnection of a number of devices in one or more closed paths to perform a desired electrical or electronic function. Circuit Board (PCB/ECB): The general term for a printed or etched circuit board. It includes single, double, or multiple layer boards, both rigid and flexible. Circuitry Layer: A layer of a printed board containing conductors, including ground and voltage planes. Clad or Cladding: A relatively thin layer or sheet of metal foil that is bonded to a laminate core to form the base material for printed circuit boards. Cleanroom: A room in which the concentration of airborne particles is controlled to specified limits. Clearances: A clearance (or isolation) is a term to describe the space from power/ground layer copper to through hole. To prevent shorting, ground and power layer clearances need to be .023”larger then the finish hole size for the inner layers. This allows for registration, drilling, and plating tolerances.

Coating: A thin layer of material, conductive, magnetic or dielectric, deposited on a substance surface.

Coefficient of Thermal Expansion (CTE): The ratio of dimensional change of an object to the original dimension when temperature changes, expressed in %/ºC or ppm/ºC.

Component: An electronic device, typically a resistor, capacitor, inductor, or integrated circuit (IC), that is mounted to the circuit board and performs a specific electrical function.

Component Hole: A hole used for the attachment and electrical connection of a component termination, such as a pin or wire to the circuit board.

Component Side: The Side of a PCB on which most of components are mounted. Also called the “top side”.

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Computer-Aided Design (CAD): A software program with algorithms for drafting and modeling, providing a graphical representation of a printed board’s conductor layout and signal routes.

Computer-Aided Manufacturing (CAM): The use of computers to analyze and transfer an electronic design (CAD) to the manufacturing floor.

Computer-Integrated Manufacturing (CIM): Software that takes assembly data from a CAD or CAM package and, using a pre-defined factory modeling system, outputs routing of components to machine programming points and assembly and inspection documentation.

Conductor: A thin layer conductive area on a PCB surface or internal layer usually composed of lands (to which component leads are connected) and paths (traces).

Conductor Base Width: The conductor width at the plane of the surface of the base material. Also see Conductor Width.

Conductor-to-Hole Spacing: The distance between the edge of a conductor and the edge of hole.

Conductor Spacing: The distance between adjacent edges (not centreline to centreline) of isolated conductive patterns in a conductor layer.

Conductor Thickness: The thickness of the conductor including all metallic coatings.

Conductor Width: The observable width of the pertinent conductor at any point chosen at random on the printed circuit board.

Conformal Coating: An insulating protective coating that conforms to the configuration of the object coated and is applied on the completed board assembly.

Connector Area: The portion of the circuit board that is used for providing electrical connections.

Contaminant: An impurity or foreign substance whose presence on printed wiring assemblies could electrolytically, chemically, or galvanically corrode the system.

Continuity: An uninterrupted flow of electrical current in a circuit.

Controlled Impedance: See Characteristic Impedance

Coordinate Tolerancing: A method of tolerancing hole locations in which the tolerance is applied directly to linear and angular dimensions, usually forming a rectangular area of allowable variation. Also see, Positional Limitation Tolerancing and True Position Tolerance.

Copper Foil (Base Copper Weight): Coated copper layer on the board. It can be either characterized by weight or thickness of the coated copper layer. For instance, 0.5, 1 and 2 ounces per square foot are equivalent to 0.0007, 0.0014 and 0.0028 inch thick copper layers.

Copper (finished copper): This is how much copper your board will have on its surface. It is the copper foil thickness, plus plated copper, minus surface preparation. It is given in oz/per sq foot. 1 oz=a minimum of .0012-.0014” thickness

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Copper Invar Copper: A multilayer metal alloy of a specific proportion, laminated together without the use of an insulating adhesive, thereby retaining a thermal and electrical conductive property.

Core Thickness: The thickness of the laminate base without copper.

Corrosive Flux: A flux that contains corrosive chemicals such as halides, amines, inorganic or organic acids that can cause oxidation of copper or tin conductors.

Cosmetic Defect: A defect such as a slight change in its usual colour that doesn’t affect a board’s functionality.

Cover Lay, Cover Layer, Cover Coat: Outer layer(s) of insulation material applied over the conductive pattern on the surface of a printed circuit board.

Crazing: A condition existing in the base material in the form of connected white spots or “crosses” on or below the surface of the base material, reflecting the separation of fibres in the glass cloth and resin material.

CTE: Coefficient of thermal expansion. The measure of the amount a material changes in any axis per degree of temperature change.

Curing: The irreversible process of polymerizing a thermosetting epoxy in a temperature-time profile.

Curing Time: The time needed to complete curing of resin at a certain temperature.

Current Carrying Capacity: The maximum current which can be carried continuously, under specified conditions, by a conductor without causing degradation of electrical or mechanical properties of the printed circuit board.

Cut lines: The cut line is going to be used to program the router path and it represents the board outside edge.

D

DFSM: Dry Film Solder Mask. Coating material (dry-film resist) applied to the printed circuit board via a lamination process to protect the board from solder or plating.

Date Code: This will have the year and week of manufacture of the board. It can be etched on the board or part of the silkscreen.

Datum Reference: A defined point, line, or plane used to locate the pattern or layer for manufacturing, inspection, or for both purposes.

Deburring: Process of removing burrs after drilling.

Defect: Any non-conformance to specified requirements by a unit or product.

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Definition: The accuracy of reproduction of pattern edges, especially in a printed circuit relative to the original mater pattern.

Delamination: A separation between any of the layers of the base of laminate or between the laminate and the metal cladding originating from or extending to the edges of a hole or edge of board.

Design Rule: Guidelines that determine automatic conductor routing behaviour with respect to specified design parameters.

Design Rule Checking: The use of a computer program to perform continuity verification of all conductor routing in accordance with appropriate design rules.

Desmear: The removal of friction-melted resin and drilling debris from a hole wall.

Develop: An imaging operation in which unpolymerized (unexposed) photoresist is dissolved or washed away to produce a copper board with a photoresist pattern for etching or plating.

Dewetting: A condition which occurs when molten solder has coated a surface and then recedes, leaving irregular shape mounds of solder separated by areas covered with thin solder film; base material is not exposed.

Die: Integrated circuit chip as diced or cut from a finished wafer.

Die Bonder: The placement machine bonding IC chips onto a chip-on-board substrate.

Die Bonding: The attachment of an IC chip to a substrate.

Dielectric: An insulating medium between conductors.

Dielectric Constant: Is the ratio of permittivity of the material to that of a vacuum (referred to as a relative permittivity).

Differential Impedance: Refers to the impedance of a pair of conductors when driven in a differential mode, that is, when the conductors are driven by signals that have opposite polarity edges.

Digitizing: The converting of feature locations on a flat plane to a digital representation in X-Y coordinates.

Dimensional Stability: A measure of the dimensional change of a material that is caused by factors such as temperature changes, humidity changes, chemical treatment, and stress exposure.

DIP: Dual in-line package with two rows of leads from the base in standard spacing between the leads and row.

Double-Sided Assembly: PCB assembly with components on both sides of the substrate. Double-Sided Board: A circuit board with conductive patterns on both sides.

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Drawing or Print: This usually includes a drawing of the board outline with symbols marking individual drill sizes and corresponding board locations, dimensions, and any other pertinent manufacturing information unique to the board (copper weight, board thickness, stack-up specifics, etc.) Drill file (Excellon Drill File): It will have x and y coordinates with tool sizes viewable in any text editor. It is the file that governs your finished hole sizes. Drilling: The act of forming holes (vias) in a substrate by mechanical or laser means.

Drills, Circuit Board: Solid carbide cutting tools with four facet points and two helical flutes designed specifically for the fast removal of chips in extremely abrasive materials.

Dry - Film Resists: Coated photosensitive film on the copper foil of PCB using photographic methods. They are resistant to electroplating and etching processes in the manufacturing process of PCB.

Dry Film Solder Mask: A solder coating material applied to the PCB, through a lamination process to protect the board from solder or plating.

DRC: Design rule check.

E

Edge Bevel: A bevel operation performed on edge connectors to improve their wear and ease of installation.

Edge-Board Connector: A connector designed specifically for making removable and reliable interconnection between the edge board contacts on the edge of a printed board and external wiring.

Edge Connector: A connector on the circuit-board edge in the form of gold plated pads or lines of coated holes used to connect other circuit board or electronic device.

Edge Clearance: The smallest distance from any conductors or components to the edge of the PCB.

Edge Dip Solderability Test: A solderability test performed by taking a specially-prepared specimen, fluxing it with a non-activated rosin flux, and then immersing it into a pot of molten solder at a pre-determined rate of immersion for a pre-determined dwell time, and then withdrawing it at a pre-determined rate.

Electrical Test (1 sided / 2/sided): Testing is primarily to test for opens and shorts.

Electroless deposition: The chemical coating of a conductive material onto a base material surface by reduction of metal ions in a chemical solution without using electrodes compared to electroplating.

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Electroless Copper: A thin layer of copper deposited on the plastic or metallic surface of a PCB from an auto-catalytic plating solution (without the application of electrical current).

Electroplating: The electrochemical deposition of reduced metal ions from an electrolytic solution onto the cathode by applying a DC current through the electrolytic solution between two electrodes, cathode and anode, respectively.

Entry Material: A thin layer of material composed of phenolic, aluminium foil, or paper that is placed on top to the panel prior to drilling, to improve drill accuracy and prevent burrs and dents.

Epoxy: A family of thermosetting resins. Epoxies form a chemical bond to many metal surfaces.

Epoxy Smear: Epoxy resin that has been deposited on edges of copper in holes during drilling either as uniform coating or in scattered patches. It is undesirable because it can electrically isolate the conductive layers from the plated-through-hole interconnections.

ESR: Electro-statically applied Solder Resist.

Etch: Chemical removal of metal (copper) to achieve a desired circuit pattern.

Etch Factor: The ratio of the depth of etch (conductor thickness) to the amount of lateral etch (undercut).

Etchback: The controlled removal of all components of the base material by a chemical process acting on the sidewalls of plated-through holes to expose additional internal conductor areas.

Etching: The process of removing unwanted metallic substances via chemical means.

Even Mode Impedance: The impedance of a single line in a coupled-line pair when a common-mode signal drives both conductors within the pair

F

Fiducial: Etched features or drilled hole used for optical alignment during assembly operations.

Film Artwork: A positive or negative piece of film containing a circuit, soldermask, or nomenclature pattern.

Fine Pitch: Fine pitch is more commonly referred to surface-mount components with a lead pitch of 25 mils or less.

Finger: A gold-plated terminal of a card-edge connector. Also see Gold Finger. Files Gerber: Industry standard format for files used to generate artwork necessary for circuit board imaging.

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First Article: A sample part or assembly manufactured prior to the start of production for the purpose of ensuring that the manufacturer is capable of producing a product that will meet specified requirements.

Fixture: A device that enables interfacing a printed circuit board with a spring-contact probe test pattern.

Flat: A standard size sheet of laminate material which is processed into one or more circuit boards.

Flux: The material used to remove oxides from metal surfaces and enable wetting of the metal with solder.

Flying Probe: A testing device that uses multiple moving pins to make contact with two spots on the electrical circuit and send a signal between them, a procedure that determines whether faults exist.

FR-1: A paper material with a phenolic resin binder. FR-1 has a Tg of about 130°C.

FR-2: A paper material with phenolic resin binder similar to FR-1 but with a Tg of about 150°C.

FR-3: A paper material that similar to FR-2 except that an epoxy resin is used instead of phenolic resin as a binder.

FR-4: Flame Retardant laminate made from woven glass fibre material impregnated with epoxy resin.

Functional Test: The electrical testing of an assembled electronic device with simulated function generated by the test hardware and software.

Fused Coating: A metallic coating (usually tin or solder alloy) which has been melted and solidified, forming a metallurgical bond to the base material.

G

G10: A laminate consisting of woven epoxy-glass cloth impregnated with epoxy resin under pressure and heat. G10 lacks the anti-flammability properties of FR-4. Used mainly for thin circuits such as in watches.

Gerber File: Data file used to control a photoplotter.

Glass Transition Temperature: The temperature at which an amorphous polymer (or the amorphous regions in a partially crystalline polymer) changes from a hard and relatively brittle condition to a viscous or rubbery condition. When this transition occurs, many physical properties undergo significant changes. Some of those properties are hardness, brittleness, coefficient of thermal expansion, and specific heat.

Golden Board: See Known Good Board.

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Ground Plane: A conductor layer, or portion of a conductor layer, used as a common reference point for circuit returns, shielding, or heat sinking.

GI: The woven glass fibre laminate impregnated with polyimide resin.

Gold Finger: The gold-plated terminal of a card-edge connector. Also see Finger. Approximately 150-200 micro-inches minimum of nickel under a minimum 30micro-inches of gold on top.

Grid: An orthogonal network of two sets of parallel, equidistant lines used for locating points on a printed circuit board.

H

HASL: A method of coating exposed copper with solder by inserting a panel into a bath of molten solder, then passing the panel rapidly past jets of hot air.

HDI (High Density Interconnect): Ultra fine-geometry multi-layer PCB constructed with conductive microvia connections. These boards also usually include buried and/or blind vias and are made by sequential lamination.

Haloing: Mechanically-induced fracturing delamination on or below the surface of the base material; it is usually exhibited by a light area around holes, or other machines areas, or both.

Heat Sinks: Devices used to absorb or transfer heat away from heat-generating parts/components on a PCB.

Hermetic: Airtight sealing of an object.

Hole Breakout: A condition in which a hole is partially surrounded by the land.

Hole Density: The number of holes per unit area on a PCB.

Hole Pattern: The arrangement of all holes in a printed board with respect to a reference point.

Hole Void: A void in the metallic deposit of a plated-through hole exposing the base material.

I

In-Circuit Test: Electrical test of individual component or part of the circuit in a PCB assembly instead of testing the whole circuit.

Image: That portion on artwork masters, working tools, silkscreens or photomasks that would be considered the photographic image. Also would include images created with photo-resists or silk-screening techniques. Generally, “one image” refers to a single circuit board image, thus there may be several images per array.

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Imaging: The process by which panelization data are transferred to the photoplotter, which in turn uses light to transfer an image circuitry pattern onto the panel.

Impedance: The total passive opposition offered to the flow of electric current. This term is generally used to describe high-frequency circuit boards.

Ink: Common term for screen resist.

Inkjetting: The dispersal of well-defined ink “dots” onto a PCB. Inkjet equipment uses heat to liquefy a solid ink pellet and change the ink into a liquid, which is then dropped via a nozzle onto the printed surface, where it quickly dries.

Inner layers: The internal layers of laminate and metal foil within a multilayer board.

Inspection Overlay: A positive or negative transparency made from the production master and used as an inspection aid.

Insulation Resistance: The electrical resistance of an insulating material that is determined under specific conditions between any pair of contacts, conductors, or grounding devices in various combinations.

Interstitial Via Hole: An embedded through-hole with connection of two or more conductor layers in a multilayer PCB.

J Jumper Wire: An electrical connection formed by wire between two points on a printed board adder after the intended conductive pattern is formed.

K

Kerf: A widening of the rout path as may be called out on the blueprint. Allows extra space for hardware to be attached to the board.

Keying Slot: A slot in a printed circuit board that polarizes it, thereby permitting it to be plugged into its mating receptacle with pins properly aligned, but preventing it from being reversed or plugged into any other receptacle.

Known Good Board (KGB): A board or assembly that is verified to be free of defects. Also known as a Golden Board.

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L

Laminate: The plastic material usually reinforced by glass or paper that supports the copper cladding from which circuit traces are created.

Laminate Thickness: Thickness of the metal-clad base material, single- or double-sided, prior to any subsequent processing.

Laminate Void: An absence of epoxy resin in any cross-sectional area that should normally contain epoxy resin.

Laminating Presses, Multilayer: Equipment that applies both pressure and heat to laminate and prepreg to make multilayer boards.

Lamination: The process manufacturing a laminate or PCB using pressure and heat.

Land: The portion of the conductive pattern on printed circuits designated for the mounting or attachment of components. Also called a pad.

Landless Hole: A plated-through hole without land(s). Also referred to as pad-less plated holes.

Layer-to-Layer Spacing: The thickness of dielectric material between adjacent layers or conductive circuitry in a multilayer printed circuit board.

Layers Sequence: Indicates a layer sequence so that we are able to build your order with the correct stack up.

Lay-up: The process in which treated prepregs and copper foils are prior to lamination.

Leakage Current: A small amount of current that flows across a dielectric area between two adjacent conductors.

Legend: A format of printed letters or symbols on the PCB, such as part numbers and product number or logos.

Line: See Conductor Liquid Photoimageable Soldermask (LPI): Liquid Photoimageable solder mask that uses photographic imaging to control a thinner mask deposition than the dry film solder mask. Lot: A quantity of circuit boards that share a common design.

M Major Defect: A defect that is likely to result in failure of a unit or product by materially reducing its usability for its intended purpose.

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Mask: A material applied to enable selective etching, plating, or the application of solder to a PCB. Also called soldermask or resist. Measling: Discrete white spots or crosses below the surface of the base laminate that reflect a separation of fibres in the glass cloth at the weave intersection. Metal Foil: The plane of conductive material of a printed board from which circuits are formed. Metal foil is generally copper and is provided in sheets and rolls. Micro-sectioning: The preparation of a specimen of a material, or materials that is used in metallographic examination. This usually consists of cutting out a cross-section followed by encapsulation, polishing, etching, and staining. Microstrip – a specific transmission line on a PCB where the signal trace is on an outside surface of the PCB and is spaced above a ground plane by the dielectric material, such as FR-4.

Microvia: Usually defined as a conductive hole with a diameter of 0.005” or less that connects layers of a multilayer PCB. This term is often used to refer to any small geometry connecting holes created by laser drilling.

Mil: One-thousandth of an inch (0.001”).

Minimum Annular Ring: The minimum metal width, at the narrowest point, between the circumference of the hole and the outer circumference of the land. This measurement is made to the drilled hole on internal layers of multilayer printed circuit boards and to the edge of the plating on outside layers of multilayer boards and double-sided boards.

Minimum Conductor Width: The smallest width of any conductors, such as traces, on a PCB.

Minimum Conductor Space: The smallest distance between any two adjacent conductors, such as traces, in a PCB.

Minimum Electrical Spacing: The minimum allowable distance between adjacent conductors that is sufficient to prevent dielectric breakdown, corona, or both, between the semiconductors at any given voltage and altitude.

Minor Defect: A defect that is not likely to result in the failure of a unit or product or that does not reduce its usability for its intended purpose.

Mis-Registration: The lack of dimensional conformity between successively-produced features or patterns.

Multilayer PCB: Circuit boards consisting three or more layers of printed circuits separated by laminate layers and bonded together with internal and external interconnections.

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N Nail Heading: The flared condition of copper on the inner conductor layers of a multilayer board caused by hole drilling. NC Drill: Numeric Control drill machine used to drill holes at exact locations of a PCB specified in NC Drill File. Negative: An artwork master or production master in which the intended conductive pattern is transparent to light, and the areas to be free from conductive material are opaque. Netlist: List of parts and their connection points which are connected in each net of a circuit. Node: A pin or lead to which at least two components are connected through conductors. Nomenclature: Identification symbols applied to the board by means of screen printing, ink jetting, or laser processes. Non-functional Land: A land on internal or external layers not connected to the conductive pattern on its layer. NPTH: Non-plated trough-hole. Number of Holes: This is the total number of holes in the board. It has an influence on the price if it increases drilling time. Smallest hole we can mechanically drill is .008

O

Odd Mode Impedance: The impedance of a single line in a coupled-line pair when a differential signal drives both conductors within the pair.

Open: A circuit interruption (such as a broken track) that results in an incomplete path for current flow.

Outer layer: The top and bottom sides of any type of circuit board.

Outgassing: De-aeration or other gaseous emission from a printed circuit board when exposed to the soldering operation.

Overhang: Increase in printed circuit conductor width caused by plating build-up or by undercutting during etching.

Oxide: An oxide coating on copper layers to enhance the bond or peel strength of internal layers when laminating a multilayer board, by ensuring that resin will have extra surface to adhere to

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P

Pad: The portion of a conductive pattern for connection and attachment of electronic components on the PCB. Also called Land.

Panel: A rectangular sheet of base material or metal-clad material of predetermined size that is used for the processing of printed boards, and when required, one or more test coupons.

Panel Plating: The electrolytic plating of the entire surface of a panel (including holes).

Pattern: The configuration of conductive and nonconductive materials on a panel or printed board. Also, the circuit configuration on related tools, drawings, and masters.

Pattern Plating: The selective plating of a conductive pattern.

Peel Strength: The force per unit width required to peel the conductor or foil from the base material.

Permittivity: Is the measure of the ability of a material to store electrical energy when exposed to an electrical field.

PCB: Printed Circuit Board. Also called Printed Wiring Board (PWB).

PCMCIA: Personal Computer Memory Card International Association.

PEC: Printed Electronic Component.

Photomask: A silver halide or diazo image on a transparent substrate that is used to either block or pass light.

Photoplotter: Device used to generate artwork photographically by plotting objects (as opposed to copying an entire image at once as with a camera) onto film for use in manufacturing printed circuit boards.

Photo Print: The process of forming a circuit pattern image by hardening a photosensitive polymeric material by passing light through a photographic film.

Photoresist: A light-sensitive material that is used to establish an image by exposure to light and chemical development.

Phototool: A transparent film that contains the circuit pattern, which is represented by a series of lines of dots at a high resolution.

Pick-and-Place: A manufacturing operation of assembly process in which components are selected and placed onto specific locations according to the assembly file of the circuit.

Pilot Order: First production order going through process.

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Pinhole: A minute hole through a layer or pattern.

Pitch: The centre-to-centre spacing between conductors, such as pads and pins, on a PCB.

Plastic Leaded Chip Carrier (PLCC): A component package with J-leads.

PTH (Plated Through-Hole): A hole plating on its walls that makes an electrical connection between conductive layers, external layers, or both, of a printed board.

Platen: A flat plate of metal within the lamination press in between which stacks are placed during pressing.

Plating: Chemical or electromechanical deposition of metal on a pattern.

Plating, Electroless: A method of metal deposition employing a chemical reducing agent present in the processing solution. The process is further characterized by the catalytic mature of the surface which enables the metal to be plated to any thickness.

Plating Resist: Material deposited as a covering film on an area to prevent plating on this area.

Plating Void: The area of absence of a specific metal from a specific cross-sectional area.

Plotting: The mechanical converting of X-Y positional information into a visual pattern such as artwork.

Polyimide Resins: High temperature thermoplastics used with glass to produce printed circuit laminates for multilayer and other circuit applications requiring high temperature performance.

Polymerize: To unite chemically two or more monomers or polymers to form a molecule with a higher molecular weight.

Positional Limitation Tolerancing: Defines a zone within which the axis or centre plane of a feature is permitted to vary from true (theoretically exact) position.

Preclean: Cleaning steps taken prior to an operation to ensure success of the operation.

Prepreg: Sheet material consisting of glass cloth impregnated with a synthetic resin, such as epoxy or polyimide, partially cured to the B stage.

Press-Fit Contact: An electrical contact which can be pressed into a hole in an insulator, printed board (with or without plated-through holes), or a metal plate.

Pressing: The process by which a combination of heat and pressure are applied to a book, thereby producing fully cured laminated sheets.

Printed Board: The general term for completely processed printed circuit or printed wiring configurations. It includes single, double-sided, and multilayer boards, both rigid and flexible.

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Printed Circuit: A conductive pattern that comprises printed components, printed wiring, or a combination thereof, all formed in a predetermined design and intended to be attached to a common base. (In addition, this is a generic term used to describe a printed board produced by any of a number of techniques).

Printed Wiring Board: A part manufactured from rigid base material upon which completely processed printed wiring has been formed.

Production Master: A 1:1 scale pattern which is used to produce one or more printed boards (rigid or flexible) within the accuracy specified on the master drawing. (a) Single-Image Product Master – A production master used in the process of making a single printed circuit board. (b) Multiple-Image Production Master – A production master used in the process of making two or more printed circuit boards simultaneously.

Pulse Plating: A method of plating that uses pulses instead of a direct current.

R

Readme Files: A text file included in the zip file. It provides a reference for your order. If you have a specific need or important point it is generally put in the readme file.

Reflowing: The melting of an electro-deposit followed by solidification. The surface has the appearance and physical characteristics of being hot-dipped.

Reflow Soldering: Melting, joining and solidification of two coated metal layers by application of heat to the surface and predeposited solder paste.

Registration: The degree of conformity to the position of a pattern, or a portion thereof, a hole, or other, feature to its intended position on a product.

Residue: An undesirable substance remaining on a substrate after a process step.

Resin (Epoxy) Smear: Resin transferred from the base material onto the surface of the conductive pattern in the wall of a drilled hole.

Resin-Starved Area: A region in a printed circuit board that has an insufficient amount of resin to wet out the reinforcement completely evidenced by low gloss, dry spots or exposed fibres.

Resist: Coating material used to mask or to protect selected areas of a pattern from the action of an etchant, solder, or plating. Also called soldermask or mask.

Resistivity: The ability of a material to resist the passage of electrical current through it.

Reverse Image: The resist pattern on a printed circuit board enabling the exposure of conductive areas for subsequent plating.

Rework: Reprocessing that makes articles conform to specifications.

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Rigid-Flex: A PCB construction combining flexible circuits and rigid multilayers usually to provide a built-in connection or to make a three-dimensional form that includes components.

Robber: An exposed area generally attached to a rack used in electroplating, usually to provide a more uniform current density on plated parts. Thieves are intended to absorb the unevenly distributed current on parts, thereby assured that the parts will receive a uniform electroplated coating.

Rough Holes: Holes with a copper burr around either the entry or exit hole and that lack a smooth barrel.

Route (or Track): A layout or wiring of an electrical connection.

Routing options: They can be Tab routing, Tab routing with Perforation Holds and Vscore.

S

Schematic Diagram: A drawing which shows, by means of graphic symbols, the electrical connections, components, and functions of an electronic circuit.

Scoring: A technique in which grooves are machined on opposite sides of a panel to a depth that permits individual boards to be separated from the panel after component assembly.

Screen: A cloth material (usually polyester or stainless steel for circuit boards) coated with a pattern which determines the flow and location of coatings forced through its openings.

Screen Printing: A process for transferring an image to a surface by forcing suitable media through a stencil screen with a squeegee.

Selective Plate: A process for plating unique features with a different metal than the remaining features will have. Created by imaging, exposing and plating selected area then repeating the process for the remainder of the board.

Shadowing: A condition occurring during etchback in which the dielectric material, in contact with the foil, is incompletely removed although acceptable etchback may have been achieved elsewhere.

Silk Screen (Silk Legend): Epoxy-ink Legend printed on PCB. The most common colours used are white and yellow.

Single-sided Board: A printed board with conductive pattern on one side only.

Small Outline Integrated Circuit (SOIC): An integrated circuit with two parallel rows of pins in surface mount package.

Smallest Hole: This is the smallest hole contained in your drill file.

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SMOBC: Solder mask over bare copper. A method of fabricating a printed circuit board which results in final metallization being copper with no protective metal. The non-coated areas are coated by solder resist, exposing only the component terminal areas. This eliminated tin lead under the pads.

SMD: Surface Mount Device.

SMT: Surface Mount Technology. Defines the entire body of processes and components that create printed circuit board assemblies with leadless components.

Solder: An alloy that melts at relatively low temperatures and is used to join or seal metals with higher melting points. A metal alloy with a melting temperature below 427°C (800°F).

Solder Bridging: Solder connecting, in most cases, misconnecting, two or more adjacent pads that come into contact to form a conductive path.

Solder Bumps: Round solder balls bonded to the pads of components used in face-down bonding techniques.

Solder Levelling: The process by which the board is exposed to hot oil or hot air to remove any excess solder from holes and lands.

Solder Mask: Used to protect the board and circuitry during the assembly and packaging operations.

Solder Mask or Solder resist: Coating to prevent solder to deposit on.

Solder Wick: A band of wire removes molten solder away from a solder joining or a solder bridge or just for desoldering.

Solderability Testing: The evaluation of a metal to determine its ability to be wetted by solder.

Squeegee: The tool used in silk-screening which forces the resist or ink through the mesh.

Starvation, Resin: A deficiency of resin in base material which is apparent after lamination by the presence of weave texture, low gloss, or dry spots.

Step-and-Repeat: A method by which successive exposures of a single image are made to produce a multiple image production master.

Stripline: A specific transmission line on a PCB where the signal trace is buried within the PCB and is spaced above and below a ground plane by the dielectric material, such as FR-4.

Stripping: The process by which imaging material (resist) is chemically removed from a panel during fabrication.

Substrate: A material on whose surface adhesive substance is spread for bonding or coating. Also, any material that provides a supporting surface for other materials used to support printed circuit patterns.

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Subtractive Processing: The method of selectively removing copper from a board to form a circuit. In this case, “subtractive” refers to the method of image transfer from a phototool or image file to the copper circuit.

T

TDR: Time Domain Reflectometer, a device which a board house can use for measuring characteristic impedance of a conductor on a printed board, thus insuring an accurate build for controlled impedance

Tab Routing: Rather than completing the route path around the board edge, “Tabs” are left so as to leave boards attached in pallets for ease of assembly.

Temperature Coefficient (TC): The ratio of a quantity change of an electrical parameter, such as resistance or capacitance, of an electronic component to the original value when temperature changes, expressed in %/ºC or ppm/ºC.

Test Coupon: A portion of a printed circuit board containing printed circuit coupons used to determine the acceptability of such boards.

Test Point: A specific point in a circuit board used for specific testing for functional adjustment or quality test in the circuit-based device.

TG: Glass transition temperature, the point at which rising temperatures causes the solid base laminate to start to exhibit soft, plastic-like symptoms. This is expressed in degrees Celsius (°C).

Thief: An extra cathode placed as to divert to itself some of the current from portions of the board which otherwise would receive too high a current density.

Tooling Holes: The general term for holes placed on a printed circuit board for registration purposes during the manufacturing process

Top Side: See Component Side

Trace: A common term for conductor.

Transmission line: Commonly used to denote a controlled impedance conductor path that has a defined velocity of propagation. Geometry and dielectric materials determine many of the properties of a transmission line. Examples are coaxial cable, twinax or parallel paired cable, twisted pairs, parallel traces on a PCB.

Traveler: The list of instructions describing the board, including any specific processing requirements. Also called a shop traveler, routing sheet, job order, or production order.

Twist: A laminate defect in which deviation from planarity results in a twisted arc.

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U

UL: Underwriter’s Laboratories. An independent product safety testing and certification organization.

UV (Ultraviolet) Curing: Polymerizing hardening, or cross-linking a low molecular weight resinous material in a wet coating or ink, using ultraviolet light as an energy source.

V

V-Scoring: The edges are “scored” to allow breaking boards apart after assembly

Via: A plated-through hole used for interconnection of conductors on different sides or layers of a PCB. Void: A void in the metallic deposit of a plated-through hole exposing the base material.

W Wave Soldering: A manufacturing operation in which solder joints are soldered simultaneously using a wave of molten solder. Wicking: Migration of copper salts into the glass fibres of the insulation material.

Z Zero Defects Sampling: A statistical based attribute sampling plan (c=o) where a given sample of parts are inspected and any defects found are cause for rejection of the entire lot. Zip File: Zipping a file compresses one or more files into a smaller archive. It takes up less hard drive space and less time to transfer across a network or the internet.

Dapc Dfm Guide 2.0

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