PHKD13N03LTDual TrenchMOS logic level FETM3D315

Rev. 01 23 June 2003 Product data

1. Product profile

1.1 DescriptionDual N-channel enhancement mode field-effect transistor in a plastic package usingTrenchMOS technology.

Product availability:

PHKD13N03LT in SOT96-1 (SO8).

1.2 Features

1.3 Applications

1.4 Quick reference data

2. Pinning information

n Low gate charge n Surface mount packagen Low on-state resistance n Fast switching.

n Portable appliances n Notebook computersn Lithium-ion battery chargers n DC-to-DC converters.

n VDS 30 V n ID 10.4 An Ptot 3.57 W n RDSon 20 m

Table 1: Pinning - SOT96-1 (SO8), simplified outline and symbolPin Description Simplified outline Symbol1 source1 (s1)

SOT96-1 (SO8)

2 gate1 (g1)3 source2 (s2)4 gate2 (g2)5,6 drain2 (d2)7,8 drain1 (d1)

4

5

1

8

Top view MBK187

d

MBK725

gs

d

11

1 1 d

gs

d

22

2 2

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FET3. Limiting values

[1] Single device conducting.

Table 2: Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max UnitVDS drain-source voltage (DC) 25 C Tj 150 C - 30 VVDGR drain-gate voltage (DC) 25 C Tj 150 C; RGS = 20 k - 30 VVGS gate-source voltage (DC) - 20 VID drain current (DC) Tsp = 25 C; VGS = 10 V; Figure 2 and 3 [1] - 10.4 A

Tsp = 100 C; VGS = 10 V; Figure 2 [1] - 6.6 AIDM peak drain current Tsp = 25 C; pulsed; tp 10 s; Figure 3 [1] - 42 APtot total power dissipation Tsp = 25 C; Figure 1 - 3.57 WTstg storage temperature 55 +150 CTj junction temperature 55 +150 CSource-drain diodeIS source (diode forward) current (DC) Tsp = 25 C [1] - 3.2 AISM peak source (diode forward) current Tsp = 25 C; pulsed; tp 10 s [1] - 42 AProduct data Rev. 01 23 June 2003 2 of 129397 750 11612 Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FETVGS 5 V

Fig 1. Normalized total power dissipation as afunction of solder point temperature.

Fig 2. Normalized continuous drain current as afunction of solder point temperature.

Tsp = 25 C; IDM is single pulse

Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.

03aa17

0

40

80

120

0 50 100 150 200

(%)

Tsp (C)

Pder

03aa25

0

40

80

120

0 50 100 150 200Tsp (C)

Ider(%)

PderPtot

Ptot 25 C( )

----------------------- 100%=Ider

IDI

D 25 C( )------------------- 100%=

003aaa368

10-1

1

10

102

10-1 1 10 102VDS (V)

ID(A)

DC100 ms

10 ms

1 ms

tp = 10 s

100 s

Limit RDSon = VDS/IDProduct data Rev. 01 23 June 2003 3 of 129397 750 11612 Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FET4. Thermal characteristics

4.1 Transient thermal impedance

Table 3: Thermal characteristicsSymbol Parameter Conditions Min Typ Max UnitRth(j-sp) thermal resistance from junction to solder

pointFigure 4 - - 35 K/W

Rth(j-a) thermal resistance from junction to ambient minimum footprint;mounted on a printed-circuit board

- 70 - K/W

Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.

003aaa415

10-1

1

10

102

10-4 10-3 10-2 10-1 1 10tp (s)

Zth(j-sp) (K/W)

single pulse

0.2

0.1

0.05

= 0.5

0.02

tp

tp

T

P

t

T =Product data Rev. 01 23 June 2003 4 of 129397 750 11612 Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FET5. Characteristics

Table 4: CharacteristicsTj = 25 C unless otherwise specified.Symbol Parameter Conditions Min Typ Max UnitStatic characteristicsV(BR)DSS drain-source breakdown voltage ID = 250 A; VGS = 0 V

Tj = 25 C 30 - - VTj = 55 C 27 - - V

VGS(th) gate-source threshold voltage ID = 250 A; VDS = VGS; Figure 9 VTj = 25 C 1 1.5 2 VTj = 150 C 0.5 - - VTj = 55 C - - 2.2 V

IDSS drain-source leakage current VDS = 24 V; VGS = 0 VTj = 25 C - - 1 ATj = 100 C - - 5 A

IGSS gate-source leakage current VGS = 20 V; VDS = 0 V - - 100 nARDSon drain-source on-state resistance VGS = 10 V; ID = 8 A; Figure 7 and 8

Tj = 25 C - 17 20 mTj = 150 C - - 34 m

VGS = 4.5 V; ID = 7 A; Figure 7 - 21 26 mDynamic characteristicsQg(tot) total gate charge ID = 5 A; VDD = 15 V; VGS = 5 V; Figure 13 - 10.7 - nCQgs gate-source charge - 2.7 - nCQgd gate-drain (Miller) charge - 3.9 - nCCiss input capacitance VGS = 0 V; VDS = 15 V; f = 1 MHz; Figure 11 - 752 - pFCoss output capacitance - 200 - pFCrss reverse transfer capacitance - 130 - pFtd(on) turn-on delay time VDD = 15 V; ID = 1.5 A; VGS = 10 V; RG = 6 - 6 - nstr rise time - 7 - nstd(off) turn-off delay time - 23 - nstf fall time - 11 - nsSource-drain diodeVSD source-drain (diode forward) voltage IS = 7 A; VGS = 0 V; Figure 12 - 0.86 1.1 Vtrr reverse recovery time IS = 7 A; dIS/dt = 100 A/s; VR = 30 V;

VGS = 0 V- 25 - ns

Qr recovered charge - 5 - nCProduct data Rev. 01 23 June 2003 5 of 129397 750 11612 Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FETTj = 25 C Tj = 25 C and 150 C; VDS > ID x RDSonFig 5. Output characteristics: drain current as a

function of drain-source voltage; typical values.Fig 6. Transfer characteristics: drain current as a

function of gate-source voltage; typical values.

Tj = 25 C

Fig 7. Drain-source on-state resistance as a functionof drain current; typical values.

Fig 8. Normalized drain-source on-state resistancefactor as a function of junction temperature.

003aaa325

0

2

4

6

8

10

0 0.5 1 1.5 2VDS (V)

ID(A)

2.5 V

2.3 V

2.4 V

2.6 V

VGS = 2.8 V

2.7 V

3 V

10 V5 V

003aaa326

0

2

4

6

8

10

0 1 2 3VGS (V)

(A)VDS > ID x RDSonID

Tj = 150 C

25 C

003aaa327

0

20

40

60

80

0 2 4 6 8 10ID (A)

RDSon(m)

10 V

2.6 V2.5 V

3 V

5 V

4 V

VGS = 2.8 V

03aa27

0

0.5

1

1.5

2

-60 0 60 120 180Tj (C)

a

aRDSon

RDSon 25 C( )-----------------------------=Product data Rev. 01 23 June 2003 6 of 129397 750 11612 Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FETID = 1 mA; VDS = VGS Tj = 25 C; VDS = 5 V

Fig 9. Gate-source threshold voltage as a function ofjunction temperature.

Fig 10. Sub-threshold drain current as a function ofgate-source voltage.

VGS = 0 V; f = 1 MHz

Fig 11. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values.

03aa33

0

0.5

1

1.5

2

2.5

-60 0 60 120 180Tj (C)

VGS(th)(V)

max

typ

min

003aaa426

10-6

10-5

10-4

10-3

10-2

10-1

0 1 2 3VGS (V)

ID(A)

maxtypmin

003aaa328

10

102

103

104

10-1 1 10 102

C (pF)

Ciss

CossCrss

VDS (V)Product data Rev. 01 23 June 2003 7 of 129397 750 11612 Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FETTj = 25 C and 150 C; VGS = 0 V ID = 8 A; VDD = 15 V

Fig 12. Source (diode forward) current as a function ofsource-drain (diode forward) voltage; typicalvalues.

Fig 13. Gate-source voltage as a function of gatecharge; typical values.

003aaa329

0

2

4

6

8

0.2 0.4 0.6 0.8 1VSD (V)

IS(A)

Tj = 150 C

25 C

003aaa330

0

1

2

3

4

5

0 5 10 15QG (nC)

VGS(V)Product data Rev. 01 23 June 2003 8 of 129397 750 11612 Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FET6. Package outline

Fig 14. SOT96-1 (SO8).

UNIT Amax. A1 A2 A3 bp c D(1) E(2) (1)e HE L Lp Q Zywv

REFERENCESOUTLINEVERSION

EUROPEANPROJECTION ISSUE DATE

IEC JEDEC JEITA

mm

inches

1.75 0.250.101.451.25 0.25

0.490.36

0.250.19

5.04.8

4.03.8 1.27

6.25.8 1.05

0.70.6

0.70.3 8

0o

o

0.25 0.10.25

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Notes1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.

1.00.4

SOT96-1

X

w M

AA1A2

bp

D

HE

Lp

Q

detail X

E

Z

e

c

L

v M A

(A )3

A

4

5

pin 1 index

1

8

y

076E03 MS-012

0.069 0.0100.0040.0570.049 0.01

0.0190.014

0.01000.0075

0.200.19

0.160.15 0.05

0.2440.228

0.0280.024

0.0280.0120.010.010.041 0.004

0.0390.016

0 2.5 5 mm

scale

SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1

99-12-2703-02-18Product data Rev. 01 23 June 2003 9 of 129397 750 11612 Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FET7. Revision history

Table 5: Revision historyRev Date CPCN Description01 20030623 - Product data (9397 750 11612)Product data Rev. 01 23 June 2003 10 of 129397 750 11612 Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FET

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FETContact informationFor additional information, please visit http://www.semiconductors.philips.com.

8. Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at

URL http://www.semiconductors.philips.com.[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

9. DefinitionsShort-form specification The data in a short-form specification isextracted from a full data sheet with the same type number and title. Fordetailed information see the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in accordance withthe Absolute Maximum Rating System (IEC 60134). Stress above one ormore of the limiting values may cause permanent damage to the device.These are stress ratings only and operation of the device at these or at anyother conditions above those given in the Characteristics sections of thespecification is not implied. Exposure to limiting values for extended periodsmay affect device reliability.

Application information Applications that are described herein for anyof these products are for illustrative purposes only. Philips Semiconductorsmake no representation or warranty that such applications will be suitable forthe specified use without further testing or modification.

10. DisclaimersLife support These products are not designed for use in life supportappliances, devices, or systems where malfunction of these products canreasonably be expected to result in personal injury. Philips Semiconductors

customers using or selling these products for use in such applications do soat their own risk and agree to fully indemnify Philips Semiconductors for anydamages resulting from such application.Right to make changes Philips Semiconductors reserves the right tomake changes in the products - including circuits, standard cells, and/orsoftware - described or contained herein in order to improve design and/orperformance. When the product is in full production (status Production),relevant changes will be communicated via a Customer Product/ProcessChange Notification (CPCN). Philips Semiconductors assumes noresponsibility or liability for the use of any of these products, conveys nolicence or title under any patent, copyright, or mask work right to theseproducts, and makes no representations or warranties that these products arefree from patent, copyright, or mask work right infringement, unless otherwisespecified.

11. TrademarksTrenchMOS is a trademark of Koninklijke Philips Electronics N.V.

Level Data sheet status[1] Product status[2][3] Definition

I Objective data Development This data sheet contains data from the objective specification for product development. PhilipsSemiconductors reserves the right to change the specification in any manner without notice.

II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be publishedat a later date. Philips Semiconductors reserves the right to change the specification without notice, inorder to improve the design and supply the best possible product.

III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves theright to make changes at any time in order to improve the design, manufacturing and supply. Relevantchanges will be communicated via a Customer Product/Process Change Notification (CPCN).9397 750 11612 Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product data Rev. 01 23 June 2003 11 of 129397 750 11612 Koninklijke Philips Electronics N.V. 2003. All rights reserved.

Product data Rev. 01 23 June 2003 11 of 12

For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. Fax: +31 40 27 24825

Koninklijke Philips Electronics N.V. 2003.Printed in The NetherlandsAll rights are reserved. Reproduction in whole or in part is prohibited without the priorwritten consent of the copyright owner.The information presented in this document does not form part of any quotation orcontract, is believed to be accurate and reliable and may be changed without notice. Noliability will be accepted by the publisher for any consequence of its use. Publicationthereof does not convey nor imply any license under patent- or other industrial orintellectual property rights.Date of release: 23 June 2003 Document order number: 9397 750 11612

Contents

Philips Semiconductors PHKD13N03LTDual TrenchMOS logic level FET

1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Quick reference data. . . . . . . . . . . . . . . . . . . . . 12 Pinning information . . . . . . . . . . . . . . . . . . . . . . 13 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 24 Thermal characteristics. . . . . . . . . . . . . . . . . . . 44.1 Transient thermal impedance . . . . . . . . . . . . . . 45 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 97 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 108 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 119 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1110 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1111 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

1. Product profile1.1 Description1.2 Features1.3 Applications1.4 Quick reference data

2. Pinning information3. Limiting values4. Thermal characteristics4.1 Transient thermal impedance

5. Characteristics6. Package outlineSOT96-1

7. Revision history8. Data sheet status9. Definitions10. Disclaimers11. Trademarks