D. 215 Hybrid Metal/Dielectric Bondinghomepages.rpi.edu/~luj/Papers/lujq3.pdfEl Ramm—Handbook of...

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Handbook of Wafer Bonding, First Edition. Edited by Peter Ramm, James Jian-Qiang Lu, Maaike M. V. Taklo.© 2012 Wiley-VCH Verlag GmbH & Co. KGaA. Published 2012 by Wiley-VCH Verlag GmbH & Co. KGaA.

HybridMetal/PolymerWaferBondingPlatformJian-QiangLu,J.JayMcMahon,andRonaldJ.Gutmann

D. HybridMetal/DielectricBonding

11.1Introduction

Three-dimensional (3D) hyper-integration1) is an emerging technology that can form highly integrated systems by vertically stacking and connecting together various materials, technologies, and functional components [1–4]. The potential benefits of 3D integration vary for each 3D platform; they include multifunctional-ity, small form factor, increased speed and data bandwidth, reduced power, reduced component packaging, increased yield and reliability, flexible heterogene-ous integration, and reduced overall costs. Figure 11.1 shows schematic represen-tations of major wafer-level 3D integration platforms pursued currently [1].

There are four key enabling technologies for 3D integration [1]: wafer alignment, wafer bonding, wafer thinning, and interstrata interconnection. The wafer align-ment technology enables accurate alignment of the circuits or devices on two or more wafers. The wafer bonding technology enables two or more processed wafers to be thermomechanically bonded together. The wafer thinning technology enables the circuits or devices on two or more wafers to be closely connected by short interstrata interconnections. The interstrata interconnection technology (i.e., inter-tier, interchip, or interwafer interconnections as also called in the literature) enables electrical, thermal, and optical interstrata interconnects or fluidic channels between the circuits or devices on the stacked wafers. The interstrata electrical interconnection passing through thinned Si substrate is called a through-Si via, or, in general, a through-strata via (TSV). The interstrata electrical interconnec-tions at the bonding interface could be called “bonded interstrata via” (BISV). Among the four key enabling technologies, wafer bonding technology enables not only the stacking of circuits or devices on two or more wafers, but also BISV and wafer thinning, thus a massive number of short TSVs.

As can be seen from Figure 11.1, currently there are four major bonding and interstrata interconnection approaches, as highlighted in Figures 11.1b–e [5–29]:

1) The term “hyper-integration” means to integrate various materials, processing technologies, and functions beyond ultralarge-scale integration (ULSI) or gigascale integration.

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216 11 HybridMetal/PolymerWaferBondingPlatform

• oxide-to-oxide bonding (Figure 11.1a) [28, 29],• adhesive (polymer) bonding (Figure 11.1b) [5–13],• Cu-to-Cu bonding (Figure 11.1d) [14–19],• bonding of hybrid metal/polymer redistribution layer (Figure 11.1e) [20–27].

Since the key advantage of 3D integration is to vertically integrate multiple circuits, devices, and/or systems on separately processed wafers, the following conditions to bond two wafers are desired for any 3D approaches, if not strictly required:

• compatible with back-end-of-the-line (BEOL) IC process, that is, with a bonding temperature at, or lower than, 400 °C;

• high thermal and mechanical stability of the bonding interface over the ranges of BEOL and packaging processing conditions;

• no outgassing during bonding to avoid void formation;• seamless bonding interface with high bond strength to prevent

delamination.

To satisfy the last condition, strong chemical bonds must be formed between the bonding surfaces over the entire wafer pair during the bonding process. This further requires (i) topography dictated by characteristics of the materials at the bonding interface (e.g., atomically flat bonding surfaces for oxide bonding) and/or (ii) diffusion of a massive number of atoms/molecules across the bonding interface during bonding or post-bond anneal.

Various wafer bonding approaches are described in this book. The hybrid wafer bonding approach using damascene-patterned metal/dielectric layers [30–32] involves combining metal bonding for direct electrical interstrata interconnections and dielectric (oxide or polymer) bonding for mechanical bonding strength, thus facilitating electrical and mechanical bonds between a pair of wafers. Specific details of a hybrid metal/polymer wafer bonding platform using damascene-patterned Cu/benzocyclobutene (BCB) layers as the wafer bonding intermediate layers are discussed in this chapter. Details of metal/oxide bonding [31, 32] are described in the following chapters. Since the Cu and BCB bonding are

Figure11.1 Schematicsofamajorwafer-level3Dintegrationplatformwith(a)fourkey3Denablingprocesses,and(b–e)fourmajorwaferbondingapproaches.(Figureadaptedfrom[1].©2009IEEE.)


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11.2 Three-DimensionalPlatformUsingHybridCu/BCBBonding 217

relevant to this chapter, their advances and advantages are summarized in the following.

For polymer bonding, particularly with BCB as the bonding polymer, as described in Chapter 3, major research advances include [5–13, 33, 34]:

• free of voids, defects, and structural damage;

• sufficiently high bond strength with a critical adhesion energy of the order of 30 J m−2;

• no degradation of electrical characteristics on wafers with Cu interconnect test structures and wafers with CMOS Si-on-insulator Cu/low-k devices and circuits after multiple bonding and thinning processes;

• significantly reduced wafer edge chipping during wafer thinning [33] and comparable chip sawing results to two-dimensional IC wafers [13];

• no degradation in bond strength after conventional die packaging reliability tests [13].

The key advantages of this approach include:

• the ability of the polymer to accommodate wafer surface nonplanarity (e.g., due to the last BEOL metallization) and particulates at the bonding interfaces;

• edge chipping protection during wafer thinning [33] and dicing [13];

• no handling wafers are required, that is, thinned Si is not transferred as in some other wafer-level 3D approaches;

• stacks of three or more wafers can be fabricated without changing the process-ing approach since the wafer bond with fully cured BCB sandwiched between two Si wafers is thermally stable up to 400 °C [7, 34].

For metal bonding, particularly with Cu as the bonding metal, as described in previous chapters, the key advances include that [14–19]:

• the Cu bond can be formed at a temperature of 350 °C or lower;• the Cu grain passes though the bonding interface;• the specific contact resistance of the bonded Cu is as low as 10−8 Ω cm2.

The key advantages of this approach are:

• interstrata electrical vias, or BISVs, can be formed during the bonding process;• density of BISVs (not TSVs) can be very high because they are very short; the

via density is largely limited by the alignment accuracy.

11.2Three-DimensionalPlatformUsingHybridCu/BCBBonding

The 3D technology platform using hybrid metal/polymer bonding [20–25] employs wafer bonding of damascene-patterned metal/polymer redistribution layers on two


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wafers, thus providing interstrata electrical interconnects (i.e., BISVs) and polymer bonding of two wafers in one unit processing step. A conceptual schematic of this approach is illustrated in Figure 11.2 and key points are listed as follows:

• Cu/Ta and BCB are selected as the metal/liner and polymer for feasibility demonstration of this 3D platform.

• The bottom wafer (i.e., the first stratum) has a full wafer thickness as a base wafer to mechanically support the 3D fabrication processes of multiple strata of circuits/devices, which are fabricated separately on different wafers with their optimized materials and fabrication processes. Multicore processor chips with multilevel interconnects could be fabricated on this base wafer, serving as the central processing unit (CPU) for the whole 3D system. A heat sink could be attached to the backside of the processor chip, perhaps after thinning to about 200 µm for improved heat sinking as done with conventional two-dimensional ICs.

• A damascene-patterned Cu/BCB layer using chemical-mechanical plana-rization (CMP) technology is formed over the uppermost metal layer of the bottom wafer.

• A damascene-patterned Cu/BCB redistribution layer is formed over the upper-most metal layer of a second wafer. Memory chips with L3 cache and/or

Figure11.2 Schematicofa3Dplatformusinghybridmetal/dielectricbonding.ForhybridCu/BCBredistributionlayerbonding:Cu–Cubondsprovideinterstrataelectricalintercon-

nects(i.e.,BISVs)andBCB–BCBpolymerbondsprovidemechanicalwaferattachment.Tworedistributionlayeroptionsareshownonthesecondandthirdwafers,respectively[22].


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11.2 Three-DimensionalPlatformUsingHybridCu/BCBBonding 219

advanced DRAMs could be fabricated on this wafer, providing the memory needed for the CPU on the base chip.

• This second wafer is then flipped, aligned, and bonded to the patterned Cu/BCB layer on the base wafer. Note that the patterned Cu/BCB layer on the base wafer can also be a Cu/BCB redistribution layer if needed (not shown in Figure 11.2).

• The substrate of the face-down bonded second wafer is then thinned by mechanical grinding, CMP, and wet-etching.

• The process can be extended to multiple wafer stacks by etching through the thinned second wafer of the bonded pair to create another damascene-patterned layer, which mates with a third wafer. Note that the patterned Cu/BCB layer on the thinned second wafer substrate can also be a Cu/BCB redistribution layer if needed (not shown in Figure 11.2).

• An extra Cu/oxide (or Cu/BCB, or other metal/dielectric) redistribution layer, for example, that over the uppermost metal layer of the third wafer as shown in Figure 11.2, can be added prior to the patterning process of any Cu/BCB bonding layer, thus simplifying the patterning process of Cu/BCB bonding layer because only Cu bonding posts (vias) are needed. This approach also offers a simple bonding scheme, that is, with minimum misalignment one is always bonding Cu posts to Cu posts and BCB field to BCB fields, avoiding undesirable contact (i.e., bonding) of long Cu lines with BCB fields (see the bonding layers between second and third wafers as shown Figure 11.2). Moreover, this approach provides much more redistribution capability than that combining Cu bonding vias with the redistribution layer (e.g., the Cu/BCB redistribution layer on front side of the second wafer as shown in Figure 11.2).

This 3D platform using hybrid metal/polymer wafer bonding would provide:

• both electrical and mechanical interstrata connections/bonds (combining advantages of both BCB/BCB and Cu/Cu bonding);

• thermal management options: a Cu/BCB “redistribution layer” could serve as a good thermal conductor and/or spreader (with large percentage of Cu area), or as a poor thermal conductor (with large percentage of BCB area), based on local design considerations;

• high interstrata interconnectivity while allowing large alignment tolerance by eliminating direct bonding between deep interstrata vias (i.e., TSVs) and bonding pads;

• a “redistribution layer” as interstrata interconnect routing for wafers, on which the interstrata interconnect pads are not matched, which further reduces the process flow and is compatible with wafer-level packaging technologies;

• potential edge chipping protection during wafer thinning and dicing.


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This platform is attractive for applications of monolithic wafer-level 3D integra-tion (e.g., 3D interconnects, 3D ICs, wireless, smart imagers, etc.) as well as wafer-level packaging, passives, microelectromechanical systems (MEMS), optical MEMS, bio-MEMS, and sensors. In particular, we believe that the platform is attractive as an intermediate between wafer-level 3D ICs and more conventional wafer-level 3D packaging, where the fully functional individual wafers are equiva-lent to hard IP cores [35].

Clearly, the bonding process for such a hybrid metal/dielectric technology plat-form would be more challenging than simple Cu, oxide, or BCB bonding, as a variety of surfaces are exposed including the dielectrics, diffusion barriers, and electrical conductors. Ideally, all should be capable of being bonded to one another without interfering with the electrical characteristics of the Cu-to-Cu interconnec-tion. Surface preparation techniques for improving adhesion of BCB to Si and silicon nitride as well as Cu have been discussed in the literature, but not with respect to a wafer bonding application. Further, wafer bonding of soft-baked BCB has been well documented for 3D applications [5–13, 33], as has damascene pat-terning of Cu in fully cured BCB [36, 37]. Based on what is known about Cu and BCB processing, a baseline process for a Cu/BCB hybrid bonding platform is developed and its details are discussed in the following section.

11.3BaselineBondingProcessforHybridCu/BCBBondingPlatform

The two main challenges for any hybrid metal/dielectric bonding are (i) selection of metals and dielectrics for damascene patterning and (ii) wafer-level feature-scale CMP to ensure bonding integrity and low resistance of electrical BISVs. For hybrid metal/polymer bonding, a Cu/BCB system is selected to demonstrate this bonding approach, where BCB is partially cured to enable Cu/BCB CMP [21, 23] because a partially cured BCB layer offers the best compromise between patterning capabil-ity and bond quality, as confirmed in the next section.

Figure 11.3 illustrates the key steps of the Cu/BCB wafer bonding process. Table 11.1 gives the typical 3D integration processing flow with hybrid wafer bonding using damascene-patterned metal/polymer redistribution layers. This wafer bond-ing process flow is a combination of BCB bonding and Cu bonding processes.

Figure11.3 Simplifiedsetofwaferbondingstepsusingdamascene-patternedCu/BCBsurfaces.


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11.3 BaselineBondingProcessforHybridCu/BCBBondingPlatform 221

Table11.1 Typical3DintegrationprocessingstepswithCu/BCBwaferbonding.

No. Processstep Purposeoftheprocessstep

1 Wafer pre-cleaning and drying of the wafers

Remove particles, contaminations, and moisture from the wafer surfaces

2 Polymer application on wafers Apply BCB uniformly (55% BCB crosslinking, enabling Cu/BCB CMP process [23]

3 Damascene-patterned metal/polymer bonding interface

Form metal bonding pads, posts, and “dummy” bonding surfaces

• Cu/BCB damascene (CMP) and post-CMP brush cleaning

• CMP and post-CMP brush cleaning to form flat, clean surface across the wafers

4 Wafer alignment Wafers are aligned with pre-patterned alignment marks, allowing TSV formation at the desired locations

5 Wafer bonding Bond two wafers seamlessly

• Vacuum pump to 0.1 mtorr• Temperature ramp-up to 250 °C• Apply bond pressure of >0.3 MPa• Hold for

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The major differences are (i) partially cured BCB is used instead of soft-baked BCB to enable Cu/BCB damascene and (ii) BCB is still bonded at relatively low tem-perature of 250 °C as for soft-baked BCB bonding, followed by Cu bonding at elevated temperature of 350 °C. The detailed wafer bonding results and evaluation for this bonding approach are discussed in the following section.

11.4EvaluationofCu/BCBHybridBondingProcessingIssues

To evaluate hybrid metal/polymer wafer bonding, a via-chain structure is designed and fabricated following the baseline process flow as described in Table 11.1. The damascene-patterned Cu/BCB layer is fabricated as follows [21, 25]. BCB is spun onto oxidized 200 mm Si wafers using the manufacturer’s specifications. These films are soft-baked at 170 °C for three minutes in nitrogen, followed by a partial curing process at 250 °C in nitrogen until the films are more than 55% crosslinked. These films are then photolithograhically patterned and etched using inductively coupled plasma etching. The etch process consumes photoresist at about the same rate as BCB, so the photoresist mask is fully etched away during this process. Following etching, the patterned BCB is filled with a sputtered Ta liner and sput-tered Cu material for interconnects. Damascene patterning is accomplished using an IPEC 372M polisher with IC1400 k-groove pads and commercially available slurries for Cu and barrier removal. Both the Cu removal phase (i.e., the first-stage CMP) and the barrier removal phase (i.e., the second-stage CMP) consist of an abrasive slurry and an oxidizer. The Cu removal slurry mixture is specifically formulated to be selective over Ta, while the barrier removal slurry mixture is specifically formulated to be selective over Cu. After CMP, the damascene-patterned films are brush-cleaned in deionized water before aligning and bonding. After the baseline step 5 as shown in Table 11.1, bonded pairs are thinned in a three-step process: grinding and polishing, followed by a third step of wet processing that completely removes the top Si substrate. Optical microscopy and focused ion beam scanning electron microscopy (FIB-SEM) inspections of the bonded interfaces follow. Electrical measurements are conducted to characterize the contact resist-ance of the bonded Cu vias (i.e., BISVs).

11.4.1CMPandBondingofPartiallyCuredBCB

BCB films cured with different temperature and time cycles are evaluated for the baseline second-stage CMP process. BCB films on SiO2/Si wafer are baked at 190, 220, and 250 °C to a crosslink percentage of 45 to 95%. Controllable CMP removal rate and uniformity can be obtained for BCB films that are cured at a temperature of 220 °C or higher to a crosslink percentage of 50% or higher [21, 23].

The four-point bending technique [9] is used to quantify the critical adhesion energy (i.e., bonding strength) of partially cured BCB bonded Si wafers under a


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11.4 EvaluationofCu/BCBHybridBondingProcessingIssues 223

variety of surface preparation conditions [24]. Figure 11.4 shows typical load–deflection curves of four-point bending measurements for two specimens bonded with blanket partially cured BCB [24]. A load plateau region indicates quasistatic delamination of the weakest interface and allows extraction of a critical adhesion energy. For samples prepared under conditions such as partial cure, CMP/brush clean, and/or sulfuric acid dip, the typical delamination occurs at the BCB-to-SiO2 interface (using DOW AP3000 as an adhesion promoter) and critical adhesion energy values are similar to that of soft baked BCB at about 30 J m−2 [9, 24].

The high bonding strength and controllable CMP process confirm that partially cured BCB would offer the best compromise between patterning capability and bond quality for hybrid metal/polymer bonding using damascene-patterned Cu/BCB layers. More evidence can be seen from the bonding results as discussed in the following sections.

11.4.2Cu/BCBCMPSurfaceProfile

In general, the CMP process is well developed for Cu/polymer damascene pattern-ing, such as Cu/SiLK [38, 39] and Cu/BCB [36, 37]. However, since the surface topography of damascene-patterned Cu conductors with Ta liners and partially cured BCB dielectric plays an important role in the bondability of patterned wafers, the step heights of various features in patterned Cu/BCB wafers are inspected. Figure 11.5 shows a feature-level nonplanarity for a centrally located structure versus a structure near the edge of a 200 mm wafer [23]. The Cu features are slightly raised with respect to the partially cured BCB surface. Step heights over patterned features between Cu and BCB vary from 60 to 120 nm over the radius

Figure11.4 Load–deflectioncurvesoffour-pointbendingmeasurementsfortwospecimensbondedwithblanketpartiallycuredBCB.(a)Typicalresultforwafersbondedusing50%crosslinkedBCBfollowedbybondingat250°Cfor60min.(b)Typical

resultforwafersbondedusingthisprocess,plusadditional60minbondingat350°C.Adhesionenergyvaluesaresimilartothoseforsoft-bakedBCB[9].(Adaptedfrom[24].©2007MRS.)

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of a 200 mm wafer pair, with some well-bonded areas and some poorly bonded areas. This implies that good bonding can be obtained when step heights of fea-tures with a pitch of about 10 µm are as large as 60 nm.

Further work evaluated the effect of wafer-scale topography by employing a nonideal die layout [40]. Dies were placed with closely spaced rows, but widely spaced columns. As a result, the BCB field was high relative to the Cu-patterned regions. This nonplanarity was approximately 500 nm over a distance of several dies. Although this large nonplanarity can easily be prevented by closely spaced Cu/BCB patterns, even these nonplanarities may not be a barrier to good bondability.

11.4.3HybridCu/BCBBondingInterfaces

Observation of Cu–Cu, BCB–BCB, and Cu–Ta–BCB bonding interfaces is accom-plished using two methods: (i) by milling away material using a dual-beam FIB-SEM instrument and (ii) optical observation through a transparent film or substrate. Cross-sectional FIB-SEM is useful for inspecting bonding interfaces, such as grain structure in post-bonded Cu–Cu and Cu–Ta–BCB interfaces as well as interfacial voids. Interstrata via-chain structure is optically visible after the damascene-patterned Cu/BCB bonding and wafer thinning steps are completed if

Figure11.5 Feature-levelnonplanarityforstructureincentrallylocateddieversusstructureindieneartheedgeof200mmwafer[23].(©2005MRS.)

Position (microns)Center

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the entire top substrate is removed during thinning. Optical observation of BCB–BCB defects is possible in areas where BCB–BCB topography is not accommodated.

Figure 11.6 shows several FIB-SEM cross sections of an interstrata via-chain structure fabricated by damascene patterning Cu/Ta into 50% crosslinked BCB on two wafers and bonding the pair using the baseline bonding process. Figure 11.6a presents a selected long bonding interface of the via-chain structure, showing Cu–Cu bonding, BCB–BCB bonding, and voids at BCB–BCB bonding interfaces. Figures 11.6b, c, and f show details of three Cu–BCB bonding interfaces. Figures 11.6d and e show more details from Figures 11.6c and f, respectively. Note that the BCB–BCB bonding is performed at 250 °C; reliable Cu–Cu bonding would not occur at this temperature until the temperature is ramped up to 350 °C as previ-ously published results [17] indicate that a temperature greater than 300 °C is required to achieve lower than 1% die failure during dicing of Cu–Cu bonded structures, and that an interface-free bond is achievable when bonding and anneal-ing temperatures are at or greater than 350 °C for an hour or more.

All the FIB-SEM cross sections show (i) excellent Cu–Cu bonding as Cu grains pass across the original Cu–Cu bonding interface and (ii) seamless BCB–BCB bonding. All the FIB-SEM cross sections also show that Cu voids tend to form at the Cu/Ta line edge (see Figure 11.6d and region B of Figure 11.6e). These Cu voids are known to be often formed after the CMP process, so-called “Cu line edge trenching” [41]; they could also be formed due to thermal stress during the thermal processing, such as post-CMP anneal or high-temperature bonding [24, 42]. This Cu void formation should not be an intrinsic issue for Cu/BCB bonding because it could be controlled by a combination of improved Cu filling, prior-CMP anneal, and CMP process.

Even more interesting results about these Cu voids at the Cu/Ta line edge are that:

• almost all the Cu voids at the Cu/Ta line edge on one wafer are filled by Cu diffusion from another wafer when Cu voids oppose the Cu surface (marked as region A in Figure 11.6e), indicating Cu fusion bonding;

• almost all the Cu voids at the Cu–Ta–BCB interface on one wafer are not filled by BCB from another wafer when Cu voids oppose the BCB surface (marked as region B in Figure 11.6e), indicating no BCB reflow, thus minimizing the possibility of Cu bond contamination by BCB.

The Cu-to-Cu fusion bonding and no BCB reflow are clearly confirmed in all cases.

From Figure 11.6b, nanovoids are observed typically at Cu grain boundaries. These voids may be formed during Cu grain growth and could be enhanced or created by the ion and/or electron bombardment from FIB-SEM because the Cu grains are weakly contacted at the grain boundaries. These nanovoids could be prevented by improved Cu filling, prior-CMP anneal, CMP process, and post-bonding anneal.


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Figure11.6 FIB-SEMcrosssectionsofaninterstratavia-chainstructureusinghybridCu/BCBbonding,showing:Cu–CubondingwithCugrainsacrossthebondinginterface;seamlessBCB–BCBbonding;filledCuvoidsononewaferbyCufromanotherwaferwhentheCuvoidsopposetheCusurfaceasmarkedasregionAin(e),indicatingCufusionbonding;Cuvoids(atCu–Ta–BCB

interfaceononewafer)thatarenotfilledbyBCBwhenCuvoidsopposetheBCBsurfaceasmarkedasregionBin(e),indicatingnoBCBreflow,thusminimizingpossibleCubondcontaminationbyBCB;nanovoidsattheCugrainboundaries;andBCBbondingvoidsseveralmicrometersawayfromtheCuBISVstructure.Seetextfordetaileddescriptionanddiscussion.

BCBBCB

Ta (Cu liner)1 µm

BCB Bonding Void at Bonding Interface

Oxide

Oxide CuCuCuCu

Cu Bonding Interface a)

1 µm Oxide

Cu Grain Across Bonding Interface

Nanovoids at Cu Grain Boundary

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CuCu BCBCu-Ta-BCB wafer

Bottom

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BCB bonding voids are also observed several micrometers away from the Cu BISV structure as shown in Figure 11.6a. Voiding can also be observed in plan view via optical microscopy. Figure 11.7 shows defects in a region where post-CMP topography is too large to be accommodated. Voids are visible at the BCB–BCB interfaces near the Cu structure where post-CMP topography is expected due to dielectric loss [23, 43]. An area with a visible scratch is also shown in Figure 11.7 to illustrate that voiding can be produced in areas where no Cu structure exists. This suggests that the observed BCB–BCB defects can be caused by BCB topog-raphy alone.

The Cu nanovoids and BCB bonding voids are concerns, but both can be addressed in further development. In particular, optimized processes for Cu/BCB damascene patterning and bonding are expected to solve these problems. However, the good Cu/BCB bonding achieved with a relatively high Cu/BCB surface non-planarity as shown in Figure 11.5 and discussed in Section 11.4.2 suggests that the partially cured BCB can accommodate certain Cu/BCB surface nonplanarity. Experiments have been designed and conducted to investigate the BCB accom-modation mechanisms, as described in the following section.

11.4.4TopographyAccommodationCapabilityofPartiallyCuredBCB

Bonding experiments [25] utilizing structured Si wafers are depicted schematically in Figure 11.8. This procedure has a simplified material set in comparison to the full integration with via chains; however, it is useful in demonstrating how

Figure11.7 Opticalmicrographofaninterstratavia-chainstructureusingCu/BCBbonding,showinganareawherepost-CMPtopographyistoolargetoallowwell-bondedBCB–BCBinterfacesinallareas.Micrograph

withthescratchwaschosenasanindicationthatBCB–BCBdefectdensitycanbecontrolledwithoutCu/Tainthestructure[25].(©2008IEEE.)

Inter-wafervia-chains

50 µm50 µm

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Well-BondedBCB FieldDielectric

Well-BondedBCB FieldDielectric

BCB-BCBVoid RegionsCaused byPost-CMPTopography


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partially cured BCB films behave under various bonding conditions, with varying surface step heights and feature sizes. Bare Si wafers are photolithographically patterned with lines of pitch varying between 1 and 500 µm, and etched in a SF6 plasma. This process produces steps from 0.12 to 1.5 µm deep in the Si. These structured surfaces are then coated with BCB, which is partially cured at 250 °C to a degree of crosslinking between 50 and 90%. The degree of planarization (DoP) for the partially cured BCB film is expected to be about 90% for small features, based on previously published data [44].

Figure 11.9 compares two surface profile measurements of a structured Si wafer. These profiles represent the surface before and after BCB coating with a nominal BCB thickness of 1 µm, and the height shift is equal to the BCB film thickness. Note that the etched Si step height of 500 nm is translated to the same topography in the 250 µm wide features, that is, no planarization, but is reduced to about 50 nm in the 50 µm wide features, that is, a DoP of about 90%. These BCB-coated, structured Si surfaces are bonded against a flat BCB-coated glass wafer to examine the topography accommodation capability of the BCB. The glass wafer has a coef-ficient of thermal expansion close to that of the Si wafer. The bonding recipe used is identical to that described in Section 11.3. After bonding, optical inspection of the interface is possible because the top substrate (glass) is transparent.

The resulting observations include a difference in voiding presentations for dif-fering crosslink percentages: BCB films crosslinked to a degree of 50 or 60% present voids that are typical of a solid/solid bond as well as “hazy” or “dendritic” type voids. Figure 11.10 shows optical micrographs of bonding of partially cured BCB over structured Si with 1.5 µm trenches. The high regions of the Si trenches are well bonded for 50–90% crosslinked BCB. Hazy defects are observed at the

Figure11.8 SchematiccrosssectionofbondedwafersusedinthecharacterizationofthetopographyaccommodationcapabilityofpartiallycuredBCB.Ablanketfilmofpartially

curedBCBonaglasswaferisbondedtoablanketfilmofpartiallycuredBCBthathasbeencoatedoverstructuredSi.

Glass substrate

Partially cured BCB

100 m500 B d

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edge of Si trenches due to “crosslink-percentage-controlled” voids as shown in Figure 11.10a. These small crosslink-percentage-controlled voids are consistently observed at the edge of features with steps that are too large to be completely accommodated in cases of 50% crosslinked BCB. Once the crosslinking percent-age is raised to 70% or greater, this type of void is not observed; voids exhibit smooth edges after bonding as shown in Figure 11.10b for the case of 90%

Figure11.9 ProfilometrymeasurementoftheDoPforpartiallycuredBCBspunoverstructuredSi(comparetobottomwaferinFigure11.8).Post-etchprofilehaslowestfeaturesatzeroheight;post-BCBprofilehas

lowestfeaturesatabout1100nmheight(foranominalBCBthicknessof1µm).Featureslessthan100µmaretypicallyabout90%planarized.

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theedgeofSitrenchfora50%crosslinkedBCB.(b)Well-bondedhighregionofSitrenchwithwell-definededgesandnobonding(void)atthelowregionofSitrench.

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crosslinked BCB. The BCB at low regions of the Si trench is not bonded due to the large feature size of the trench that BCB cannot accommodate.

Table 11.2 shows the progression of voiding types as observed in the structured bonding experiments as surface topography is increased [25]. Since both crosslink-percentage-dependent voids and feature-size-dependent voids are dependent on the step height, the initial Si step height at which voids disappear is of interest. For the smallest topography, all steps can be accommodated, resulting in a void-free structure as shown in the top image of Table 11.2, that is, both high and low regions of the BCB surface are well bonded. For the 50% crosslinked case, the BCB-coated structures first begin to exhibit accommodation with an initial Si step

Table11.2 Progressionofvoidclassificationsasthemagnitudeoftopographyincreases.Inthetoprow,allstructureisbonded;inthemiddlerow,thetopographydictatesthebondedarea;onthebottomrow,noareaisbonded.Theintermediaterowsshowwhere“hazy”or“dendritic”typevoidsappearwhen50and60%crosslinkedBCBisusedinthestructuredbondingexperiments.

Example Highregion Lowregion Nomenclature

Defect-free Defect-free Step accommodated

Defect-free Hazy dendritic Step influenced

Defect-free Void Patterned

Hazy dendritic Void Externally influenced

Void Void Externally dominated

Adapted from [25]. © 2008 IEEE.


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height of 1 µm, but do not show consistent accommodation until the Si step is decreased to 500 nm. At that point, BCB surface topography of about 50 nm exists in the small features, and both high and low regions of the BCB surface are bonded. For cases where the level of crosslinking is increased to 70%, accommoda-tion does not begin until the Si step is at 500 nm, and significant accommodation is not observed until this step is decreased to 120 nm. Thus, for 70% crosslinked BCB, the accommodation point is when the BCB surface topography of micrometer-scale features measures about 12 nm or smaller, that is, about 10% of the step height of 120 nm.

As the Si trench step height is increased in structured bonding experiments utilizing 50–60% crosslinked BCB, “hazy” or “dendritic” type voids begin to appear in the bottom of the patterned features. Once the topography dominates the capa-bility for accommodation, voids follow the structure and create a patterned bonding layer. If structure external to that topography (such as a particle) provides influ-ence, then it is possible to observe the “hazy” or “dendritic” type voids at the top of the features as well. Once that external structure dominates the capability for the partially cured BCB to bond, the interface will be completely unbonded. Not only is it noteworthy that this additional defect mechanism is observed in the 50 and 60% crosslinked BCB films, but also that the magnitude of topography accom-modation (as defined by the number of dies exhibiting complete accommodation) is observed to be about four times greater in comparison to films with 70–90% crosslinking.

Defects at the partially cured BCB–BCB interface are found to be controllable based on the magnitude of the post-CMP topography. Since the magnitude of topography acceptance is found to be nearly constant for wafers constructed in 50 and 60% crosslinked BCB, at a level that is about four times greater than that found for 70–90% crosslinked BCB, the mechanism is attributed to deformation of the partially cured BCB film. The sharp difference in topography accommoda-tion for the partially cured films used in this study coincides with the structural change between the sol–gel/rubber region and the gel–glass region of BCB accord-ing to its time–temperature transformation curve [45].

11.4.5ElectricalCharacterizationofHybridCu/BCBBonding

Electrical characterization of hybrid Cu/BCB bonding is conducted using four-probe measurements of specific contact resistance of the via-chain structure as illustrated in Figure 11.11 [24]. The cross-sectional area of the contacts is measured by optical microscopy and assumed to be uniformly bonded over areas that exhibit continuous chains. Specific contact resistance of the order of 10−7 Ω cm2 is higher than reported values for bonded evaporated Cu [46] and for surface-activated bonding [47]. Contacts in the surface-activated bonding method are very clean, as in situ cleaning is done in an ultrahigh vacuum system just prior to alignment and bonding of the wafers. Contacts in the evaporated Cu approach have been reported to have oxygen content of the order of a few percent [48], but after annealing at


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400 °C this oxygen is diffused throughout the film. It is likely that the contact resistance reported in [46, 48] is lower than that for the hybrid metal/polymer bonding approach because of the difference in annealing temperatures and, par-ticularly, the absence of post-CMP cleaning (as needed with Cu damascene patterning).

11.5SummaryandConclusions

This chapter describes a hybrid metal/polymer bonding 3D platform with damascenepatterned Cu/BCB. Many aspects of the processing and characteriza-tion can be applied to other hybrid bonding platforms. The hybrid metal/polymer bonding platform combines the advantages of metal/metal bonding (for direct electrical interstrata interconnections) and polymer bonding (for robust thermo-mechanical wafer bonding strength as well as surface topography accommoda-tion). The redistribution layers (Cu/BCB or other metal/dielectric combinations) at the bonding interface provide design tradeoffs between thermal management, BISV routing, and alignment relaxation.

Partially cured BCB offers the best compromise between patterning capability and bond quality, and thus enables the hybrid Cu/BCB wafer bonding 3D plat-form. Controllable CMP process can be achieved when BCB is cured to a degree of crosslinking of more than 50%; void-free bonding with high bond strength (i.e., about 30 J m−2, similar to that of soft-baked BCB bonding) is possible with partially cured BCB up to a degree of crosslinking of 90% under various surface processing conditions.

A structured bonding procedure that allows isolation of the partially cured BCB topography accommodation capability demonstrates that voids begin to appear for

Figure11.11 (a)Electricaltestingof12µmpads(8µmviainterconnects).(b)Summaryofseveraltestedstructures[24].Inallcasesthebondprocessincludedbondingat250°Cfor60minfollowedbybondingat350°Cfor60min.(©2007MRS.)

Specific Contact Resistance

Contact Area

Resistance (

Number of

Chain

a) b)

Size 10

(Ω)(mm)

1.7

xContacts

52064

(10-7Ω -cm2)(cm2 -8)

0.91.2

1.1

6388

630.3528

2.76314328


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References 233

different magnitudes of topography based on the pitch of the features and the crosslinking of the partially cured BCB. BCB with a degree of crosslinking of 70–90% is found to accommodate BCB surface topography depth of about 12 nm for features of about 1 µm. Topography accommodation is observed to increase by a factor of about 4 when the BCB crosslinking is reduced to 50%.

The processing flow of the hybrid metal/polymer bonding is a combination of polymer-to-polymer bonding and metal-to-metal bonding, without introducing extra difficult processing steps. A via-chain structure is designed, fabricated, and characterized to demonstrate this 3D platform. Cu–Cu bonding with Cu grain across the bonding interface and seamless BCB–BCB bonding are demonstrated. A contact resistance of the order of 10−7 Ω cm2 is obtained. Although BCB bonding voids, nanovoids at Cu grain boundaries, and voids at Cu–Ta–BCB interface (i.e., Cu/Ta line edge) are found and the contact resistance is still high, these problems could be solved by process optimization of Cu/BCB damascene patterning and bonding.

These promising results demonstrate the feasibility of this 3D technology plat-form using hybrid metal/polymer bonding. This platform is attractive for all applications of monolithic wafer-level 3D integration and wafer-level 3D packag-ing. In particular, we believe that the platform is attractive as an intermediate between wafer-level 3D ICs and more wafer-level 3D packaging, where the fully functional individual wafers are equivalent to hard IP cores.

Acknowledgments

This research has been partially supported by the Interconnect Focus Center, sponsored by MARCO, DARPA, and NYSTAR. The Interconnect Focus Center is one of five research centers funded under the Focus Center Research Program, a DARPA and Semiconductor Research Corporation.

References

1 Lu, J.-Q. (2009) 3D hyper-integration and packaging technologies for micro-nano-systems. Proc. IEEE, 97 (1), 18–30.

2 Garrou, P., Ramm, P., and Bower, C. (eds) (2008) Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, Wiley-VCH Verlag GmbH, Weinheim.

3 Lu, J.-Q., Rose, K., and Vitkavage, S. (2007) 3D integration: why, what, who, when? Future Fab Int., 23, 25–27.

4 Meindl, J.D., Davis, J.A., Zarkesh-Ha, P., Patel, C.S., Martin, K.P., and Kohl, P.A. (2002) Interconnect opportunities for

gigascale research. IBM J. Res. Dev., 46 (2/3), 245–263.

5 Lu, J.-Q., Cale, T.S., and Gutmann, R.J. (2008) 3D integration based upon dielectric adhesive bonding, in Wafer Level 3-D ICS Process Technology (eds C.S. Tan, R.J. Gutmann, and R. Reif), Springer, pp. 219–256.

6 Niklaus, F., Stemme, G., Lu, J.-Q., and Gutmann, R. (2006) Adhesive wafer bonding. J. Appl. Phys., 99 (3), 031101.

7 Lu, J.-Q., Kwon, Y., Kraft, R.P., Gutmann, R.J., McDonald, J.F., and Cale, T.S. (2001) Stacked chip-to-chip


El



interconnections using wafer bonding technology with dielectric bonding glues. IEEE International Interconnect Technology Conference (IITC 2001), 4–6 June 2001, pp. 219–221.

8 Lu, J.-Q., Cale, T.S., and Gutmann, R.J. (2005) Wafer-level three-dimensional hyper-integration technology using dielectric adhesive wafer bonding, in Materials for Information Technology: Devices, Interconnects and Packaging (eds E. Zschech, C. Whelan, and T. Mikolajick), Springer-Verlag, Berlin, pp. 386–397.

9 Kwon, Y., Seok, J., Lu, J.-Q., Cale, T.S., and Gutmann, R.J. (2006) Critical adhesion energy of benzocyclobutene (BCB)-bonded wafers. J. Electrochem. Soc., 153 (4), G347–G352.

10 Lu, J.-Q., Lee, K.W., Kwon, Y., Rajagopalan, G., McMahon, J., Altemus, B., Gupta, M., Eisenbraun, E., Xu, B., Jindal, A., Kraft, R.P., McDonald, J.F., Castracane, J., Cale, T.S., Kaloyeros, A., and Gutmann, R.J. (2003) Processing of inter-wafer vertical interconnects in 3D ICs. MRS Proc., V18, 45–51.

11 Lu, J.-Q., Jindal, A., Kwon, Y., McMahon, J.J., Rasco, M., Augur, R., Cale, T.S., and Gutmann, R.J. (2003) Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs. IEEE International Interconnect Technology Conference (IITC 2003), June 2003, pp. 74–76.

12 Gutmann, R.J., Lu, J.-Q., Pozder, S., Kwon, Y., Menke, D., Jindal, A., Celik, M., Rasco, M., McMahon, J.J., Yu, K., and Cale, T.S. (2003) A wafer-level 3D IC technology platform. Advanced Metallization Conference (AMC 2003), pp. 19–26.

13 Pozder, S., Lu, J.-Q., Kwon, Y., Zollner, S., Yu, J., McMahon, J.J., Cale, T.S., Yu, K., and Gutmann, R.J. (2004) Back-end compatibility of bonding and thinning processes for a wafer-level 3D interconnect technology platform. IEEE International Interconnect Technology Conference (IITC 2004), June 2004, pp. 102–104.

14 Chen, K.-N., Lee, S.H., Andry, P.S., Tsang, C.K., Topol, A.W., Lin, Y.-M., Lu, J.-Q., Young, A.M., Ieong, M., and

Haensch, W. (2006) Structure design and process control for cu bonded interconnects in 3D integrated circuits. Technical Digest of the IEEE International Electron Devices Meeting (IEDM 2006), December 2006, pp. 367–370.

15 Chen, K.N., Tsang, C.K., Topol, A.W., Lee, S.H., Furman, B.K., Rath, D.L., J.-Q. Lu, Young A.M., Purushothaman, S., and Haensch, W. (2006) Improved manufacturability of cu bond pads and implementation of seal design in 3D integrated circuits and packages. 23rd International VLSI Multilevel Interconnection (VMIC) Conference, September 2006, pp. 195–202, IMIC.

16 Chen, K.N., Fan, A., Tan, C.S., and Reif, R. (2002) Microstructure evolution and abnormal grain growth during copper wafer bonding. Appl. Phys. Lett., 81 (20), 3774–3776.

17 Chen, K.N., Tan, C.S., Fan, A., and Reif, R. (2004) Morphology and bond strength of copper wafer bonding. Electrochem. Solid-State Lett., 7 (1), G14–G16.

18 Morrow, P., Park, C.-M., Ramanathan, S., Kobrinsky, M.J., and Harmes, M. (2006) Three-dimensional wafer stacking via Cu–Cu bonding integrated with 65-nm strained-Si/low-k CMOS technology. IEEE Electron Dev. Lett., 27 (5), 335–337.

19 Patti, R. (2006) Three-dimensional integrated circuits and the future of system-on-chip designs. Proc. IEEE, 94 (6), 1214–1222.

20 Lu, J.-Q., Jay McMahon, J., and Gutmann, R.J. (2007) Wafer bonding of damascene-patterned metal/adhesive redistribution layers. US Patent Application 20070207592, 6 September 2007.

21 McMahon, J.J., Lu, J.-Q., and Gutmann, R.J. (2005) Wafer bonding of damascene-patterned metal/adhesive redistribution layers for via-first 3D interconnect. 55th IEEE Electronic Components and Technology Conference (ECTC 2005), pp. 331–336.

22 Lu, J.-Q., McMahon, J.J., and Gutmann, R.J. (2006) Via-first inter-wafer vertical interconnects utilizing wafer-bonding of damascene-patterned metal/adhesive


El


References 235

redistribution layers. 3D Packaging Workshop at IMAPS Device Packaging Conference, Scottsdale, AZ, 20–23 March 2006, paper WP64.

23 McMahon, J.J., Niklaus, F., Kumar, R.J., Yu, J., Lu, J.-Q., and Gutmann, R.J. (2005) CMP compatibility of partially cured benzocyclobutene (BCB) for a via-first 3D IC process. MRS Proc., 867, W4.4.1–W4.4.6.

24 Gutmann, R.J., McMahon, J.J., and Lu, J.-Q. (2007) Damascene patterned metal/adhesive redistribution layers. MRS Proc., 970, 205–214.

25 McMahon, J.J., Chan, E., Lee, S.H., Gutmann, R.J., and Lu, J.-Q. (2008) Bonding interfaces in wafer-level metal/adhesive bonded 3D integration. 58th Electronic Components and Technology Conference (ECTC 2008), May 2008, pp. 871–878.

26 Swinnen, B., Jourdain, A., De Moor, P., and Beyne, E. (2008) Direct hybrid bonding, in Wafer Level 3-D ICs Process Technology (eds C.S. Tan, R.J. Gutmann, and R. Reif), Springer Science, New York, pp. 257–267.

27 McMahon, J.J., Gutmann, R.J., Smith, G., and Lu, J.-Q. (2008) A wafer-level 3D integration technology platform using damascene patterned metal/adhesive hybrid bonding. Proceedings of 25th International VLSI Multilevel Interconnection (VMIC) Conference (MIC 2008), Fremont, CA, 28–30 October 2008, pp. 337–342.

28 Guarini, K.W., Topol, A.W., Ieong, M., Yu, R., Shi, L., Newport, M.R., Frank, D.J., Singh, D.V., Cohen, G.M., Nitta, S.V., Boyd, D.C., O’Neil, P.A., Tempest, S.L., Pogge, H.B., Purushothaman, S., and Haensch, W.E. (2002) Electrical integrity of state-of-the-art 0.13 mm SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication. Technical Digest of the IEEE International Electron Devices Meeting (2002 IEDM), pp. 943–945.

29 Burns, J.A., Aull, B.F., Chen, C.K., Chen, C.-L., Keast, C.L., Knecht, J.M., Suntharalingam, V., Warner, K., Wyatt, P.W., and Yost, D.-R.W. (2006) A wafer-scale 3-D circuit integration

technology. IEEE Trans. Electron Dev., 53 (10), 2507–2516, October 2006.

30 Lu, J.-Q., McMahon1, J.J., and Gutmann, R.J. (2008) 3D integration using adhesive, metal, and metal/adhesive as wafer-level bonding interfaces. MRS Symp. Proc., 1112, 69–80.

31 DiCioccio, L., Gueguen, P., Gergaud, P., Zussy, M., Lafond, D., Gonchond, J.P., Rivoire, M., Scevola, D., and Clavelier, L. (2008) 3D vertical interconnects by copper direct bonding. MRS Symp. Proc., 1112, 81–89.

32 Enquist, P., Fountain, G., Petteway, C., Hollingsworth, A., and Grady, H. (2009) Low cost of ownership scalable copper direct bond interconnect 3D IC technology for three dimensional integrated circuit applications. Proceedings of the IEEE International 3D System Integration Conference (3D IC), San Francisco, CA, 28–30 September 2009.

33 Lu, J.-Q., Kwon, Y., Jindal, A., McMahon, J.J., Cale, T.S., and Gutmann, R.J. (2003) Dielectric glue wafer bonding and bonded wafer thinning for wafer-level 3D integration, in Semiconductor Wafer Bonding VII: Science, Technology, and Applications, (eds F.S. Bengtsson, H. Baumgart, C.E. Hunt, and T. Suga), Electrochemical Society, Pennington, NJ, pp. 76–86.

34 Kwon, Y., Seok, J., Lu, J.-Q., Cale, T.S., and Gutmann, R.J. (2005) Thermal cycling effects on critical adhesion energy and residual stress in benzocyclobutene (BCB)-bonded wafers. J. Electrochem. Soc., 152 (4), G286-G294.

35 Gutmann, R.J., Lu, J.-Q., Kraft, R.P., Belemjian, P.M., Erdogan, O., Barrett, J., and McDonald, J.F. (2001) IP core-based design, high-speed processor design and multiplexing LAN architectures enabled by 3D wafer bonding technologies. Proceedings of DesignCon 2001: Wireless and Optical Broadband Design Conference, Santa Clara, CA, 29 January–1 February 2001, paper WB-15.

36 Price, D.T., Gutmann, R.J., and Murarka, S.P. (1997) Damascene copper interconnects with polymer ILDs. Thin Solid Films, 308–309, 523–528.


El



37 Borst, C.L., Thakurta, D.G., Gill, W.N., and Gutmann, R.J. (2002) Chemical-mechanical planarization of low-k polymers for advanced IC structures, Trans. ASME J. Electron. Packag., 124 (4), 362–366.

38 Goldblatt, R.D., Agarwala, B., Anand, M.B., Barth, E.P., Biery, G.A., Chen, Z.G., Cohen, S., Connolly, J.B., Cowley, A., Dalton, T., Das, S.K., Davis, C.R., Deutsch, A., DeWan, C., Edelstein, D.C., Emmi, P.A., Faltermeier, C.G., Fitzsimmons, J.A., Hedrick, J., Heidenreich, J.E., Hu, C.K., Hummel, J.P., Jones, P., Kaltalioglu, E., Kastenmeier, B.E., Krishnan, M., Landers, W.F., Liniger, E., Liu, J., Lustig, N.E., Malhotra, S., Manger, D.K., McGahay, V., Mih, R., Nye, H.A., Purushothaman, S., Rathore, H.A., Seo, S.C., Shaw, T.M., Simon, A.H., Spooner, T.A., Stetter, M., Wachnik, R.A., and Ryan, J.G. (2000) A high performance 0.13 µm copper BEOL technology with low-k dielectric. Proceedings of the IEEE International Interconnect Technology Conference (IITC), June 2000, pp. 261–263.

39 Kuchenmeister, F., Stavreva, Z., Schubert, U., Richter, K., Wenzel, C., and Simmonds, M. (1998) A comparative CMP study of BCB and SiLK for copper damascene technologies. MRS Conf. Proc., 14, 237–248.

40 Gutmann, R.J., McMahon, J., and Lu, J.-Q. (2005) Global planarization requirements for wafer-level three-dimensional (3D) ICs. Proceedings of Surface Engineering and Coatings, Session on Chemical Mechanical Polishing (CMP), World Tribology Congress III, Washington, DC, 12–16 September 2005.

41 Lefevre, P. (2008) Defects observed on the wafer after the CMP process, in

Microelectronic Applications of Chemical Mechanical Planarization (ed. L. Yuzhuo), John Wiley & Sons, Inc., New York, pp. 511–561.

42 Tan, C., Reif, R., Theodore, N., and Pozder, S. (2005) Observation of interfacial void formation in bonded copper layers. Appl. Phys. Lett., 87, 201909.

43 McMahon, J.J., Lu, J.-Q., and Gutmann, R.J. (2008) Three Dimensional (3D) integration, in Microelectronic Applications of Chemical Mechanical Planarization (ed. Y. Li), John Wiley and Sons, pp. 431–465.

44 Stokich, T., Fulks, C., Bernius, M., Burdeaux, D., Garrou, P., and Heistand, R.H. (1993) Planarization with Cyclotene™ 3022 (BCB) polymer coatings. MRS Symp. Proc., 308, 517–526.

45 Dibbs, M.G., Townsend, P.H., Stokich, T.M., Huber, B.S., Mohler, C.E., Heistand, R.H., Garrou, P.E., Adema, G.M., Berry, M.J., and Turlik, I. (1992) Cure management of benzocyclobutene dielectric for electronic applications. SAMPE Conference, pp. 1–10.

46 Chen, K.N., Fan, A., Tan, C.S., and Reif, R. (2004) Contact resistance measurement of bonded copper interconnects for three-dimensional integration technology. IEEE Electron Dev. Lett., 25 (1), 10–12.

47 Shigetou, A., Itoh, T., Matsuo, M., Hayasaka, N., Okumura, K., and Suga, T. (2006) Bumpless interconnect through ultrafine Cu electrodes by means of surface-activated bonding method. IEEE Trans. Adv. Packag., 29 (2), 218–226.

48 Chen, K.N., Tan, C.S., and Reif, R. (2005) Abnormal contact resistance reduction of bonded copper interconnects in three-dimensional integration during current stressing. Appl. Phys. Lett., 86, 011903.


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Keywords:

Abstract:This chapter provides an overview of a hybrid metal/polymer wafer bonding plat-form using damascene-patterned intermediate layers for wafer bonding and elec-trical interconnections. This hybrid bonding platform combines the advantages of metal-to-metal bonding (for direct electrical interstrata interconnection) and polymer bonding (for robust thermomechanical wafer bonding strength and sur-face topography accommodation). Copper/benzocyclobutene (Cu/BCB) layers are selected for the demonstration vehicle. A detailed Cu/BCB bonding process base-line is described, and the results obtained are presented. The key issues of hybrid metal/polymer wafer bonding are discussed.

hybrid wafer bonding, copper/benzocyclobutene (Cu/BCB) bonding, topography accommodation, three-dimensional integration, through-strata via (TSV), bonded interstrata via (BISV)

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