CY8C29466 Automotive PSoC® Programmable …...CY8C29466 Document Number: 001-12899 Rev. *B Page 2...

CY8C29466

Automotive PSoC®

Programmable System-on-Chip

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document Number: 001-12899 Rev. *B Revised September 25, 2009

Features■ AEC Qualified

■ Powerful Harvard Architecture Processor❐ M8C Processor Speeds up to 24 MHz❐ Two 8x8 Multiply, 32-Bit Accumulate❐ Low Power at High Speed❐ 3.0V to 5.25V Operating Voltage❐ Automotive Temperature Range: -40°C to +85°C

■ Advanced Peripherals (PSoC® Blocks)❐ 12 Rail-to-Rail Analog PSoC Blocks Provide:

• Up to 14-Bit ADCs• Up to 9-Bit DACs• Programmable Gain Amplifiers• Programmable Filters and Comparators

❐ 16 Digital PSoC Blocks Provide:• 8- to 32-Bit Timers, Counters, and PWMs• CRC and PRS Modules• Up to Four Full-Duplex or Eight Half-Duplex UARTs• Multiple SPI Masters or Slaves• Connectable to all GPIO Pins

❐ Complex Peripherals by Combining Blocks

■ Precision, Programmable Clocking❐ Internal ±5% 24/48 MHz Oscillator❐ High Accuracy 24 MHz with Optional 32.768 kHz Crystal

and PLL❐ Optional External Oscillator, up to 24 MHz❐ Internal Low Speed, Low Power Oscillator for Watchdog and

Sleep Functionality

■ Flexible On-Chip Memory❐ 32K Bytes Flash Program Storage,

1000 Erase/Write Cycles❐ 2K Bytes SRAM Data Storage❐ In-System Serial Programming (ISSP)❐ Partial Flash Updates❐ Flexible Protection Modes❐ EEPROM Emulation in Flash

■ Programmable Pin Configurations❐ 25 mA Sink, 10 mA Drive on All GPIO❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive

Modes on All GPIO❐ Up to 12 Analog Inputs on GPIO[1]

❐ Four 30 mA Analog Outputs on GPIO❐ Configurable Interrupt on All GPIO

■ Additional System Resources❐ I2C Master, Slave, or Multi-Master Operation up to 400 kHz

❐ Watchdog and Sleep Timers❐ User-Configurable Low Voltage Detection❐ Integrated Supervisory Circuit❐ On-Chip Precision Voltage Reference

■ Complete Development Tools❐ Free Development Software (PSoC Designer™)❐ Full Featured In-Circuit Emulator and

Programmer❐ Full Speed Emulation❐ Complex Breakpoint Structure❐ 128K Bytes Trace Memory❐ Complex Events❐ C Compilers, Assembler, and Linker

Logic Block Diagram

DIGITAL SYSTEM

SRAM2K

InterruptController

Sleep and Watchdog

Multiple Clock Sources(Includes IMO, ILO, PLL, and ECO)

Global Digital InterconnectGlobal Analog Interconnect

PSoC CORE

CPU Core (M8C)

SROM Flash 32K

DigitalBlock Array

TwoMultiply Accums.

Internal Voltage

Ref.

Digital Clocks

POR and LVD

System ResetsDecimator

SYSTEM RESOURCES

ANALOG SYSTEM

Analog Block Array

Analog Ref.

Analog Input

Muxing

I C2

Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers

SYSTEM BUS

Note1. There are eight standard analog inputs on the GPIO. The other four analog inputs connect from the GPIO directly to specific switched-capacitor block inputs. See the

PSoC Technical Reference Manual for more details

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CY8C29466

Document Number: 001-12899 Rev. *B of 34

PSoC Functional OverviewThe PSoC programmable system-on-chip family consists ofmany devices with On-Chip Controllers. These devices aredesigned to replace multiple traditional MCU-based systemcomponents with one, low cost single-chip programmabledevice. PSoC devices include configurable blocks of analog anddigital logic, as well as programmable interconnects. This archi-tecture enables the user to create customized peripheral config-urations that match the requirements of each individual appli-cation. Additionally, a fast CPU, Flash program memory, SRAMdata memory, and configurable I/O are included in a range ofconvenient pinouts and packages.The PSoC architecture, as illustrated in the Logic Block Diagramon page 1, is comprised of four main areas: PSoC Core, DigitalSystem, Analog System, and System Resources. Configurableglobal buses allow all the device resources to be combined intoa complete custom system. The automotive PSoC CY8C29x66family can have up to three I/O ports that connect to the globaldigital and analog interconnects, providing access to 16 digitalblocks and 12 analog blocks.The PSoC Core is a powerful engine that supports a rich featureset. The core includes a CPU, memory, clocks, and configurableGPIO (General Purpose IO).The M8C CPU core is a powerful processor with speeds up to24 MHz, providing a four MIPS 8-bit Harvard architecture micro-processor. The CPU utilizes an interrupt controller with 25vectors, to simplify programming of real time embedded events.Program execution is timed and protected using the includedSleep Timer and Watch Dog Timer (WDT).Memory includes 32K of Flash for program storage and 2K ofSRAM for data storage. Program Flash utilizes four protectionlevels on blocks of 64 bytes, allowing customized software IPprotection.The PSoC device incorporates flexible internal clock generators,including a 24 MHz IMO (internal main oscillator) accurate to±5% over temperature and voltage. A low power 32 kHz ILO(internal low speed oscillator) is provided for the Sleep Timer andWDT. If crystal accuracy is desired, the ECO (32.768 kHzexternal crystal oscillator) is available for use as a Real TimeClock (RTC) and can optionally generate a crystal-accurate 24MHz system clock using a PLL. The clocks, together withprogrammable clock dividers (as a System Resource), providethe flexibility to integrate almost any timing requirement into thePSoC device.PSoC GPIOs provide connection to the CPU, digital resources,and analog resources of the device. Each pin’s drive mode maybe selected from eight options, allowing great flexibility inexternal interfacing. Every pin also has the capability to generatea system interrupt.

The Digital SystemThe Digital System is composed of 16 digital PSoC blocks. Eachblock is an 8-bit resource that can be used alone or combinedwith other blocks to form 8, 16, 24, and 32-bit peripherals, whichare called user modules. Digital peripheral configurations includethose listed here.

■ PWMs (8 to 32 bit)

■ PWMs with Dead Band (8 to 24 bit)

■ Counters (8 to 32 bit)

■ Timers (8 to 32 bit)

■ Full or Half-Duplex 8-bit UART with selectable parity (up to 4 Full-Duplex or 8 Half-Duplex)

■ SPI master and slave (up to 8 total)

■ I2C master, slave, or multi-master

■ Cyclical Redundancy Checker/Generator (16 bit)

■ IrDA (up to 4)

■ Pseudo Random Sequence Generators (8 to 32 bit)The digital blocks can be connected to any GPIO through aseries of global buses that can route any signal to any pin. Thebuses also allow for signal multiplexing and for performing logicoperations. This configurability frees your designs from theconstraints of a fixed peripheral controller.Digital blocks are provided in rows of four, where the number ofblocks varies by PSoC device family. This allows the optimumchoice of system resources for your application. Familyresources are shown in Table 1 on page 4.

Figure 1. Digital System Block Diagram

DIGITAL SYSTEM

To System BusDigital Clocks From Core

Digital PSoC Block Array

To Analog System

8

Row

Inpu

t C

onfig

urat

ion R

ow O

utput C

onfiguration

88

8

Row 1

DBB10 DBB11 DCB12 DCB13

Row

Inpu

t C

onfig

urat

ion 4

4

Row

Output

Configuration

Row

Inpu

t C

onfig

urat

ion R

ow O

utput C

onfiguration

Row 2


4

4

Row 0


4

4

Row

Inpu

t C

onfig

urat

ion R

ow O

utput C

onfiguration

Row 3


4

4

GIE[7:0]

GIO[7:0]

GOE[7:0]

GOO[7:0]Global Digital Interconnect

Port 5

Port 4

Port 3

Port 2

Port 1

Port 0

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The Analog SystemThe Analog System is composed of 12 configurable blocks, eachcomprised of an opamp circuit allowing the creation of complexanalog signal flows. Analog peripherals are very flexible and canbe customized to support specific application requirements.Some of the common PSoC analog functions for this device(most available as user modules) are as follows:

■ Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta-Sigma, and SAR)

■ Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch)

■ Amplifiers (up to 4, with selectable gain up to 48x)

■ Instrumentation amplifiers (up to 2, with selectable gain up to 93x)

■ Comparators (up to 4, with 16 selectable thresholds)

■ DACs (up to 4, with 6- to 9-bit resolution)

■ Multiplying DACs (up to 4, with 6- to 9-bit resolution)

■ High current output drivers (four with 30 mA drive as a PSoC Core resource)

■ 1.3V reference (as a System Resource)

■ DTMF Dialer

■ Correlators

■ Peak Detectors

■ Many other topologies possibleAnalog blocks are provided in columns of three, which includesone CT (Continuous Time) and two SC (Switched Capacitor)blocks, as shown in Figure 2.

Figure 2. Analog System Block Diagram

ACB00 ACB01

Block Array

Array Input Configuration

ACI1[1:0] ACI2[1:0]

ACB02 ACB03

ASC12 ASD13

ASD22 ASC23ASD20

ACI0[1:0] ACI3[1:0]

P0[6]

P0[4]

P0[2]

P0[0]

P2[2]

P2[0]

P2[6]

P2[4]

Ref

InAG

ND

In

P0[7]

P0[5]

P0[3]

P0[1]

P2[3]

P2[1]

Reference Generators

AGNDInRefInBandgap

RefHiRefLoAGND

ASD11

ASC21

ASC10

Interface to Digital System

M8C Interface (Address Bus, Data Bus, Etc.)

Analog Reference

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Additional System ResourcesSystem Resources, some of which have been previously listed,provide additional capability useful for complete systems.Additional resources include a multiplier, decimator, low voltagedetection, and power on reset. Brief statements describing themerits of each system resource are given below:

■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers.

■ Two multiply accumulates (MACs) provide fast 8-bit multiplier with 32-bit accumulate to assist in both general math as well as digital filters.

■ The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs.

■ The I2C module provides 0 to 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported.

■ Low Voltage Detection (LVD) interrupts can signal the appli-cation of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor.

■ An internal 1.3V voltage reference provides an absolute reference for the analog system, including ADCs and DACs.

PSoC Device CharacteristicsDepending on your PSoC device characteristics, the digital andanalog systems can have a varying number of digital and analogblocks. The following table lists the resources available forspecific PSoC device groups. The PSoC device covered by thisdata sheet is highlighted in Table 1.

Getting StartedThe quickest way to understand PSoC silicon is to read this datasheet and then use the PSoC Designer Integrated DevelopmentEnvironment (IDE). This data sheet is an overview of the PSoCintegrated circuit and presents specific pin, register, andelectrical specifications. For in depth information, along with detailed programmingdetails, see the PSoC® Technical Reference Manual forCY8C29x66 PSoC devices.For up-to-date ordering, packaging, and electrical specificationinformation, see the latest PSoC device data sheets on the webat www.cypress.com/psoc.

Application NotesApplication notes are an excellent introduction to the wide varietyof possible PSoC designs. They are located here:www.cypress.com/psoc. Select Application Notes under theDocumentation tab.

Development KitsPSoC Development Kits are available online from Cypress atwww.cypress.com/shop and through a growing number ofregional and global distributors, which include Arrow, Avnet,Digi-Key, Farnell, Future Electronics, and Newark.

TrainingFree PSoC technical training (on demand, webinars, andworkshops) is available online at www.cypress.com/training. Thetraining covers a wide variety of topics and skill levels to assistyou in your designs.

Cypros ConsultantsCertified PSoC Consultants offer everything from technicalassistance to completed PSoC designs. To contact or become aPSoC Consultant go to www.cypress.com/cypros.

Solutions LibraryVisit our growing library of solution focused designs atwww.cypress.com/solutions. Here you can find various appli-cation designs that include firmware and hardware design filesthat enable you to complete your designs quickly.

Technical SupportFor assistance with technical issues, search KnowledgeBasearticles and forums at www.cypress.com/support. If you cannotfind an answer to your question, call technical support at1-800-541-4736.

Table 1. PSoC Device Characteristics

PSoC PartNumber

Dig

ital

I/O

Dig

ital

Row

s

Dig

ital

Blo

cks

Ana

log

Inpu

ts

Ana

log

Out

puts

Ana

log

Col

umns

Ana

log

Blo

cks

SRA

MSi

ze

Flas

h Si

ze

CY8C29x66[2] up to 64

4 16 12 4 4 12 2K 32K

CY8C27x43 up to 44

2 8 12 4 4 12 256 Bytes

16K

CY8C24x94 64 1 4 48 2 2 6 1K 16K

CY8C24x23A[2] up to 24

1 4 12 2 2 6 256 Bytes

4K

CY8C23x33 up to 1 4 12 2 2 4 256 Bytes

8K

CY8C21x34[2] up to 28

1 4 28 0 2 4[3] 512 Bytes

8K

CY8C21x23 16 1 4 8 0 2 4[3] 256 Bytes

4K

CY8C20x34 up to 28

0 0 28 0 0 3[3,4] 512 Bytes

8K

Notes2. Automotive qualified devices available in this group.3. Limited analog functionality.4. Two analog blocks and one CapSense.

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Development ToolsPSoC Designer is a Microsoft® Windows-based, integrateddevelopment environment for the ProgrammableSystem-on-Chip (PSoC) devices. The PSoC Designer IDE runson Windows XP or Windows Vista. This system provides design database management by project,an integrated debugger with In-Circuit Emulator, in-systemprogramming support, and built-in support for third-partyassemblers and C compilers. PSoC Designer also supports C language compilers developedspecifically for the devices in the PSoC family.

PSoC Designer Software Subsystems

System-Level ViewA drag-and-drop visual embedded system design environmentbased on PSoC Express. In the system level view you create amodel of your system inputs, outputs, and communication inter-faces. You define when and how an output device changes statebased upon any or all other system devices. Based upon thedesign, PSoC Designer automatically selects one or more PSoCMixed-Signal Controllers that match your system requirements.PSoC Designer generates all embedded code, then compilesand links it into a programming file for a specific PSoC device.

Chip-Level ViewThe chip-level view is a more traditional integrated developmentenvironment (IDE) based on PSoC Designer 4.4. Choose a basedevice to work with and then select different onboard analog anddigital components called user modules that use the PSoCblocks. Examples of user modules are ADCs, DACs, Amplifiers,and Filters. Configure the user modules for your chosenapplication and connect them to each other and to the properpins. Then generate your project. This prepopulates your projectwith APIs and libraries that you can use to program yourapplication.The device editor also supports easy development of multipleconfigurations and dynamic reconfiguration. Dynamicconfiguration allows for changing configurations at run time.

Hybrid DesignsYou can begin in the system-level view, allow it to choose andconfigure your user modules, routing, and generate code, thenswitch to the chip-level view to gain complete control overon-chip resources. All views of the project share a common codeeditor, builder, and common debug, emulation, and programmingtools.

Code Generation ToolsPSoC Designer supports multiple third party C compilers andassemblers. The code generation tools work seamlessly withinthe PSoC Designer interface and have been tested with a fullrange of debugging tools. The choice is yours.

Assemblers. The assemblers allow assembly code to mergeseamlessly with C code. Link libraries automatically use absoluteaddressing or are compiled in relative mode, and linked withother software modules to get absolute addressing.

C Language Compilers. C language compilers are availablethat support the PSoC family of devices. The products allow youto create complete C programs for the PSoC family devices.The optimizing C compilers provide all the features of C tailoredto the PSoC architecture. They come complete with embeddedlibraries providing port and bus operations, standard keypad anddisplay support, and extended math functionality.

DebuggerThe PSoC Designer Debugger subsystem provides hardwarein-circuit emulation, allowing you to test the program in a physicalsystem while providing an internal view of the PSoC device.Debugger commands allow the designer to read and programand read and write data memory, read and write I/O registers,read and write CPU registers, set and clear breakpoints, andprovide program run, halt, and step control. The debugger alsoallows the designer to create a trace buffer of registers andmemory locations of interest.

Online Help SystemThe online help system displays online, context-sensitive helpfor the user. Designed for procedural and quick reference, eachfunctional subsystem has its own context-sensitive help. Thissystem also provides tutorials and links to FAQs and an OnlineSupport Forum to aid the designer in getting started.

In-Circuit EmulatorA low cost, high functionality ICE (In-Circuit Emulator) isavailable for development support. This hardware has thecapability to program single devices.The emulator consists of a base unit that connects to the PC byway of a USB port. The base unit is universal and operates withall PSoC devices. Emulation pods for each device family areavailable separately. The emulation pod takes the place of thePSoC device in the target board and performs full speed (24MHz) operation.

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Designing with PSoC DesignerThe development process for the PSoC device differs from thatof a traditional fixed function microprocessor. The configurableanalog and digital hardware blocks give the PSoC architecture aunique flexibility that pays dividends in managing specificationchange during development and by lowering inventory costs.These configurable resources, called PSoC Blocks, have theability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in thefollowing four steps: 1. Select components2. Configure components3. Organize and Connect4. Generate, Verify, and Debug

Select ComponentsBoth the system-level and chip-level views provide a library ofprebuilt, pretested hardware peripheral components. In thesystem-level view, these components are called “drivers” andcorrespond to inputs (a thermistor, for example), outputs (abrushless DC fan, for example), communication interfaces(I2C-bus, for example), and the logic to control how they interactwith one another (called valuators). In the chip-level view, the components are called “user modules”.User modules make selecting and implementing peripheraldevices simple, and come in analog, digital, and mixed signalvarieties.

Configure ComponentsEach of the components you select establishes the basic registersettings that implement the selected function. They also provideparameters and properties that allow you to tailor their preciseconfiguration to your particular application. For example, a PulseWidth Modulator (PWM) User Module configures one or moredigital PSoC blocks, one for each 8 bits of resolution. The usermodule parameters permit you to establish the pulse width andduty cycle. Configure the parameters and properties tocorrespond to your chosen application. Enter values directly orby selecting values from drop-down menus.Both the system-level drivers and chip-level user modules aredocumented in data sheets that are viewed directly in the PSoCDesigner. These data sheets explain the internal operation of thecomponent and provide performance specifications. Each datasheet describes the use of each user module parameter or driverproperty, and other information you may need to successfullyimplement your design.

Organize and ConnectYou can build signal chains at the chip level by interconnectinguser modules to each other and the I/O pins, or connect systemlevel inputs, outputs, and communication interfaces to eachother with valuator functions.In the system-level view, selecting a potentiometer driver tocontrol a variable speed fan driver and setting up the valuatorsto control the fan speed based on input from the pot selects,places, routes, and configures a programmable gain amplifier(PGA) to buffer the input from the potentiometer, an analog todigital converter (ADC) to convert the potentiometer’s output toa digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, androuting so that you have complete control over the use of allon-chip resources.

Generate, Verify, and DebugWhen you are ready to test the hardware configuration or moveon to developing code for the project, perform the “GenerateApplication” step. This causes PSoC Designer to generatesource code that automatically configures the device to yourspecification and provides the software for the system.Both system-level and chip-level designs generate softwarebased on your design. The chip-level design provides applicationprogramming interfaces (APIs) with high level functions tocontrol and respond to hardware events at run-time and interruptservice routines that you can adapt as needed. The system-leveldesign also generates a C main() program that completelycontrols the chosen application and contains placeholders forcustom code at strategic positions allowing you to further refinethe software without disrupting the generated code.A complete code development environment allows you todevelop and customize your applications in C, assemblylanguage, or both.The last step in the development process takes place inside thePSoC Designer’s Debugger subsystem. The Debuggerdownloads the HEX image to the In-Circuit Emulator (ICE) whereit runs at full speed. Debugger capabilities rival those of systemscosting many times more. In addition to traditional single-step,run-to-breakpoint and watch-variable features, the Debuggerprovides a large trace buffer and allows you define complexbreakpoint events that include monitoring address and data busvalues, memory locations and external signals.

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Document ConventionsAcronyms UsedThe following table lists the acronyms that are used in thisdocument.

Units of MeasureA units of measure table is located in the Electrical Specificationssection. Table 7 on page 12 lists all the abbreviations used tomeasure the PSoC devices.

Numeric NamingHexadecimal numbers are represented with all letters inuppercase with an appended lowercase ‘h’ (for example, ‘14h’ or‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’prefix, the C coding convention. Binary numbers have anappended lowercase ‘b’ (for example, ‘01010100b’ or‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ aredecimal.

Table 2. AcronymsAcronym DescriptionAC alternating currentADC analog-to-digital converterAPI application programming interfaceCPU central processing unitCT continuous timeDAC digital-to-analog converterDC direct currentECO external crystal oscillatorEEPROM electrically erasable programmable read-only

memoryFSR full scale rangeGPIO general purpose IOGUI graphical user interfaceHBM human body modelICE in-circuit emulatorILO internal low speed oscillatorIMO internal main oscillatorI/O input/outputIPOR imprecise power on resetLSb least-significant bitLVD low voltage detectMSb most-significant bitPC program counterPLL phase-locked loopPOR power on resetPPOR precision power on resetPSoC Programmable System-on-ChipPWM pulse width modulatorSC switched capacitorSRAM static random access memory

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PinoutsThe automotive CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables.Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.

28-Pin Part Pinout

Table 3. 28-Pin Part Pinout (SSOP)Pin No.

Type Pin Name Description Figure 3. CY8C29466 28-Pin PSoC Device

Digital Analog1 I/O I P0[7] Analog column mux input.2 I/O I/O P0[5] Analog column mux input and column output.3 I/O I/O P0[3] Analog column mux input and column output.4 I/O I P0[1] Analog column mux input.5 I/O P2[7]6 I/O P2[5]7 I/O I P2[3] Direct switched capacitor block input.8 I/O I P2[1] Direct switched capacitor block input.9 Power Vss Ground connection.10 I/O P1[7] I2C Serial Clock (SCL).11 I/O P1[5] I2C Serial Data (SDA).12 I/O P1[3]13 I/O P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL),

ISSP-SCLK[5].14 Power Vss Ground connection.15 I/O P1[0] Crystal Output (XTALout), I2C Serial Data

(SDA), ISSP-SDATA[5].16 I/O P1[2]17 I/O P1[4] Optional External Clock Input (EXTCLK).18 I/O P1[6] 19 Input XRES Active high external reset with internal pull

down.20 I/O I P2[0] Direct switched capacitor block input.21 I/O I P2[2] Direct switched capacitor block input.22 I/O P2[4] External Analog Ground (AGND).23 I/O P2[6] External Voltage Reference (VRef).24 I/O I P0[0] Analog column mux input.25 I/O I/O P0[2] Analog column mux input and column output.26 I/O I/O P0[4] Analog column mux input and column output.27 I/O I P0[6] Analog column mux input.28 Power Vdd Supply voltage.

LEGEND: A = Analog, I = Input, and O = Output.

SSOP

2827262524232221201918171615

123456789

1011121314

AI, P0[7]AIO, P0[5]AIO, P0[3]

AI, P0[1]P2[7]P2[5]

AI, P2[3]AI, P2[1]

VssI2C SCL, P1[7]I2C SDA, P1[5]

P1[3]I2C SCL, XTALin, P1[1]

Vss

VddP0[6], AIP0[4], AIOP0[2], AIOP0[0], AIP2[6], External VRefP2[4], External AGNDP2[2], AIP2[0], AIXRESP1[6]P1[4], EXTCLKP1[2]P1[0], XTALout, I2C SDA

Note5. These are the ISSP pins, which are not High Z when coming out of POR (Power On Reset). See the PSoC Technical Reference Manual for details.

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RegistersRegister ConventionsThis section lists the the registers of the automotive CY8C29x66PSoC device. For detailed register information, reference thePSoC Technical Reference Manual.The register conventions specific to this section are listed in thefollowing table.

Register Mapping TablesThe PSoC device has a total register address space of 512bytes. The register space is referred to as I/O space and isdivided into two banks. The XIO bit in the Flag register (CPU_F)determines which bank the user is currently in. When the XIO bitis set the user is in Bank 1.Note In the following register mapping tables, blank fields areReserved and should not be accessed.Table 4. Abbreviations

Convention DescriptionR Read register or bit(s)W Write register or bit(s)L Logical register or bit(s)C Clearable register or bit(s)# Access is bit specific

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CY8C29466


Table 5. Register Map Bank 0 Table: User Space Name Addr (0, Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access Name Addr (0,Hex) Access

PRT0DR 00 RW DBB20DR0 40 # ASC10CR0 80 RW RDI2RI C0 RWPRT0IE 01 RW DBB20DR1 41 W ASC10CR1 81 RW RDI2SYN C1 RWPRT0GS 02 RW DBB20DR2 42 RW ASC10CR2 82 RW RDI2IS C2 RWPRT0DM2 03 RW DBB20CR0 43 # ASC10CR3 83 RW RDI2LT0 C3 RWPRT1DR 04 RW DBB21DR0 44 # ASD11CR0 84 RW RDI2LT1 C4 RWPRT1IE 05 RW DBB21DR1 45 W ASD11CR1 85 RW RDI2RO0 C5 RWPRT1GS 06 RW DBB21DR2 46 RW ASD11CR2 86 RW RDI2RO1 C6 RWPRT1DM2 07 RW DBB21CR0 47 # ASD11CR3 87 RW C7PRT2DR 08 RW DCB22DR0 48 # ASC12CR0 88 RW RDI3RI C8 RWPRT2IE 09 RW DCB22DR1 49 W ASC12CR1 89 RW RDI3SYN C9 RWPRT2GS 0A RW DCB22DR2 4A RW ASC12CR2 8A RW RDI3IS CA RWPRT2DM2 0B RW DCB22CR0 4B # ASC12CR3 8B RW RDI3LT0 CB RWPRT3DR 0C RW DCB23DR0 4C # ASD13CR0 8C RW RDI3LT1 CC RWPRT3IE 0D RW DCB23DR1 4D W ASD13CR1 8D RW RDI3RO0 CD RWPRT3GS 0E RW DCB23DR2 4E RW ASD13CR2 8E RW RDI3RO1 CE RWPRT3DM2 0F RW DCB23CR0 4F # ASD13CR3 8F RW CFPRT4DR 10 RW DBB30DR0 50 # ASD20CR0 90 RW CUR_PP D0 RWPRT4IE 11 RW DBB30DR1 51 W ASD20CR1 91 RW STK_PP D1 RWPRT4GS 12 RW DBB30DR2 52 RW ASD20CR2 92 RW D2PRT4DM2 13 RW DBB30CR0 53 # ASD20CR3 93 RW IDX_PP D3 RWPRT5DR 14 RW DBB31DR0 54 # ASC21CR0 94 RW MVR_PP D4 RWPRT5IE 15 RW DBB31DR1 55 W ASC21CR1 95 RW MVW_PP D5 RWPRT5GS 16 RW DBB31DR2 56 RW ASC21CR2 96 RW I2C_CFG D6 RWPRT5DM2 17 RW DBB31CR0 57 # ASC21CR3 97 RW I2C_SCR D7 #

18 DCB32DR0 58 # ASD22CR0 98 RW I2C_DR D8 RW19 DCB32DR1 59 W ASD22CR1 99 RW I2C_MSCR D9 #1A DCB32DR2 5A RW ASD22CR2 9A RW INT_CLR0 DA RW1B DCB32CR0 5B # ASD22CR3 9B RW INT_CLR1 DB RW1C DCB33DR0 5C # ASC23CR0 9C RW INT_CLR2 DC RW1D DCB33DR1 5D W ASC23CR1 9D RW INT_CLR3 DD RW1E DCB33DR2 5E RW ASC23CR2 9E RW INT_MSK3 DE RW1F DCB33CR0 5F # ASC23CR3 9F RW INT_MSK2 DF RW

DBB00DR0 20 # AMX_IN 60 RW A0 INT_MSK0 E0 RWDBB00DR1 21 W 61 A1 INT_MSK1 E1 RWDBB00DR2 22 RW 62 A2 INT_VC E2 RCDBB00CR0 23 # ARF_CR 63 RW A3 RES_WDT E3 WDBB01DR0 24 # CMP_CR0 64 # A4 DEC_DH E4 RCDBB01DR1 25 W ASY_CR 65 # A5 DEC_DL E5 RCDBB01DR2 26 RW CMP_CR1 66 RW A6 DEC_CR0 E6 RWDBB01CR0 27 # 67 A7 DEC_CR1 E7 RWDCB02DR0 28 # 68 MUL1_X A8 W MUL0_X E8 WDCB02DR1 29 W 69 MUL1_Y A9 W MUL0_Y E9 WDCB02DR2 2A RW 6A MUL1_DH AA R MUL0_DH EA RDCB02CR0 2B # 6B MUL1_DL AB R MUL0_DL EB RDCB03DR0 2C # TMP_DR0 6C RW ACC1_DR1 AC RW ACC0_DR1 EC RWDCB03DR1 2D W TMP_DR1 6D RW ACC1_DR0 AD RW ACC0_DR0 ED RWDCB03DR2 2E RW TMP_DR2 6E RW ACC1_DR3 AE RW ACC0_DR3 EE RWDCB03CR0 2F # TMP_DR3 6F RW ACC1_DR2 AF RW ACC0_DR2 EF RWDBB10DR0 30 # ACB00CR3 70 RW RDI0RI B0 RW F0DBB10DR1 31 W ACB00CR0 71 RW RDI0SYN B1 RW F1DBB10DR2 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2DBB10CR0 33 # ACB00CR2 73 RW RDI0LT0 B3 RW F3DBB11DR0 34 # ACB01CR3 74 RW RDI0LT1 B4 RW F4DBB11DR1 35 W ACB01CR0 75 RW RDI0RO0 B5 RW F5DBB11DR2 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6DBB11CR0 37 # ACB01CR2 77 RW B7 CPU_F F7 RLDCB12DR0 38 # ACB02CR3 78 RW RDI1RI B8 RW F8DCB12DR1 39 W ACB02CR0 79 RW RDI1SYN B9 RW F9DCB12DR2 3A RW ACB02CR1 7A RW RDI1IS BA RW FADCB12CR0 3B # ACB02CR2 7B RW RDI1LT0 BB RW FBDCB13DR0 3C # ACB03CR3 7C RW RDI1LT1 BC RW FCDCB13DR1 3D W ACB03CR0 7D RW RDI1RO0 BD RW FDDCB13DR2 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #DCB13CR0 3F # ACB03CR2 7F RW BF CPU_SCR0 FF #Blank fields are Reserved and should not be accessed. # Access is bit specific.

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CY8C29466


Table 6. Register Map Bank 1 Table: Configuration Space Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access Name Addr (1,Hex) Access

PRT0DM0 00 RW DBB20FN 40 RW ASC10CR0 80 RW RDI2RI C0 RWPRT0DM1 01 RW DBB20IN 41 RW ASC10CR1 81 RW RDI2SYN C1 RWPRT0IC0 02 RW DBB20OU 42 RW ASC10CR2 82 RW RDI2IS C2 RWPRT0IC1 03 RW 43 ASC10CR3 83 RW RDI2LT0 C3 RWPRT1DM0 04 RW DBB21FN 44 RW ASD11CR0 84 RW RDI2LT1 C4 RWPRT1DM1 05 RW DBB21IN 45 RW ASD11CR1 85 RW RDI2RO0 C5 RWPRT1IC0 06 RW DBB21OU 46 RW ASD11CR2 86 RW RDI2RO1 C6 RWPRT1IC1 07 RW 47 ASD11CR3 87 RW C7PRT2DM0 08 RW DCB22FN 48 RW ASC12CR0 88 RW RDI3RI C8 RWPRT2DM1 09 RW DCB22IN 49 RW ASC12CR1 89 RW RDI3SYN C9 RWPRT2IC0 0A RW DCB22OU 4A RW ASC12CR2 8A RW RDI3IS CA RWPRT2IC1 0B RW 4B ASC12CR3 8B RW RDI3LT0 CB RWPRT3DM0 0C RW DCB23FN 4C RW ASD13CR0 8C RW RDI3LT1 CC RWPRT3DM1 0D RW DCB23IN 4D RW ASD13CR1 8D RW RDI3RO0 CD RWPRT3IC0 0E RW DCB23OU 4E RW ASD13CR2 8E RW RDI3RO1 CE RWPRT3IC1 0F RW 4F ASD13CR3 8F RW CFPRT4DM0 10 RW DBB30FN 50 RW ASD20CR0 90 RW GDI_O_IN D0 RWPRT4DM1 11 RW DBB30IN 51 RW ASD20CR1 91 RW GDI_E_IN D1 RWPRT4IC0 12 RW DBB30OU 52 RW ASD20CR2 92 RW GDI_O_OU D2 RWPRT4IC1 13 RW 53 ASD20CR3 93 RW GDI_E_OU D3 RWPRT5DM0 14 RW DBB31FN 54 RW ASC21CR0 94 RW D4PRT5DM1 15 RW DBB31IN 55 RW ASC21CR1 95 RW D5PRT5IC0 16 RW DBB31OU 56 RW ASC21CR2 96 RW D6PRT5IC1 17 RW 57 ASC21CR3 97 RW D7

18 DCB32FN 58 RW ASD22CR0 98 RW D819 DCB32IN 59 RW ASD22CR1 99 RW D91A DCB32OU 5A RW ASD22CR2 9A RW DA1B 5B ASD22CR3 9B RW DB1C DCB33FN 5C RW ASC23CR0 9C RW DC1D DCB33IN 5D RW ASC23CR1 9D RW OSC_GO_EN DD RW1E DCB33OU 5E RW ASC23CR2 9E RW OSC_CR4 DE RW1F 5F ASC23CR3 9F RW OSC_CR3 DF RW

DBB00FN 20 RW CLK_CR0 60 RW A0 OSC_CR0 E0 RWDBB00IN 21 RW CLK_CR1 61 RW A1 OSC_CR1 E1 RWDBB00OU 22 RW ABF_CR0 62 RW A2 OSC_CR2 E2 RW

23 AMD_CR0 63 RW A3 VLT_CR E3 RWDBB01FN 24 RW 64 A4 VLT_CMP E4 RDBB01IN 25 RW 65 A5 E5DBB01OU 26 RW AMD_CR1 66 RW A6 E6

27 ALT_CR0 67 RW A7 E7DCB02FN 28 RW ALT_CR1 68 RW A8 IMO_TR E8 WDCB02IN 29 RW CLK_CR2 69 RW A9 ILO_TR E9 WDCB02OU 2A RW 6A AA BDG_TR EA RW

2B 6B AB ECO_TR EB WDCB03FN 2C RW TMP_DR0 6C RW AC ECDCB03IN 2D RW TMP_DR1 6D RW AD EDDCB03OU 2E RW TMP_DR2 6E RW AE EE

2F TMP_DR3 6F RW AF EFDBB10FN 30 RW ACB00CR3 70 RW RDI0RI B0 RW F0DBB10IN 31 RW ACB00CR0 71 RW RDI0SYN B1 RW F1DBB10OU 32 RW ACB00CR1 72 RW RDI0IS B2 RW F2

33 ACB00CR2 73 RW RDI0LT0 B3 RW F3DBB11FN 34 RW ACB01CR3 74 RW RDI0LT1 B4 RW F4DBB11IN 35 RW ACB01CR0 75 RW RDI0RO0 B5 RW F5DBB11OU 36 RW ACB01CR1 76 RW RDI0RO1 B6 RW F6

37 ACB01CR2 77 RW B7 CPU_F F7 RLDCB12FN 38 RW ACB02CR3 78 RW RDI1RI B8 RW F8DCB12IN 39 RW ACB02CR0 79 RW RDI1SYN B9 RW F9DCB12OU 3A RW ACB02CR1 7A RW RDI1IS BA RW FLS_PR1 FA RW

3B ACB02CR2 7B RW RDI1LT0 BB RW FBDCB13FN 3C RW ACB03CR3 7C RW RDI1LT1 BC RW FCDCB13IN 3D RW ACB03CR0 7D RW RDI1RO0 BD RW FDDCB13OU 3E RW ACB03CR1 7E RW RDI1RO1 BE RW CPU_SCR1 FE #

3F ACB03CR2 7F RW BF CPU_SCR0 FF #Blank fields are Reserved and should not be accessed. # Access is bit specific.

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CY8C29466


Electrical SpecificationsThis section presents the DC and AC electrical specifications of the CY8C29x66 PSoC device. For the most up to date electricalspecifications, confirm that you have the most recent data sheet by visiting http://www.cypress.com/psoc.Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted.Refer to Table 20 on page 21 for the electrical specifications of the Internal Main Oscillator (IMO) using Slow IMO (SLIMO) mode.

Figure 4. Voltage versus CPU Frequency Figure 5. IMO Frequency Trim Options

The following table lists the units of measure that are used in this section.

5.25

4.75

93 kHz 24 MHzCPU Frequency

(nominal setting)

Vdd Voltage (V)

012 MHz

3.0

Valid

Operating

Region

SLIMO Mode=0

SLIMO Mode=0

SLIMO Mode=1

5.25

4.75

6 MHz 24 MHz

IMO Frequency

Vdd Voltage (V)

012 MHz

3.0

3.6SLIMO

Mode=1

Table 7. Units of Measure

Symbol Unit of Measure Symbol Unit of Measure°C degree Celsius μVrms microvolts root-mean-squaredB decibels μW microwattsfF femto farad mA milli-ampereHz hertz ms milli-secondKB 1024 bytes mV milli-voltsKbit 1024 bits nA nanoamperekHz kilohertz ns nanosecondkΩ kilohm nV nanovolts

Mbaud megabaud Ω ohmMbps megabits per second pA picoampereMHz megahertz pF picofaradMΩ megaohm pp peak-to-peakμA microampere ppm parts per millionμF microfarad ps picosecondμH microhenry sps samples per secondμs microsecond σ sigma: one standard deviationμV microvolts V volts

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Absolute Maximum Ratings

Operating Temperature

Symbol Description Min Typ Max Units NotesTSTG Storage Temperature -55 25 +100 °C Higher storage temperatures reduce

data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 65°C degrades reliability.

TA Ambient Temperature with Power Applied -40 – +85 °CVdd Supply Voltage on Vdd Relative to Vss -0.5 – +6.0 VVIO DC Input Voltage Vss - 0.5 – Vdd + 0.5 VVIOZ DC Voltage Applied to Tristate Vss - 0.5 – Vdd + 0.5 VIMIO Maximum Current into any Port Pin -25 – +50 mAIMAIO Maximum Current into any Port Pin Configured

as Analog Driver-50 – +50 mA

ESD Electro Static Discharge Voltage 2000 – – V Human Body Model ESD.LU Latch Up Current – – 200 mA

Symbol Description Min Typ Max Units NotesTA Ambient Temperature -40 – +85 °CTJ Junction Temperature -40 – +100 °C The temperature rise from ambient

to junction is package specific. See Thermal Impedances on page 30. The user must limit the power consumption to comply with this requirement.

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CY8C29466


DC Electrical Characteristics

DC Chip-Level SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

DC General Purpose I/O SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 8. DC Chip-Level Specifications

Symbol Description Min Typ Max Units NotesVdd Supply Voltage 3.00 – 5.25 V See DC POR and LVD Specifications on

page 19.IDD Supply Current – 8 14 mA Conditions are 5.25V, CPU = 3 MHz,

48 MHz disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz.

IDD3 Supply Current – 5 9 mA Conditions are Vdd = 3.3V, CPU = 3 MHz, 48 MHz disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz.

IDDP Supply Current when IMO = 6 MHz using SLIMO Mode.

– 2 3 mA Conditions are Vdd = 3.3V, CPU = 3 MHz, 48 MHz disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz.

ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and Internal Low Speed Oscil-lator Active.

– 4 25 μA Conditions are with internal low speed oscillator, Vdd = 3.3V, -40°C ≤ TA ≤ 85°C.

ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, Internal Low Speed Oscillator, and 32 kHz Crystal Oscillator Active.

– 4 27 μA Conditions °C are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 3.3V, -40°C ≤ TA ≤ 85°C.

VREF Reference Voltage (Bandgap) 1.28 1.3 1.32 V Trimmed for appropriate Vdd.

Table 9. DC GPIO SpecificationsSymbol Description Min Typ Max Units NotesRPU Pull Up Resistor 4 5.6 8 kΩRPD Pull Down Resistor 4 5.6 8 kΩVOH High Output Level Vdd - 1.0 – – V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total

loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget.

VOL Low Output Level – – 0.75 V IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget.

VIL Input Low Level – – 0.8 V Vdd = 3.0 to 5.25.VIH Input High Level 2.1 – V Vdd = 3.0 to 5.25.VH Input Hysterisis – 60 – mVIIL Input Leakage (Absolute Value) – 1 – nA Gross tested to 1 μA.CIN Capacitive Load on Pins as Input – 3.5 10 pF Package and pin dependent.

Temp = 25°C.COUT Capacitive Load on Pins as Output – 3.5 10 pF Package and pin dependent.

Temp = 25°C.

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DC Operational Amplifier SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.The Operational Amplifier is a component of both the Analog Continuous Time (CT) PSoC blocks and the Analog Switched Capacitor(SC) PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parametersapply to 5V at 25°C and are for design guidance only.

Table 10. 5V DC Operational Amplifier SpecificationsSymbol Description Min Typ Max Units Notes

VOSOA Input Offset Voltage (Absolute Value) Power = Low, Opamp Bias = HighPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

–––

1.6 1.31.2

10 8

7.5

mV mVmV

TCVOSOA Average Input Offset Voltage Drift – 7.0 35.0 μV/°CIEBOA Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent.

Temp = 25°C. VCMOA Common Mode Voltage Range.

All cases, except highest.Power = High, Opamp Bias = High

0.00.5

––

VddVdd - 0.5

VV

CMRROA Common Mode Rejection Ratio 60 – – dBGOLOA Open Loop Gain 80 – – dBVOHIGHOA High Output Voltage Swing (Internal Signals) Vdd - 0.01 – – VVOLOWOA Low Output Voltage Swing (Internal Signals) – – 0.01 VISOA Supply Current (including associated AGND

buffer)Power = Low, Opamp Bias = LowPower = Low, Opamp Bias = HighPower = Medium, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = LowPower = High, Opamp Bias = High

––––––

150300600

120024004600

200400800

160032006400

μAμAμAμAμAμA

PSRROA Supply Voltage Rejection Ratio 67 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN ≤ Vdd.

Table 11. 3.3V DC Operational Amplifier Specifications

Symbol Description Min Typ Max Units NotesVOSOA Input Offset Voltage (Absolute Value)

Power = Low, Opamp Bias = HighPower = Medium, Opamp Bias = HighHigh Power is 5 Volts Only

––

1.65 1.32

10 8

mV mV

TCVOSOA Average Input Offset Voltage Drift – 7.0 35.0 μV/°CIEBOA Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA.CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent.

Temp = 25°C.VCMOA Common Mode Voltage Range 0 – Vdd VCMRROA Common Mode Rejection Ratio 60 – – dBGOLOA Open Loop Gain 80 – – dBVOHIGHOA High Output Voltage Swing (Internal Signals) Vdd - 0.01 – – VVOLOWOA Low Output Voltage Swing (Internal Signals) – – 0.01 V

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DC Low Power Comparator SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parametersapply to 5V at 25°C and are for design guidance only.

ISOA Supply Current (including associated AGND buffer)Power = Low, Opamp Bias = LowPower = Low, Opamp Bias = HighPower = Medium, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = LowPower = High, Opamp Bias = High

––––––

150300600

12002400

–

200400800

16003200

–

μAμAμAμAμA– Not Allowed

PSRROA Supply Voltage Rejection Ratio 54 80 – dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN ≤ Vdd

Table 11. 3.3V DC Operational Amplifier Specifications (continued)

Symbol Description Min Typ Max Units Notes

Table 12. DC Low Power Comparator SpecificationsSymbol Description Min Typ Max Units Notes

VREFLPC Low power comparator (LPC) reference voltage range

0.2 – Vdd - 1 V

ISLPC LPC supply current – 10 40 μAVOSLPC LPC voltage offset – 2.5 30 mV

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DC Analog Output Buffer SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 13. 5V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units NotesVOSOB Input Offset Voltage (Absolute Value) – 3 12 mVTCVOSOB Average Input Offset Voltage Drift – +6 – μV/°CVCMOB Common-Mode Input Voltage Range 0.5 – Vdd - 1.0 VROUTOB Output Resistance

Power = LowPower = High

––

––

11

ΩΩ

VOHIGHOB High Output Voltage Swing (Load = 32Ω to Vdd/2)Power = LowPower = High

0.5 x Vdd + 1.30.5 x Vdd + 1.3

––

––

VV

VOLOWOB Low Output Voltage Swing (Load = 32Ω to Vdd/2)Power = LowPower = High

––

––

0.5 x Vdd - 1.30.5 x Vdd - 1.3

VV

ISOB Supply Current Including Bias Cell (No Load)Power = LowPower = High

––

1.12.6

25

mAmA

PSRROB Supply Voltage Rejection Ratio 40 64 – dB

Table 14. 3.3V DC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units NotesVOSOB Input Offset Voltage (Absolute Value) – 3 12 mVTCVOSOB Average Input Offset Voltage Drift – +6 – μV/°CVCMOB Common-Mode Input Voltage Range 0.5 - Vdd - 1.0 VROUTOB Output Resistance

Power = LowPower = High

––

––

1010

ΩΩ

VOHIGHOB High Output Voltage Swing (Load = 1 kΩ to Vdd/2)Power = LowPower = High

0.5 x Vdd + 1.00.5 x Vdd + 1.0

––

––

VV

VOLOWOB Low Output Voltage Swing (Load = 1 kΩ to Vdd/2)Power = LowPower = High

––

––

0.5 x Vdd - 1.00.5 x Vdd - 1.0

VV

ISOB Supply Current Including Bias Cell (No Load)Power = LowPower = High

––

0.82.0

15

mAmA

PSRROB Supply Voltage Rejection Ratio 60 64 – dB

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DC Analog Reference SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer tothe power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Controlregister. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block.Reference control power is high.Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some couplingof the digital signal may appear on the AGND.

Table 15. 5V DC Analog Reference Specifications

Symbol Description Min Typ Max UnitsVBG5 Bandgap Voltage Reference 5V 1.28 1.30 1.32 V– AGND = Vdd/2[6] Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V– AGND = 2 x BandGap[6] 2.52 2.60 2.72 V– AGND = P2[4] (P2[4] = Vdd/2)[6] P2[4] - 0.013 P2[4] P2[4] + 0.013 V– AGND = BandGap[6] 1.27 1.3 1.34 V– AGND = 1.6 x BandGap[6] 2.03 2.08 2.13 V– AGND Block to Block Variation (AGND =

Vdd/2)[6]-0.034 0.000 0.034 V

– RefHi = Vdd/2 + BandGap[7] Vdd/2 + 1.21 Vdd/2 + 1.3 Vdd/2 + 1.382 V– RefHi = 3 x BandGap[7] 3.75 3.9 4.05 V– RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V)[7] P2[6] + 2.478 P2[6] + 2.6 P2[6] + 2.722 V– RefHi = P2[4] + BandGap (P2[4] = Vdd/2)[7] P2[4] + 1.218 P2[4] + 1.3 P2[4] + 1.382 V– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] =

1.3V)[7]P2[4] + P2[6] - 0.058 P2[4] + P2[6] P2[4] + P2[6] + 0.058 V

– RefHi = 2 x BandGap[7] 2.50 2.60 2.70 V– RefHi = 3.2 x BandGap[7] 4.02 4.16 4.29 V– RefLo = Vdd/2 - BandGap[7] Vdd/2 - 1.369 Vdd/2 - 1.30 Vdd/2 - 1.231 V– RefLo = BandGap[7] BG - 0.082 BG + 0.023 BG + 0.129 V– RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V)[7] 2 x BG - P2[6] - 0.084 2 x BG - P2[6] + 0.025 2 x BG - P2[6] + 0.134 V– RefLo = P2[4] - BandGap (P2[4] = Vdd/2)[7] P2[4] - BG - 0.056 P2[4] - BG + 0.026 P2[4] - BG + 0.107 V– RefLo = P2[4] - P2[6] (P2[4] = Vdd/2, P2[6] =

1.3V)[7]P2[4] - P2[6] - 0.057 P2[4] - P2[6] + 0.026 P2[4] - P2[6] + 0.110 V

Table 16. 3.3V DC Analog Reference Specifications

Symbol Description Min Typ Max UnitsVBG33 Bandgap Voltage Reference 3.3V 1.28 1.30 1.32 V– AGND = Vdd/2[6] Vdd/2 - 0.02 Vdd/2 Vdd/2 + 0.02 V– AGND = 2 x BandGap[6] Not Allowed– AGND = P2[4] (P2[4] = Vdd/2)[6] P2[4] - 0.009 P2[4] P2[4] + 0.009 V– AGND = BandGap[6] 1.27 1.30 1.34 V– AGND = 1.6 x BandGap[6] 2.03 2.08 2.13 V– AGND Block to Block Variation (AGND =

Vdd/2)[6]-0.034 0.000 0.034 mV

– RefHi = Vdd/2 + BandGap[7] Not Allowed– RefHi = 3 x BandGap[7] Not Allowed– RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V)[7] Not Allowed

Notes6. This specification is only valid when CT Block Power = High. AGND tolerance includes the offsets of the local buffer in the PSoC block.7. This specification is only valid when Ref Control Power = High.

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DC Analog PSoC Block SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

DC POR and LVD SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

– RefHi = P2[4] + BandGap (P2[4] = Vdd/2)[7] Not Allowed– RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] =

0.5V)[7]P2[4] + P2[6] - 0.042 P2[4] + P2[6] P2[4] + P2[6] + 0.042 V

– RefHi = 2 x BandGap[7] 2.50 2.60 2.70 V– RefHi = 3.2 x BandGap[7] Not Allowed– RefLo = Vdd/2 - BandGap[7] Not Allowed– RefLo = BandGap[7] Not Allowed– RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V)[7] Not Allowed– RefLo = P2[4] - BandGap (P2[4] = Vdd/2)[7] Not Allowed– RefLo = P2[4] - P2[6] (P2[4] = Vdd/2, P2[6] =

0.5V)[7]P2[4] - P2[6] - 0.036 P2[4] - P2[6] P2[4] - P2[6] + 0.036 V

Table 16. 3.3V DC Analog Reference Specifications(continued)

Symbol Description Min Typ Max Units

Table 17. DC Analog PSoC Block Specifications

Symbol Description Min Typ Max Units NotesRCT Resistor Unit Value (Continuous Time) – 12.2 – kΩCSC Capacitor Unit Value (Switch Cap) – 80 – fF

Table 18. DC POR and LVD Specifications

Symbol Description Min Typ Max Units Notes

VPPOR0VPPOR1VPPOR2

Vdd Value for PPOR Trip (negative ramp)PORLEV[1:0] = 00bPORLEV[1:0] = 01bPORLEV[1:0] = 10b

–––

2.824.394.55

–––

VVV

VPH0VPH1VPH2

PPOR HysteresisPORLEV[1:0] = 00bPORLEV[1:0] = 01bPORLEV[1:0] = 10b

–––

9200

–––

mVmVmV

VLVD0VLVD1VLVD2VLVD3VLVD4VLVD5VLVD6VLVD7

Vdd Value for LVD TripVM[2:0] = 000bVM[2:0] = 001bVM[2:0] = 010bVM[2:0] = 011bVM[2:0] = 100bVM[2:0] = 101bVM[2:0] = 110bVM[2:0] = 111b

2.862.963.073.924.394.554.634.72

2.923.023.134.004.484.644.734.81

2.98[8]

3.083.204.084.57

4.74[9]

4.824.91

V

VVVVVVV

Notes8. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply.9. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.

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DC Programming SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 19. DC Programming Specifications

Symbol Description Min Typ Max Units NotesIDDP Supply Current During Programming or Verify – 10 30 mAVILP Input Low Voltage During Programming or

Verify– – 0.8 V

VIHP Input High Voltage During Programming or Verify

2.1 – – V

IILP Input Current when Applying VILP to P1[0] or P1[1] During Programming or Verify

– – 0.2 mA Driving internal pull down resistor.

IIHP Input Current when Applying VIHP to P1[0] or P1[1] During Programming or Verify

– – 1.5 mA Driving internal pull down resistor.

VOLV Output Low Voltage During Programming or Verify

– – 0.75 V

VOHV Output High Voltage During Programming or Verify

Vdd - 1.0 – Vdd V

FlashENPB Flash Endurance (per block)[10] 1,000 – – – Erase/write cycles per block.

FlashENT Flash Endurance (total)[11] 512,000 – – – Erase/write cycles.FlashDR Flash Data Retention 15 – – Years

Notes10. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.

Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.11. A maximum of 512 x 100 block endurance cycles is allowed.

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AC Electrical Characteristics

AC Chip-Level SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 20. AC Chip-Level Specifications

Symbol Description Min Typ Max Units NotesFIMO24 Internal Main Oscillator Frequency for 24

MHz22.8[12] 24 25.2[12] MHz Trimmed for 5V or 3.3V operation

using factory trim values. See Figure 4 on page 12. SLIMO Mode = 0.

FIMO6 Internal Main Oscillator Frequency for 6 MHz

5.5[12] 6 6.5[12] MHz Trimmed for 5V or 3.3V operation using factory trim values. See Figure 4 on page 12. SLIMO Mode = 1.

FCPU1 CPU Frequency (5V Nominal) 0.089[12] 24 25.2[12] MHz 4.75V ≤ Vdd ≤ 5.25VFCPU2 CPU Frequency (3.3V Nominal) 0.089[12] 12 12.6[12] MHz 3.0V ≤ Vdd ≤ 3.6VF48M Digital PSoC Block Frequency 0 48 50.4[12, 13] MHz Refer to the Table 25 on page 26.F24M Digital PSoC Block Frequency 0 24 25.2[12, 13] MHzF32K1 Internal Low Speed Oscillator Frequency 15 32 64 kHz Trimmed. During Power up ILO is

untrimmed and Minimum is 5KHz.F32K2 External Crystal Oscillator – 32.768 – kHz Accuracy is capacitor and crystal

dependent. 50% duty cycle.FPLL PLL Frequency – 23.986 – MHz A multiple (x732) of crystal frequency.Jitter24M2 24 MHz Period Jitter (PLL) – – 600 psTPLLSLEW PLL Lock Time 0.5 – 10 ms Refer to Figure 6 on page 22.TPLLSLEWLOW PLL Lock Time for Low Gain Setting 0.5 – 50 ms Refer to Figure 7 on page 22.TOS External Crystal Oscillator Startup to 1% – 250 500 ms Refer to Figure 8 on page 22.TOSACC External Crystal Oscillator Startup to 100

ppm– 300 600 ms The crystal oscillator frequency is

within 100 ppm of its final value by the end of the TOSACC period. Correct operation assumes a properly loaded 1 µW maximum drive level 32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.25V, -40°C ≤ TA ≤ 85°C.

Jitter32k 32 kHz Period Jitter – 100 – ns Refer to Figure 10 on page 22.TXRST External Reset Pulse Width 10 – – μsDC24M 24 MHz Duty Cycle 40 50 60 %Step24M 24 MHz Trim Step Size – 50 – kHzFout48M 48 MHz Output Frequency 45.6 [12] 48.0 50.4 [12] MHz Trimmed. Using factory trim values.Jitter24M1 24 MHz Period Jitter (IMO) – 600 – ps Refer to Figure 9 on page 22.FMAX Maximum frequency of signal on row

input or row output.– – 12.6[12] MHz

TRAMP Supply Ramp Time 20 – – μs

Notes12. Accuracy derived from Internal Main Oscillator (IMO) with appropriate trim for Vdd range.13. See the individual user module data sheets for information on maximum frequencies for user modules.

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Figure 6. PLL Lock Timing Diagram

Figure 7. PLL Lock for Low Gain Setting Timing Diagram

Figure 8. External Crystal Oscillator Startup Timing Diagram

Figure 9. 24 MHz Period Jitter (IMO) Timing Diagram

Figure 10. 32 kHz Period Jitter (ECO) Timing Diagram

24 MHz

FPLL

PLLEnable

TPLLSLEW

PLLGain 0

24 MHz

FPLL

PLLEnable

TPLLSLEWLOW

PLLGain 1

32 kHz

F32K2

32KSelect

TOS

Jitter24M1

F24M

Jitter32k

F32K2

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AC General Purpose I/O SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Figure 11. GPIO Timing Diagram

Table 21. AC GPIO SpecificationsSymbol Description Min Typ Max Units Notes

FGPIO GPIO Operating Frequency 0 – 12.6[12] MHz Normal Strong ModeTRiseF Rise Time, Normal Strong Mode, Cload = 50 pF 3 – 18 ns Vdd = 4.75 to 5.25V, 10% - 90%TFallF Fall Time, Normal Strong Mode, Cload = 50 pF 2 – 18 ns Vdd = 4.75 to 5.25V, 10% - 90%TRiseS Rise Time, Slow Strong Mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25V, 10% - 90%TFallS Fall Time, Slow Strong Mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25V, 10% - 90%

TFallFTFallS

TRiseFTRiseS

90%

10%

GPIOPin

OutputVoltage

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AC Operational Amplifier SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block.Power = High and Opamp Bias = High is not supported at 3.3V.

Table 22. 5V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units NotesTROA Rising Settling Time to 0.1% for a 1V Step (10 pF load,

Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

–––

–––

3.90.720.62

μsμsμs

TSOA Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

–––

–––

5.90.920.72

μsμsμs

SRROA Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

0.151.76.5

–––

–––

V/μsV/μsV/μs

SRFOA Falling Slew Rate (80% to 20%) of a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

0.010.54.0

–––

–––

V/μsV/μsV/μs

BWOA Gain Bandwidth Product Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = HighPower = High, Opamp Bias = High

0.753.15.4

–––

–––

MHzMHzMHz

ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

Table 23. 3.3V AC Operational Amplifier SpecificationsSymbol Description Min Typ Max Units NotesTROA Rising Settling Time to 0.1% of a 1V Step (10 pF load,

Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = High

––

––

3.920.72

μsμs

TSOA Falling Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = High

––

––

5.410.72

μsμs

SRROA Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = High

0.312.7

––

––

V/μsV/μs

SRFOA Falling Slew Rate (80% to 20%) of a 1V Step (10 pF load, Unity Gain)Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = High

0.241.8

––

––

V/μsV/μs

BWOA Gain Bandwidth Product Power = Low, Opamp Bias = LowPower = Medium, Opamp Bias = High

0.672.8

––

––

MHzMHz

ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) – 100 – nV/rt-Hz

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When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of upto 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 kΩ resistance and the external capacitor.

Figure 12. Typical AGND Noise with P2[4] Bypass

At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At highfrequencies, increased power level reduces the noise spectrum level.

Figure 13. Typical Opamp Noise

100

1000

10000

0.001 0.01 0.1 1 10 100Freq (kHz)

dBV/rtHz

00.010.11.010

10

100

1000

10000

0.001 0.01 0.1 1 10 100Freq (kHz)

nV/rtHz

PH_BHPH_BLPM_BLPL_BL

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AC Low Power Comparator SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for designguidance only.

AC Digital Block SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 24. AC Low Power Comparator SpecificationsSymbol Description Min Typ Max Units Notes

TRLPC LPC Response Time – – 50 μs ≥ 50 mV overdrive comparator reference set within VREFLPC.

Table 25. AC Digital Block Specifications

Function Description Min Typ Max Units NotesAll Functions

Maximum Block Clocking Frequency (Vdd > 4.75V) – – 50.4[12] MHz 4.75V ≤ Vdd ≤ 5.25V.Maximum Block Clocking Frequency (Vdd < 4.75V) – – 25.2[12] MHz 3.0V ≤ Vdd ≤ 4.75V.

Timer Capture Pulse Width 50[14] – – nsMaximum Frequency, No Capture – – 50.4[12] MHz 4.75V ≤ Vdd ≤ 5.25V.Maximum Frequency, With Capture – – 25.2[12] MHz

Counter Enable Pulse Width 50[14] – – nsMaximum Frequency, No Enable Input – – 50.4[12] MHz 4.75V ≤ Vdd ≤ 5.25V.Maximum Frequency, Enable Input – – 25.2[12] MHz

Dead Band

Kill Pulse Width:Asynchronous Restart Mode 20 – – nsSynchronous Restart Mode 50[14] – – nsDisable Mode 50[14] – – ns

Maximum Frequency – – 50.4[12] MHz 4.75V ≤ Vdd ≤ 5.25V.CRCPRS(PRS Mode)

Maximum Input Clock Frequency – – 50.4[12] MHz 4.75V ≤ Vdd ≤ 5.25V.

CRCPRS(CRC Mode)

Maximum Input Clock Frequency – – 25.2[12] MHz

SPIM Maximum Input Clock Frequency – – 8.4[12] MHz Maximum data rate is 4.2 Mbps due to 2 x over clocking.

SPIS Maximum Input Clock Frequency – – 4.2[12] MHzWidth of SS_ Negated Between Transmissions 50[14] – – ns

Trans-mitter

Maximum Input Clock Frequency – – 25.2[12] MHz Maximum baud rate is 3.15 Mbaud due to 8 x over clocking.

Maximum Input Clock Frequency with Vdd ≥ 4.75V, 2 Stop Bits

– – 50.4[12] MHz Maximum baud rate is 6.30 Mbaud due to 8 x over clocking

Receiver Maximum Input Clock Frequency – – 25.2[12] MHz Maximum baud rate is 3.15 Mbaud due to 8 x over clocking.

Maximum Input Clock Frequency with Vdd ≥ 4.75V, 2 Stop Bits

– – 50.4[12] MHz Maximum baud rate is 6.30 Mbaud due to 8 x over clocking.

Note14. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).

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AC Analog Output Buffer SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 26. 5V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units NotesTROB Rising Settling Time to 0.1%, 1V Step, 100 pF Load

Power = Low Power = High

––

––

44

μsμs

TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

––

––

3.43.4

μsμs

SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High

0.50.5

––

––

V/μsV/μs

SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High

0.550.55

––

––

V/μsV/μs

BWOB Small Signal Bandwidth, 20 mVpp, 3 dB BW, 100 pF Load Power = Low Power = High

0.80.8

––

––

MHzMHz

BWOB Large Signal Bandwidth, 1Vpp, 3 dB BW, 100 pF Load Power = Low Power = High

300300

––

––

kHzkHz

Table 27. 3.3V AC Analog Output Buffer Specifications

Symbol Description Min Typ Max Units NotesTROB Rising Settling Time to 0.1%, 1V Step, 100 pF Load

Power = Low Power = High

––

––

4.74.7

μsμs

TSOB Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High

––

––

44

μsμs

SRROB Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High

0.360.36

––

––

V/μsV/μs

SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High

0.40.4

––

––

V/μsV/μs

BWOB Small Signal Bandwidth, 20 mVpp, 3 dB BW, 100 pF Load Power = Low Power = High

0.70.7

––

––

MHzMHz

BWOB Large Signal Bandwidth, 1Vpp, 3 dB BW, 100 pF Load Power = Low Power = High

200200

––

––

kHzkHz

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AC External Clock SpecificationsThe following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

AC Programming SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Table 28. 5V AC External Clock Specifications

Symbol Description Min Typ Max Units NotesFOSCEXT Frequency 0.093 – 24.6 MHz– High Period 20.6 – 5300 ns– Low Period 20.6 – – ns– Power Up IMO to Switch 150 – – μs

Table 29. 3.3V AC External Clock Specifications

Symbol Description Min Typ Max Units NotesFOSCEXT Frequency with CPU Clock divide by 1 0.093 – 12.3 MHz Maximum CPU frequency is 12

MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle require-ments.

FOSCEXT Frequency with CPU Clock divide by 2 or greater

0.093 – 24.6 MHz If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met.

– High Period with CPU Clock divide by 1 41.7 – 5300 ns– Low Period with CPU Clock divide by 1 41.7 – – ns– Power Up IMO to Switch 150 – – μs

Table 30. AC Programming Specifications

Symbol Description Min Typ Max Units NotesTRSCLK Rise Time of SCLK 1 – 20 nsTFSCLK Fall Time of SCLK 1 – 20 nsTSSCLK Data Setup Time to Falling Edge of SCLK 40 – – nsTHSCLK Data Hold Time from Falling Edge of SCLK 40 – – nsFSCLK Frequency of SCLK 0 – 8 MHzTERASEB Flash Erase Time (Block) – 10 – msTWRITE Flash Block Write Time – 40 – msTDSCLK Data Out Delay from Falling Edge of SCLK – – 45 ns Vdd > 3.6TDSCLK3 Data Out Delay from Falling Edge of SCLK – – 50 ns 3.0 ≤ Vdd ≤ 3.6

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AC I2C SpecificationsThe following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25Vand -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C andare for design guidance only.

Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus

Table 31. AC Characteristics of the I2C SDA and SCL Pins

Symbol DescriptionStandard Mode Fast Mode

Units NotesMin Max Min Max

FSCLI2C SCL Clock Frequency 0 100[15] 0 400[15] kHzTHDSTAI2C Hold Time (repeated) START Condition. After

this period, the first clock pulse is generated.4.0 – 0.6 – μs

TLOWI2C LOW Period of the SCL Clock 4.7 – 1.3 – μsTHIGHI2C HIGH Period of the SCL Clock 4.0 – 0.6 – μsTSUSTAI2C Setup Time for a Repeated START Condition 4.7 – 0.6 – μsTHDDATI2C Data Hold Time 0 – 0 – μsTSUDATI2C Data Setup Time 250 – 100[16] – nsTSUSTOI2C Setup Time for STOP Condition 4.0 – 0.6 – μsTBUFI2C Bus Free Time Between a STOP and START

Condition4.7 – 1.3 – μs

TSPI2C Pulse Width of spikes are suppressed by the input filter.

– – 0 50 ns

Notes15. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the

FSCLI2C specification adjusts accordingly.16. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement TSUDATI2C ≥ 250 ns must then be met. This will automatically be

the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + TSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

SDA

SCL

S Sr SP

TBUFI2C

TSPI2CTHDSTAI2C

TSUSTOI2CTSUSTAI2C

TLOWI2C

THIGHI2CTHDDATI2CTHDSTAI2C

TSUDATI2C

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Packaging InformationThis section illustrates the packaging specifications for the automotive CY8C29x66 PSoC device, along with the thermal impedancesand solder reflow for each package and the typical package capacitance on crystal pins.Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description ofthe emulation tools’ dimensions, refer to the drawings at http://www.cypress.com/design/MR10161.

Figure 15. 28-Pin (210-Mil) SSOP

Thermal Impedances Capacitance on Crystal Pins

Solder Reflow Peak TemperatureFollowing is the minimum solder reflow peak temperature to achieve good solderability.

51-85079 *C

Table 32. Thermal Impedances per PackagePackage Typical θJA

[17]

28 SSOP 94°C/W

Table 33. Typical Package Capacitance on Crystal PinsPackage Package Capacitance28 SSOP 2.8 pF

Table 34. Solder Reflow Peak Temperature

Package Minimum Peak Temperature[18] Maximum Peak Temperature

28 SSOP 240°C 260°C

Notes17. TJ = TA + POWER x θJA 18. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu

paste. Refer to the solder manufacturer specifications.

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Development Tool SelectionThis section presents the development tools available for the CY8C29x66 family.

Software

PSoC DesignerAt the core of the PSoC development software suite is PSoCDesigner. Utilized by thousands of PSoC developers, this robustsoftware has been facilitating PSoC designs for years. PSoCDesigner is available free of charge at http://www.cypress.com.PSoC Designer comes with a free C compiler.

PSoC ProgrammerFlexible enough to be used on the bench in development, yetsuitable for factory programming, PSoC Programmer workseither as a standalone programming application or it can operatedirectly from PSoC Designer. PSoC Programmer software iscompatible with both PSoC ICE-Cube In-Circuit Emulator andPSoC MiniProg. PSoC programmer is available free of charge athttp://www.cypress.com/psocprogrammer.

Development KitsAll development kits can be purchased from the Cypress OnlineStore. The online store (www.cypress.com/shop) also has themost up to date information on kit contents, descriptions, andavailability.

CY3215-DK Basic Development KitThe CY3215-DK is for prototyping and development with PSoCDesigner. This kit supports in-circuit emulation and the softwareinterface allows users to run, halt, and single step the processorand view the contents of specific memory locations. Advancedemulation features are also supported through PSoC Designer.The kit includes:

■ ICE-Cube Unit

■ 28-Pin PDIP Emulation Pod for CY8C29466-24PXI

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Samples (two)

■ PSoC Designer Software CD

■ ISSP Cable

■ MiniEval Socket Programming and Evaluation board

■ Backward Compatibility Cable (for connecting to legacy Pods)

■ Universal 110/220 Power Supply (12V)

■ European Plug Adapter

■ USB 2.0 Cable

■ Getting Started Guide

■ Development Kit Registration form

Evaluation ToolsAll evaluation tools can be purchased from the Cypress OnlineStore. The online store (www.cypress.com/shop) also has themost up to date information on kit contents, descriptions, andavailability.

CY3210-PSoCEval1The CY3210-PSoCEval1 kit features an evaluation board andthe MiniProg1 programming unit. The evaluation board includesan LCD module, potentiometer, LEDs, an RS-232 port, andplenty of breadboarding space to meet all of your evaluationneeds. The kit includes:

■ Evaluation Board with LCD Module

■ MiniProg Programming Unit

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)



■ USB 2.0 Cable

CY3210-29X66 Evaluation Pod (EvalPod)PSoC EvalPods are pods that connect to the ICE In-CircuitEmulator (CY3215-DK kit) to allow debugging capability. Theycan also function as a standalone device without debuggingcapability. The EvalPod has a 28-pin DIP footprint on the bottomfor easy connection to development kits or other hardware. Thetop of the EvalPod has prototyping headers for easy connectionto the device's pins. CY3210-29X66 provides evaluation of theCY8C29x66 PSoC device family.

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CY8C29466


Device ProgrammersAll device programmers can be purchased from the CypressOnline Store.

CY3210-MiniProg1The CY3210-MiniProg1 kit allows a user to program PSoCdevices via the MiniProg1 programming unit. The MiniProg is asmall, compact prototyping programmer that connects to the PCvia a provided USB 2.0 cable. The kit includes:

■ MiniProg Programming Unit

■ MiniEval Socket Programming and Evaluation Board

■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample



■ USB 2.0 Cable

CY3207ISSP In-System Serial Programmer (ISSP)The CY3207ISSP is a production programmer. It includesprotection circuitry and an industrial case that is more robust thanthe MiniProg in a production-programming environment. Note: CY3207ISSP needs special software and is notcompatible with PSoC Programmer. This software is free andcan be downloaded from http://www.cypress.com. The kitincludes:

■ CY3207 Programmer Unit

■ PSoC ISSP Software CD

■ 110 ~ 240V Power Supply, Euro-Plug Adapter

■ USB 2.0 Cable

Accessories (Emulation and Programming)

Third Party ToolsSeveral tools have been specially designed by the following3rd-party vendors to accompany PSoC devices during devel-opment and production. Specific details for each of these toolscan be found at http://www.cypress.com under DesignResources > Evaluation Boards.

Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volumeproduction using an on-chip debug (OCD) non-production PSoCdevice, see Application Note “Debugging - Build a PSoCEmulator into Your Board - AN2323” at http://www.cypress.com.

Table 35. Emulation and Programming AccessoriesPart Number Pin Package Pod Kit[19] Foot Kit[20] Adapter[21]

CY8C29466-24PVXA 28 SSOP CY3250-29X66 CY3250-28SSOP-FK AS-28-28-02SS-6ENP-GANG

Notes19. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.20. Foot kit includes surface mount feet that can be soldered to the target PCB.21. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at

http://www.emulation.com.

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CY8C29466


Ordering InformationThe following table lists the automotive CY8C29x66 PSoC devices’ key package features and ordering codes.

Ordering Code Definitions

Table 36. CY8C29x66 Automotive PSoC Device Key Features and Ordering Information

Pack

age

Ord

erin

gC

ode

Flas

h(B

ytes

)

RA

M(B

ytes

)

Tem

pera

ture

Ran

ge

Dig

ital P

SoC

Blo

cks

Ana

log

PSoC

Blo

cks

Dig

ital I

/OPi

ns

Ana

log

Inpu

ts

Ana

log

Out

puts

XRES

Pin

28 Pin (210 Mil) SSOP CY8C29466-24PVXA 32K 2K -40°C to +85°C 16 12 24 12[1] 4 Yes28 Pin (210 Mil) SSOP (Tape and Reel)

CY8C29466-24PVXAT 32K 2K -40°C to +85°C 16 12 24 12[1] 4 Yes

CY 8 C 29 xxx-SPxxPackage Type: Thermal Rating:

PX = PDIP Pb-Free A = Automotive -40°C to +85°CSX = SOIC Pb-Free C = CommercialPVX = SSOP Pb-Free E = Automotive Extended -40°C to +125°CLFX/LKX = QFN Pb-Free I = IndustrialAX = TQFP Pb-Free

CPU Speed: 24 MHzPart NumberFamily CodeTechnology Code: C = CMOSMarketing Code: 8 = PSoCCompany ID: CY = Cypress

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Document Number: 001-12899 Rev. *B Revised September 25, 2009 of 34

PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corp. Purchase of I2C components from Cypress or one of its sublicensed Associated Companiesconveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All otherproducts and company names mentioned in this document may be the trademarks of their respective holders.

CY8C29466

© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use ofany circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used formedical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use ascritical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systemsapplication implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypressintegrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited withoutthe express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIESOF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does notassume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems wherea malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturerassumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document History Page

Sales, Solutions, and Legal Information Worldwide Sales and Design SupportCypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the officeclosest to you, visit us at www.cypress.com/sales.

ProductsPSoC psoc.cypress.com

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Document Title: CY8C29466 Automotive PSoC® Programmable System-on-ChipDocument Number: 001-12899

Rev. ECN No. Orig. of Change

Submission Date

Description of Change

** 772096 HMT See ECN New silicon, new document (Revision **).*A 2697720 VIVG/PYRS 04/24/09 Updated template

Content edits*B 2769233 BTK 09/25/09 Updated Features section. Updated text of PSoC Functional Overview section.

Updated Getting Started section. Made corrections and minor text edits to Pinouts section. Changed the name of some sections for added clarity. Improved formatting of the register tables. Added clarifying comments to some electrical specifications. Changed TRAMP specification per MASJ input. Fixed all AC specifications to conform to a ±5% IMO accuracy. Made other miscella-neous minor text edits. Deleted some non-applicable or redundant information. Added a footnote to clarify that 8 of the 12 analog inputs are regular and the other 4 are direct SC block connections. Updated the Development Tool Selection section. Improved the bookmark structure. Edited FIMO6, TERASEB, TWRITE, TRSCLK, TFSCLK, VIHP, VPPORxR, and 5V RefLo specifications according to MASJ input. Removed ‘TM’ from Programmable System-on-Chip in the title.

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