Customer Presentation Jan 2006 v2

8/3/2019 Customer Presentation Jan 2006 v2

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2006 Confidential 1

The NewChoiceinMainframe Computing


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2006 Confidential 2

PSI History

1995 1997 1999 2003 2005

Intel and

Amdahl beginwork on IA64Mainframe

Amdahl &Hitachi misschipcycle

PSI spun-off

from Fujitsuwith Amdahls

IntellectualProperty

Intel ships Itanium 2 and HPships mainframe capableserver at a fraction of thecost of IBM hardware

Backed by leading investorsBlueprint, Goldman, IntelCapital, InterWest, InvestCorp

Amdahl engineering and IBMmanagement team in place

PSI demonstrates highperforming z/OS onItanium 2 architecture

Beta customer

placements

Initial ESP

shipments

Support

Infrastructure

Established

Direct and

channel sales

force

ISV

relationshipsHP and PSI sign businessdevelopment agreement

Today

2004 2006


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2006 Confidential 3

PSI - Investors
http://www.intel.com/index.htm?iid=HPAGE+header_intellogo&


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2006 Confidential 4

Sun Microsystems Director Worldwide Engineering DivisionsSurf Software Founder & PresidentZilog Engineering Development

John LeeVP EngineeringDevelopment

Intertrust Technologies VP Engineering Operations

Amdahl Corporation - Multiple Director-Level Engineering positions

Amdahl Tenure 23 Years

BobMontreuilVP EngineeringOperations

Siebel - VP & GM of Global Financial ServicesFleet Boston Financial EVP of Market StrategyBank of America Managing Director and EVP Marketing, InstitutionalIBM Finance Industry Sales and Marketing Executive

Linda ZiderEVP Sales andMarketing

CFO, BITFONE CorpLotus Development Corporation, cc:MAILCPA: Ernst & Young / Price Waterhouse

LisaDAlenconCFO

Director, Rackable Systems NASDAQ:RACK

CEO, Resilience (high availability servers)

CEO, Release Now (digital rights mgmt.)

IBM Executive, 20+ Years at IBM

MichaelMaulickPresident &CEO

Seasoned Management TeamExperience and Motivation


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2006 Confidential 5

Founder & CEO of System Fabric WorksVP of Micro Components, Burroughs CorporationIBM Executive 32 years

Carl CaricariTechnical

Advisor

Amdahl Corporation Senior VP Sales, Marketing, Software StrategyAmdahl Executive 20+ YearsIBM Executive 20+ Years at IBM

BillOConnellStrategicAdvisor, Sales

GregoryHandschuhCorporate Counsel

Amdahl Corporation Multiple Lead Technical Management PositionsInstrumental in 5995M Product Family DevelopmentAmdahl Tenure 19 Years

Ron HiltonFounder and

CTO

Seasoned Management TeamExperience and Motivation

Vice President, General Counsel Amdahl Corporation

Federal Trade Commission's Bureau of Competition in Washington, D.C.

GaryWoffindenChief Architect

Chief Engineer for the Amdahl Millennium DesignInventor of 14 PatentsAmdahl Corporation - 27 Years Computer Design


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2006 Confidential 6

PSI Vision

Platform Solutions, Inc., is thefirst developer of a newgeneration ofcompatiblemainframe computers

designed for todays enterprisedatacenter.

Our vision is to bring true choiceto mainframecomputing, providing customers a new level ofcontrol over their IT investments and ultimateflexibilityin aligning their computing resourceswith their changing business priorities andtechnologies.


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2006 Confidential 7

Current Business Status

Business Completed Series B Funding September 2004

Current Headcount 90+

Product Betas shipped in Dec & March 2005

1Q 06 ESP

Partners

HP: Intellectual Property agreement in place 2003 Avnet: distributor agreement signed April 2005

Intel: Technology and Investor

T3T: IBM Premier solution provider

Customers LL Bean publicly shared Beta satisfaction in April 2005

T3T showcased a demo in United Kingdom May 2005 Bank in Italy December 2005

Lufthansa Airlines POC shipped January 2006


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2006 Confidential 8

Technical Strategy

PSI develops and delivers compatible microcodeHP provides systems platform and support

Intel provides competitive chip technology


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2006 Confidential 9

Innovative Technology

Technology which supportsz/OS, Windows, Linux, andUnix on a single server

Partitioning flexibility to exploitproprietary and Open Systemsplatforms

Unique virtualization to bridge

the mainframe to opensystems environments


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2006 Confidential 10

Investment Protection

Architecture isadaptive to change

Upgrade path to

exploit newtechnology

Designed for longuseful life


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Reduced TCO

Non-proprietary silicon

Savings on hardware,maintenance, and

environmentals

Sub-capacity softwarelicensing


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Competitive Industry Benefits

Competition is a catalyst for innovation

Competition lowers TCO

Competitive leverage for all z/OS users

A dual-vendor strategy is simply good

business


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Trusted Partner

Easy to do business with

Focused on a long term

relationship Adopt the Amdahl adage,

A customer problem is

an Amdahl problem


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Competing in a Proprietary Market

Use a proven hardwareplatform

Use proven IP

Use proven talent

Use a commerciallyavailable technology

Deliver compatibility andinnovation


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What is Compatibility?

Its not the chip Its not underlying hardware

It is the execution of the 1200+ instructions fromthe z/OS and S/390 instruction set

Operating Systemand Applicationindependence fromthe HW platform


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PSI Product Overview


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Why Itanium 2

64-bit Architecture Easier to map z/Architecture address spaces

Room for virtualization data structures

Best in Class Register Implementation 128 General Purpose, 128 Floating Point, 128 Control,

64 Predicate, 8 Branch, 128 Application

Explicit Parallelism (EPIC)

2 - three word bundles executed per cycle Instruction and Thread Level Parallelism (ILP & TLP)

Good Fit Overall for z/Architecture Native big-endian support Inter-CPU communication a la SIGP Native 4K memory pages

Mainframe Class Machine Check Architecture (MCA)supported

Large On-Board Cache 9MB Single Core 24 MB Dual Core


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Advanced RAS Features

Application Layer

Operating SystemOS logs errors and initiates recovery

FirmwareWell-defined flow for reportingand logging errors to the OS

CPU and ChipsetData Integrity: Extensive ECCcoverage and parity protection

Firmware and OS interactto correct and recover from

complex platform errors

3

2

1

Itanium 2Processor RAS

Machine Check Architecture


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Itanium Market Growth


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PSI Technology

Overview


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Mainframe Technology Comparison

I/O I/O

I/OI/O

Itanium 2 Enterprise Class Server IBM zSeries Server

ccNUMA Up to eight CPUs per cell Cell-local memory Non-blocking switch remote memory access

ccNUMA

Up to sixteen CPUs per book

Book-local memory

Ring-hop remote memory access


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Multi-OS System Building Blocks

MemoryChipset

cellcontrollerCrossbar

interconnectswitch

Mem

ory

I/O card cage12 PCI-X slots

1.6 GHz Intel Itanium2processors

Chipset

cellcontroller

Cell 1

To cell 2

To cell 3To cell 4 To cell 5

To cell 6

To cell 7

Cell 8

Tocell 9

To cell 10

To cell 11

To cell 12To cell 13To cell 14

To cell 15

To cell 16

Cell 1 Cell 8

I/O I/O

1.6 GHz Intel Itanium 2processors

With Max 16 Cells systems

scale to 64 then 128 CPUs (dual core 2006)

I/O card cage12 PCI-X slots


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PSI z/Architecture on

Itanium 2 ProcessorTechnology


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PSI Processor Technology

Dynamic Translatedcode

Static commonruntimes

PSI technology loads at EFI load time and is notdependent on any other operating system software


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Multi-OS Architecture


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PSI System Block Diagram

P0P1P2

. . .

SHARED MEM

z/Architecture I/O IMPLEMENTATION

SHARED MEM DRIVER

I/O Kernel

z/Architecture CPU T-CODE

JIT BINARY TRANSLATOR

MICROKERNEL

z/Architecture MAINSTORE

z/Architecture I/O CONTROL BLOCKS

z/Architecture INTERRUPT QUEUE

INTER-PROCESSOR MESSAGE QUEUESPROCESSOR INTERRUPT BLOCK

P3P4

CONSOLE

Pn


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PSI Single Processor Performance

0.0

10.0

20.030.0

40.0

50.0

60.0

70.0

80.0

Merced McKinley Madison Madison 9M

MIPS

Estimated MIPS Measured MIPS


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MP Performance

Intel Itanium 2 EPIC architecture was explicitly

designed for MP scalability going far beyond thex86 architecture

Today, Itanium 2 systems are available with upto 64 processors -- going to 128 processors in2006

MP factors are in line with traditional mainframedesigns


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IBM I/O Architecture

SourceWashingtonSystems Center

MBA-3MBA-2

MBA-1

I/O Domain 2

STI-M

CHA

NS

Work

CHA

NS

CHA

NS

CHA

NS

SecondarySTIs

I/O Domain 1

STI-M

CHANS

Work

CHANS

CHANS

CHANS

SecondarySTIs

CPSSCH

SSID

OR5

HSA

UCW CCW@

SAP

Channel

SelectionWork

Request

CP CageMBA-0

STI

28 I/OSlots

per I/OCage

ESCONLink

ESCON OSA FICON PCI-X

I/O Cage

7 I/ODomains

I/O Domain 0

STI-M

CHANS

Work

CHANS

CHANS

CHANS

SecondarySTIs


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PSI I/O Architecture

PCI-X Slot

PCI-X BusController

C

HANS

Bus

PCI-X Slot

PCI-X BusController

CH

ANS

Bus

IA 64 CP SSCHSSIDOR5

HSA

UCW CCW@

IA64 SAP

ChannelSelection

WorkRequest

Cell 0

Cell Controller

HighSpeedCross-B

ar

4GB/S

Cell 1

Cell 2

Cell 3

I/O Controller

Ropes 12 I/OSlots

per I/OCage

ESCONLink

ESCON OSA FICON PCI-X

I/O Cage

PCI-X Slot

PCI-X HostBridge

CH

ANS

Bus


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PSI I/O Subsystem Face of the Future

Real Mainframe I/O

ESCON FICON

OSA

Virtual I/O Virtualized ECKD disk on Open Systems Storage

Fibre Channel and SCSI attached devices

Network attached Virtual 3270

Virtual CTC

Virtual Unit Record printer and card reader


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Virtualization to Bridge between Two Worlds

Ph

ysical

4.5 MB/SBus/Tag(Legacy)

17 MB/S

ESCON Devices

100 MB/S

Gigabit Ethernet

OSA

200 MB/S

FICONISC CouplingLinks

Open Systems Connectivity Mainframe Connectivity

100 MB/SGigabit Ethernet

160 MB/SUltra160 SCSI

320 MB/S

Ultra320 SCSI

200MB/S2 Gigabit EthernetFibre Channel

Ph

ysical

Ethernet

Disk & Tape

WindowTerminals 3270 Terminals

Printers

PSIs Virtualized I/O Devices

L i h b f b h I/O ld
http://www.columbia.edu/acis/history/3270-01.jpg


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Leveraging the best of both I/O worlds

Benefits Introduces a new tier

of mainframe storage

Extends ILM for themainframe

Brings the mainframeinto the opensystems world

PSI I/O S b t O i


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PSI I/O Subsystem Overview

OpenSystems

Devices

I/O Subsystem Environment

HSACachesDVBs

Channel 0

z/ArchCPU

z/ArchCPU

z/ArchCPU

PartitionController

RequestQueue

VirtualChannel

DeviceDrivers

Disk

InterruptQueues

Tape

Terminal

SubchannelControlBlocks

DeviceInfo.

BlocksCaches

Channel 1

VirtualChannel

Channel n

VirtualChannel

VirtualDevice

VirtualDevice

VirtualDevice

z/OSApplications

z

/OS

StartSubchann

el(SSCH)Instruction

ESCON Ch l I l i


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ESCON Channel Implementation

I/O Subsystem environment

z/Arch

CPU

z/ArchCPU

z/Arch

CPU

MSC

RequestQueue

ESCONChannel

PSI

Driver

InterruptQueues

Mainstore&

HSA

ESCON

HBA

Applications

z/OS

CCW &Data

Buffers

Sta

rtSubchannel(SSCH)Instru

ction

FICON Ch l I l t ti


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FICON Channel Implementation

I/O Subsystemz/ArchCPU

z/ArchCPU

z/ArchCPU

MSC

RequestQueue

FICONChannel

EmulexHBA

Driver

InterruptQueues

Mainstore

&HSA

FICONHBA

Applications

z/OS

FrameBuffers

StartS

ubchannel(SSCH)Instruction

OSA I l t ti


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OSA Implementation

I/O environment

z/Arch

CPU

z/ArchCPU

z/Arch

CPU

MSC

RequestQueue

OSAChannel

DeviceDrivers

InterruptQueues

Mainstore&

HSA

OSAControl

Unit

NIC

Applications

z/OS

FrameBuffers

S

tartSubchannel(SSCH)Instru

ction

EMIF S t


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PhysicalSystem

Partition BPartition A

EMIF Support

ControlUnit

Channel

CPU 0

Mainstore

Device 0 Device 1

CPU 1 CPU 0

Mainstore

CPU 1

ESCON

C li Li k d ETR


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Coupling Links and ETR

z/ArchCPU

z/ArchCPU

z/ArchCPU

Mainstore

&HSA

I/S Channel

PCI card

Applications

z/OS

StartSubchannel(SMSG)Instruction

I/O environment

MSCI/S

ChannelSupport

DeviceDrivers

I t S t Ch l PCI C d


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Inter-System Channel PCI Card

SerDes

FPGA

Fibre ChannelTransceiver

SerDes Fibre ChannelTransceiver

133MHzPCI-XBus

PCI-Xcore

ETRTransceiver

Coupling Link 0

Coupling Link 1

Sysplex Timer Link


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PSI Systems ManagementArchitecture

PSI Console Control


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PSI Console Control

Systems Management

Redundant servers running Linux IBM service element and HMC

equivalent

Systems management acrossheterogeneous systems

WEB Server implementation

Browser GUI

Systems Management Objectives


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Systems Management Objectives

Provide IBM systems management functionality

IBM service element and HMC equivalent Provide equivalent visibility (systems, partitions, I/O)

Provide equivalent control (move the machine through specificarchitecturally defined states: Activate, Deactivate, Reset Normal,Start, Stop)

Provide equivalent configurability (I/O, soft partitions, CPU) Provide equivalent error and event notification

Leverage HP systems management and servicefunctionality

Mainframe-class Reliability/Availability/Serviceability Web server implementation

Browser GUI

The IBM User Interface


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The IBM User Interface

(Work Area)

(Views Area)

(Task Area)

(Unintuitive Drag andDrop Interface)

The PSI Console User Interface


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The PSI Console User Interface

(Work Area)

(Views Area)

(Task Area)

Intuitive Point

and Click

Browser

Based

Interface

Console Architectural Logical Diagram


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PSI Console App

MVS

Browser

Console Architectural Logical Diagram

I/O KernelMVS

PSI FW

rx8620 or Superdome

PSI Console BoxConsole UI Web Server

Linux

CPU CPU CPU CPU

SNMPXML

Sharedmemory

Mainframe Operator isFamiliar with the Interface

SAL/PALSAL/PAL

SAP

Mainframe RAS Approach


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Mainframe RAS Approach

Machine Check Architecture Extensive parity checking

Dynamic CPU and Memory Sparing

ECC across all caches

Redundant primary power Hot swappable

Channel cards

Power and cooling

Remote support and call-home

Concurrent software maintenance

Redundant Management Consoles

Maintenance & Support


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Maintenance & Support

PSI provides z/OS problem determination

z/OS software support provided by IBM

Same support model as Amdahl

A customer problem is a PSI problem

1 year warranty

Annual maintenanceafter warranty

PSI call center takesfirst call

Warm hand-off to HPwhen required

Escalation when required


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Partition Management


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PSI Solution Benefits

PSI Server Solution Benefits


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PSI Server Solution Benefits

Virtual I/O Requirement: leverage open systems storage;migrate from ESCON to PSI virtual I/O on FCP

IBM to opensystems migrationmachineRequirement: Migration from IBM mainframesoftware applications to open systems ; provides

bridge between both

Delayedcapacity/growthmachineRequirement: Expanded capacity for

datacenters balancing mainframe and open

systems to meet peek demand

Research, DR &Development/TestRequirement: Lower cost MIPS for research

and development/test; disaster recovery

machine with day time open systemscapacity

Low end VSEoffering deliveredby T3TRequirement: Limited growth path; no plans to

migrate from VSE

Investment protection


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Investment protection

z/OS HP UXpenSystems

z/OS OpenSystems

AssetFlexibility

I/O Implementation - Comparison


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I/O Implementation - Comparison

IBM: z/890 z/990 PSI/ 5320

ESCON 420 - 1024 Max192 PCI slots

FICON 40 - 120 Max192 PCI slots

Virtual n/a 256 (MVS limit); 32K devices

Capability Limited to physical and FCP Open System Storage Leverage

ESCONFICON

EMCCLARiiON

Cx700

CU SANFCFC

ESCONor FICONDirector

Linux Implementation - Comparison


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Linux Implementation - Comparison

IBM PSI

Resource Usage Over 400 MIPs 100 or less MIPs

Transaction Speed 1 X 3 5 X (native Itanium)Cost +/- $125K +/- $25K

Design Point z/Architecture Multiple OS

Multi-OS deployments


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Multi OS deployments

Multi-OS single server

footprint Enterprise Server

Consolidation

Opportunity for open and

mainframe workloads Value statement:

Flexibility to deployapplications to bestenvironment

Reduce MSUs and SW costs

Reduced operating expenses

Tighter integration

Traditional z/OSApplications and ISV SW

Front End Modern Applications

And Migration

z/OS and Middleware

Customer Applications

System Management

Linux/Windows/Unix

Middleware

Customer Applications

System Management

Integration


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PSI System Demo

PSI System Overview


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PSI System Overview

Demonstration Workload


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Demonstration Workload

Base Control Program (BCP)

DFSMSdfp Data Facility System Managed Storage DFSMSdss Data Set Services DFSORT Data Facility Sort ICKDSF Device Support Facilities

FFST First Failure Support Technology LE Language Environment HLASM High Level Assembler C/C++ IBM Open Class Library TSO / ISPF / SDSF JES2 Lob Entry Subsystem RMF Resource Measurement Facility DB2, CICS, TPNS Transactions

Customer Advantage


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Customer Advantage

PSIprovides z/OS application portability on an

Open Systems Mainframe giving usersadded flexibility for exploiting emergingarchitectures.

Summary


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Summary

Choice and Flexibility

Compatibility and Innovation

Competitive Spirit

Trusted Partner

PSIprovides z/OS application portability on an Open Systems Mainframegiving users added flexibility for exploiting emerging architectures.


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Back up Slides onVirtualization

Realization Technology Basic Approaches


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Realization Technology Basic Approaches

Static Translated Code (prior to run-time): Object Code Translation - compiled with legacy binary as

source.

API mapping - Legacy OS functions mapped to native OS calls.

Dynamic Execution Code (during run-time): Interpreter - Each legacy instruction fetched, parsed, and

executed.

JIT - Piecemeal object code translation and cachingon the fly.

FIRMWARE-BASED HARDWARE VIRTUALIZATION

STATIC

OBJECT CODETRANSLATION

API MAPPING

DYNAMIC

INTERPRETER JIT CACHEDTRANSLATION

Interpretation Typical Low Performing Approach toTranslation


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Translation

120 DATA1 DC X005390BC

DC X09C20004

128 DATA2 DC X0009

12A DATA3 DC X800039AF

110 SRA R1,1

114 SH R2,DATA2

118 AR R1,R211A BC TARGET

100 START BALR B1,R0

102 BASE LM R1,R2,DATA1

106 MVC DATA1,DATA3

10C AH R1,DATA2

LEGACY CODE

BRTBL B INVLD

B O1_OP

B INVLD

B INVLD

B SPM

B BALR

B BCTR. . .

INIT LD8 PC PGM_CNTR

LD8 GR GEN_REGS

MOV BT BRTBL

NEXT LD1 OC [PC]

ADD PC PC,1

SHL OC 4

ADD OC OC,BTB [OC]

INVLD. . .

O1_OP. . .

SPM. . .

BALR LD1 R1 [PC]

ADD PC PC,1

AND R2 R1,0x0F

AND R1 R1,0xF0SHL R2 4

ADD R1 R1,GR

ST4 PC [R1]

CMP R2,0

BE NEXT

. . .

BCTR . . .

. . .

INTERPRETER

PSI High Performing JIT Binary Translation


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PSI High Performing JIT Binary Translation

110 SRA R1,1

114 SH R2,DATA2

118 AR R1,R2

11A BC TARGET


102 BASE LM R1,R2,DATA1

106 MVC DATA1,DATA3

10C AH R1,DATA2

TRANSLATED T-CODE

SRA SHR R1 1

SH ADD A1 B1,DATA2-BASE

LD2 T1 [A1]

SUB R2 R2,T1

AR ADD R1 R1,R2BC ADD A1 B1,TARGET-

BASE

B XFER_BRANCH

BALR MOV B1 BASE

LM ADD A1 B1,DATA1-BASE

LD4 R1 [A1]

ADD A1 A1,4

LD4 R2 [A1]

MVC ADD A1 B1,DATA1-BASE

ADD A2 B1,DATA3-BASE

LD4 T1 [A2]

ST4 T1 [A1]

AH ADD A1 B1,DATA2-BASELD2 T1 [A1]

ADD R1 R1,T1

B XFER_SEQUENTIAL

LEGACY CODE


DC X09C20004

128 DATA2 DC X0009


JIT Translation - Self-modifying Code


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JIT Translation Self modifying Code

TRANSLATED (RISC) CODE


DC X09C20004128 DATA2 DC X0009

12A NEWINST AH R2,DATA2

110 SRA R1,1114 OLDINST SH R2,DATA2118 AR R1,R2

11A BC TARGET

100 START BALR B1,R0102 BASE LM R1,R2,DATA1106 MVC OLDINST,NEWINST

10A AH R1,DATA2


102 BASE LM R1,R2,DATA1106 MVC OLDINST,NEWINST10A AH R1,DATA2


DC X09C20004128 DATA2 DC X0009


110 SRA R1,1114 SH R2,DATA2118 AR R1,R2

11A BC TARGET

100 START BALR B1,R0102 BASE LM R1,R2,DATA1106 MVC OLDINST,NEWINST

10C AH R1,DATA2


102 BASE LM R1,R2,DATA1106 MVC OLDINST,NEWINST10C AH R1,DATA2

120 DATA1 DC X005390BCDC X09C20004

128 DATA2 DC X0009

12A NEWINST SLA R2 4

110 SRA R1,1114 OLDINST SH R2,DATA2



SRA SHR R1 1

SH ADD A1 B1,DATA2-BASELD2 T1 [A1]SUB R2 R2,T1

AR ADD R1 R1,R2BC ADD A1 B1,TARGET-BASE

B XFER_BRANCH

BALR MOV B1 BASE

LM ADD A1 B1,DATA1-BASELD4 R1 [A1]ADD A1 A1,4LD4 R2 [A1]

MVC ADD A1 B1,OLDINST-BASE

ADD A2 B1,NEWINST-BASESHR A3 A1,4

AND A3 A3,0xFADD A3 A3,TABLELD4 T1 [A2]ST4 T1 [A1]LD1 T2 [A3]

CMP T2,0BNE CHK_MODIFIED

AH ADD A1 B1,DATA2-BASE

LD2 T1 [A1]ADD R1 R1,T1

B XFER_SEQUENTIAL

0 1

1 1

2 0

3 0

4 0

5 0

6 0

7 0

8 0

9 0

A 0

B 0

C 0

D 0

E 0

F 0

LEGACY (S/390) CODE TABLELEGACY (CISC) CODE

1

2

3

4

5

JIT Translation State-specific Variants


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p

SRA SHR R1 1

SH ADD A1 B1,DATA2-BASELD2 T1 [A1]

SUB R2 R2,T1AR ADD R1 R1,R2BC ADD A1 B1,TARGET-BASE

B XFER_BRANCH

BALR MOV B1 BASE

LM ADD A1 B1,DATA1-BASELD4 R1 [A1]

ADD A1 A1,4LD4 R2 [A1]


ADD A2 B1,DATA3-BASELD4 T1 [A2]

ST4 T1 [A1]AH ADD A1 B1,DATA2-BASE

LD2 T1 [A1]ADD R1 R1,T1B XFER_SEQUENTIAL

0F0 TM PERFLAG

0F4 BNE START0F8 SSM ENBLPER

0FC LCTL CR9,STOREPER

120 DATA1 DC X005390BCDC X09C20004

128 DATA2 DC X0009


110 SRA R1,1114 SH R2,DATA2



102 BASE LM R1,R2,DATA1106 MVC DATA1,DATA3

10C AH R1,DATA2


LEGACY (CISC) CODE

0000000000000000 (PER OFF)

BALR MOV B1 BASELM ADD A1 B1,DATA1-BASE

LD4 R1 [A1]


MVC ADD A1 B1,DATA1-BASEADD A2 B1,DATA3-BASE

LD4 T1 [A2]ST4 T1 [A1]CMP A1,C10BLT AH

CMP A1,C11BGT AH

B PER_RUPTAH ADD A1 B1,DATA2-BASE

LD2 T1 [A1]

ADD R1 R1,T1B XFER_SEQUENTIAL

0000000000000000 (PER OFF)

SRA SHR R1 1

SH ADD A1 B1,DATA2-BASELD2 T1 [A1]SUB R2 R2,T1

AR ADD R1 R1,R2BC ADD A1 B1,TARGET-BASE

B XFER_BRANCH

0000000000004200 (PER ON)

0000000000004200 (PER ON)

STATE = 0000000000004200

JIT Translation - Memory Address Prediction


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y

110 SRA R1,1

114 SH R2,DATA2118 AR R1,R2

11A BC TARGET


SRA SHR R1 1

SH ADD A1 B1,DATA2-BASELD2 T1 [A1]

SUB R2 R2,T1AR ADD R1 R1,R2BC ADD A1 B1,TARGET-BASE

B XFER_BRANCH

LEGACY (CISC) CODE

BALR MOV B1 BASE



MVC B RESUME_TRANSLATION

. . .

BALR MOV B1 BASELM ADD A1 B1,DATA1-BASE

LD4 R1 [A1]


MVC ADD A1 B1,DATA1-BASEADD A2 B1,DATA3-BASE

LD2 T1 [A2]ADD A2 A2,2LD2 T2 [A2}

SHL T1 T1,16OR T1 T1,T2

ST4 T1 [A1]AH ADD A1 B1,DATA2-BASE

LD2 T1 [A1]

ADD R1 R1,T1B XFER_SEQUENTIAL


102 BASE LM R1,R2,DATA1106 MVC . . .

. . . DATA1,DATA3

10C AH R1,DATA2


DC X09C20004128 DATA2 DC X0009


JIT Translation Flexible Caching


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g

LINK

SRA SHR R1 1SH ADD A1 B1,DATA2-BASE

LD2 T1 [A1]

SUB R2 R2,T1AR ADD R1 R1,R2BC B TARGET

LINK

LINK

LINK


DC X09C20004128 DATA2 DC X0009


110 SRA R1,1114 SH R2,DATA2

118 AR R1,R2

11A BC TARGET

TRANSLATED (RISC) CODELEGACY (CISC) CODE


102 BASE LM R1,R2,DATA1106 MVC DATA1,DATA3

10C AH R1,DATA2

BALR MOV B1 BASE


ADD A1 A1,4

LD4 R2 [A1]B MVC


ADD A2 B1,DATA3-BASE

LD4 T1 [A2]

ST4 T1 [A1]B AH

AH ADD A1 B1,DATA2-BASE

LD2 T1 [A1]ADD R1 R1,T1B SRA

...

Instruction Distribution is the Key


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y

10% of theinstructionsaccount for80% of those

executed.

Tuning primalset ofinstructionsallows

exploitationhost machineat nativespeeds. 0 50 100 150 200 250

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tedCode

25

Instructions

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Instructions

RISCarchitectureshave effectivelyreplaced moreexpensivespecial machine

architectures,the PSI virtualprocessor canexploit the IAtechnology inhosting othermachine

environments.

Performance tuning of the PrimalInstruction Set

INSTRCOUN

T OPCD MNEM NOTES TSO FREQ CUML FREQ1 58 L DBLWRD AL 0.154052697 0.1540526972 47 BC COND TKN 0.092450036 0.2465027323 47 BC COND .TKN 0.082462528 0.328965264 50 ST DBLWRD AL 0.071421671 0.4003869315 91 TM MASK=77 0.057172258 0.4575591896 41 LA LA 3,4(3) 0.051781982 0.5093411717 18 LR LR 6,4 0.051300283 0.5606414548 1F SLR 370-17 0.028331156 0.5889726119 2 MVC L=8&.OVLP 0.021513292 0.610485902

10 12 LTR R2>0 0.021322849 0.63180875111 1E ALR 370+17 0.019755109 0.6515638612 5E AL 1387+48 0.018955566 0.67051942513 BF ICM MASK = C 0.0186 0.68916942514 48 LH DBLWRD AL 0.015491222 0.70466064715 96 1 MASK=7C 0.014900326 0.71956097416 94 NI MASK=C7 0.014566785 0.73412775917 98 LM LM 0,10 0.014251283 0.74837904118 7 BCR TAKEN 0.013875519 0.7622545619 D5 CLC L=8&.OVLP 0.013616677 0.77587123720 95 CLI MASK=C7 0.011222828 0.78709406521 90 STM STM 0,15 0.010872599 0.79796666422 43 IC DBLWRD AL 0.010836294 0.80880295723 54 N OP1=OP2 0.010751272 0.8195542324 55 CL OP1=OP2 0.009797534 0.82935176425 19 CR CR 6,4 0.008133045 0.83748480926 92 MVI DBLWRD AL 0.007884764 0.84536957227 15 CLR 3,5/R3=R5 0.007097957 0.85246752928 59 C OP1=OP2 0.006786195 0.85925372529 B20A SPKA KEY=O 0.006460318 0.86571404230 40 STH DBLWRD AL 0.006204943 0.87191898531 5 BALR TAKEN 0.005875299 0.87779428432 45 BAL 4,16(0,5) 0.005758106 0.8835523933 D7 XC L=8&.OVLP 0.005569686 0.88912207634 B6 STCTL STCTL O,F 0.005228056 0.89435013235 5F SL 1387-48 0.004980784 0.89933091636 42 STC DBLWRD AL 0.004953682 0.90428459737 6 BCTR R21S 0 0.004907376 0.90919197338 89 SLL 8 BITS 0.004636619 0.91382859239 5A A 1387+48 0.00455022 0.91837881240 8B SLA 8 BITS 0.003862383 0.92224119541 88 SRL 8 BITS 0.00383774 0.92607893542 BA CS OP1=OP2 0.00375952 0.92983845543 0B BSM TAKEN 0.003629467 0.93346792244 49 CH DBLWRD AL 0.003612157 0.93708007845 AF MC NO RUPT 0.003516373 0.94059645246 1B SR 370-17 0.002811749 0.94340820147 5 BALR R2 IS 0 0.002687654 0.94609585548 4A AH 1387+48 0.002319776 0.94841563149 16 OR 3,5/R3=R5 0.001930803 0.95034643450 4C MH 1387*48 0.001920703 0.952267137

Components of Performance


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p

z/Architecture CPI = E + S + T E-term = T-code Execution cycles per dynamic z/Architecture instruction

(end-op) S-term = T-code Storage (cache/bus) cycles per z/Architecture end-op T-term = Translation cycles (Execution and Storage) per z/Architecture

end-op

T = I/R = I*M

I = Initial Translation cycles per static z/Architecture instruction R = Instruction Re-use rate = 50-100 times M = T-cache Miss rate = 1-2%

S-term effects Code expansion - linear effect on miss rate

Data expansion - square-root effect Frequency of Translator invocations Duration of Translator invocations

JIT Translation Direct Branching


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g

Branch base register tends to be static

If branch base register is unmodified, targetstream is queued for translation

Translation continues until all queued streamsare exhausted

T-cache entries that share a common baseregister are logically grouped together

Branch base register contents are checked

whenever a logical group is entered

Customer Presentation Jan 2006 v2

Documents

Transcript of Customer Presentation Jan 2006 v2