Electronics Engineer

Daniel Domínguez Ramírez

Address: Bronce #370 int. 58, Col. El Fortin, Zapopan, Jalisco.Email:daniel.doram@gmail.com

Phone: +52 1 (33) 15754713.

Education:

· Master of Science on Electronics Design.Instituto Tecnológico de Estudios Superiores de Occidente (ITESO)Guadalajara, Jalisco, México. (Thesis on going 2011-2016)

· Post-Graduate Diploma on Integrated Circuits DesignInstituto Tecnológico de Estudios Superiores de Occidente (ITESO)Guadalajara, Jalisco, México. (2007 - 2008)

· Bachelor of Science on Electronics Engineer Instituto Tecnológico de Estudios Superiores de Occidente (ITESO)Guadalajara, Jalisco, México. (2001-2005)

Skills:

- 8 yrs. experience in analog/digital custom layout.- PERL/TCL scripting (Intermediate).- Digital/analog design validation (Timing/RV/PV).- Experienced in UNIX operating System.- Circuit design experience in high performance and low power IC designs- 2 yrs. experience in ICC layout tools.- Development of layout methodologies.- Development of automation tools. - Excellent debugging skills.- Experience in ASIC integration, including floor-planning, clock and power distribution and global signal

planning.

Languages: English – Fluent speaker.Spanish – Native speaker.

Professional Experience:

Physical Design Engineer INTEL (April 2008 - Present)Layout design and verification for custom Analog and Digital circuits (Clock circuits, PLLs, IO pads, register files, etc.).

Many Integrated Core projects:RF Assembly layout (digital). Deliver 15 analog custom blocks with high quality, many of the sub blocks were made from scratch. Such as IOs circuits, clock generation circuits, clock mux, etc.Delivered 4 high complex clock channels blocks for analog blocks consumption. Worked closely with DE to meet all requirements for PV/RV/Integration.

Graphic Projects:Delivered 320 RFs for all projects through RFA (RF Automation tool). Owned timing/RV/PV/FEV validation for all the blocks. Delivered feedback for layout performance improvements.Design and simulation of memory cells (circuit/layout) for using in all RFs flavors.

Responsible of delivering ~30 blocks with TI quality through different projects stepping. Work consisted LV cleanup, implementation of different scripts to solve DRCs automatically. Worked closely with Process Owners to improve LV methodologies, repetitive DRC errors, find floor plan issues before data bases were delivered to LV cleanup, worked with clock team to improve their routings for timing/ RV/FV.

FEV for graphic project:Member of team that delivered around 100 blocks FEV passed using LEC tool. The team created and delivered .do map files to make the blocks match logically with RTL. Blocks included (Iscan, scanout, LCP) logics for testing.